CN108063137B - Transient voltage suppressor and manufacturing method thereof - Google Patents

Abstract

The invention relates to a transient voltage suppressor and a manufacturing method thereof. The transient voltage suppressor includes an N-type substrate, a first trench and a second trench formed on the surface of the N-type substrate, and first and second P-type diffusions formed on the surface of the first and second trenches region, an N-type epitaxy formed on the surface of the N-type substrate and the first and second P-type diffusion regions, a silicon oxide layer formed on the N-type epitaxy, penetrating the N-type epitaxy and extending into the N-type substrate and Two third trenches on both sides of the first P-type diffusion region, two fourth trenches on both sides of the N-type epitaxy and extending to the N-type substrate and the second P-type diffusion region, located at the third and fourth Silicon oxide in the trench, a first through hole corresponding to the first trench, a second through hole corresponding to the second trench, a P-type implantation region formed on the surface of the N-type epitaxial layer and extending into the N-type substrate, An N-type implanted region formed on the surface of the P-type implanted region, an opening corresponding to the N-type implanted region, and a P-type implanted layer formed on the other side of the N-type substrate.

Description

Transient voltage suppressor and method of making the same

【Technical field】

The present invention relates to the technical field of semiconductor device manufacturing, and in particular, to a transient voltage suppressor and a manufacturing method thereof.

【Background technique】

Transient Voltage Suppressor (TVS) is a solid-state semiconductor device specially designed to protect sensitive semiconductor devices from damage by transient voltage surges. It has the advantages of small current and high reliability, so it has been widely used in voltage transient and surge protection. The low-capacitance transient voltage suppressor is suitable for protection devices of high-frequency circuits, because it can reduce the interference of parasitic capacitance on the circuit and reduce the attenuation of high-frequency circuit signals.

Electrostatic discharge (ESD) and some other random voltage transients in the form of voltage surges, commonly found in various electronic devices. As semiconductor devices become increasingly miniaturized, dense, and multi-functional, electronic devices are increasingly vulnerable to voltage surges, which can even lead to fatal injuries. Voltage surges ranging from electrostatic discharge to lightning can induce transient current spikes, and transient voltage suppressors are often used to protect sensitive circuits from surges. Depending on the application, a transient voltage suppressor can protect the circuit by changing the surge discharge path and its own clamping voltage. In order to save chip area and obtain higher surge immunity, the concept of trench transient voltage suppressor has been proposed and studied. The junction surface of the trench TVS is formed on the sidewall of the longitudinal trench, so that, under the same chip area, it has more effective junction area, that is, stronger discharge capacity. The small package size of trench TVS is critical for protecting high-end chips.

Currently commonly used transient voltage suppressors (such as trench transient voltage suppressors) generally can only achieve unidirectional protection. If bidirectional protection is required, multiple transient voltage suppressors need to be connected in series or in parallel, but this will increase the number of transient voltage suppressors. Larger device area and manufacturing cost.

[Content of the invention]

Aiming at the deficiencies of the existing methods, the present invention provides a transient voltage suppressor and a manufacturing method thereof.

A transient voltage suppressor comprising an N-type substrate, a first trench and a second trench formed on the surface of the N-type substrate, and a first P-type diffusion formed on the surface of the first trench The second P-type diffusion region formed on the surface of the second trench, the N-type epitaxy formed on the surface of the N-type substrate and the first and second P-type diffusion regions, and the N-type diffusion region formed on the surface of the N-type a silicon oxide layer on the epitaxy, through the N-type epitaxy and extending to two third trenches in the N-type substrate and on both sides of the first P-type diffusion region, through the N-type epitaxy and extending to two fourth trenches on both sides of the N-type substrate and the second P-type diffusion region, the silicon oxide in the third trench, the silicon oxide in the fourth trench, A first through hole corresponding to the first trench and penetrating the silicon oxide layer, a second through hole corresponding to the second trench and penetrating the silicon oxide layer, formed on the surface of the N-type epitaxial layer and A P-type implanted region extending into the N-type substrate, an N-type implanted region formed on the surface of the P-type implanted region, an opening through the silicon oxide layer corresponding to the N-type implanted region, and an opening formed in the N-type implanted region The N-type substrate is away from the P-type implantation layer on the side of the N-type epitaxy.

In one embodiment, the transient voltage suppressor further includes a first metal layer formed on the silicon oxide layer and the silicon oxide and passing through the first via and all the The second through hole is connected to the N-type epitaxy on the first trench and the second trench, and the first metal layer is also connected to the N-type implantation region through the opening.

In one embodiment, the transient voltage suppressor further includes a second metal layer, and the second metal layer is formed on the surface of the P-type implanted layer away from the N-type substrate and the N-type substrate Bottom connection.

In one embodiment, the P-type implanted region is located between the two third trenches and the two fourth trenches.

In one embodiment, the depth of the third trench in the N-type substrate is less than the depth of the first trench, and the depth of the fourth trench in the N-type substrate is less than the depth of the second trench.

A method for manufacturing a transient voltage suppressor, comprising the following steps:

An N-type substrate is provided, an oxide layer is formed on the N-type substrate, the oxide layer is etched using a first photoresist as a mask, and the N-type substrate is formed through the oxide layer and extending to the N a first trench and a second trench in the type substrate;

performing P-type diffusion to form a first P-type diffusion region on the surface of the first trench and a second P-type diffusion region on the surface of the second trench;

removing the oxide layer to form an N-type epitaxy in the N-type substrate, the first trench and the second trench in the first and second P-type diffusion regions;

A silicon oxide layer is formed on the surface of the N-type epitaxy away from the N-type substrate, and two sides corresponding to the first P-type diffusion region are formed through the silicon oxide layer, the N-type epitaxy and extending to the Two third trenches on both sides of the n-type substrate and the first P-type diffusion region are formed through the silicon oxide layer, the N-type epitaxy and extend corresponding to the two sides of the second P-type diffusion region. to two fourth trenches on both sides of the n-type substrate and the second p-type diffusion region;

filling the two third trenches and the two fourth trenches with silicon oxide;

etching the silicon oxide layer with a second photoresist, thereby forming an opening through the silicon oxide layer, and using the opening to perform P-type ion implantation on the N-type epitaxy;

thermally annealing a P-type implanted region corresponding to the opening and extending from the N-type epitaxy to the N-type substrate; and

forming a first through hole through the silicon oxide layer and corresponding to the first trench and a second through hole through the silicon oxide layer and corresponding to the second trench;

A P-type implantation layer is formed on the N-type substrate away from the N-type epitaxial surface.

In one embodiment, the method further comprises the steps of:

A first metal layer is formed on the silicon oxide layer, the first metal layer is connected to the N-type epitaxy through the first through hole and the second through hole, and the first metal layer also passes through the An opening is connected to the N-type implanted region.

In an embodiment, grinding and thinning the N-type substrate away from the N-type epitaxial surface is performed to form the P-type implantation layer, on the surface of the P-type implantation layer away from the N-type substrate A second metal layer is formed.

In one embodiment, the P-type implanted region is located between the two third trenches and the two fourth trenches.

In one embodiment, the depth of the third trench in the N-type substrate is less than the depth of the first trench, and the depth of the fourth trench in the N-type substrate is less than the depth of the second trench.

The transient voltage suppressor of the present invention and the transient voltage suppressor obtained by the manufacturing method, on the basis of the traditional structure, are improved to integrate multiple diodes together, and the two groups of diodes connected in reverse series reduce the device capacitance , the introduction of a unidirectional diode reduces the reliability problems caused by high current during use. The improved transient voltage suppressor can realize dual bidirectional protection function, and the protection characteristics and reliability of the device have been improved.

Further, the P-type injection region can undergo multiple thermal processes, the junction is deep, the P-type concentration is low, and the breakdown voltage of the PN junction is very high, so it does not actually work within the working range of the device, so The equivalent circuit is not drawn, but the purpose of setting this structure is to quickly leak current so as not to burn the system in some extreme cases (the device temperature is very high, which leads to thermal breakdown of the PN junction), and it can also improve the normal operation of the device. thermal resistance coefficient.

【Description of drawings】

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, under the premise of no creative work, other drawings can also be obtained from these drawings, wherein:

FIG. 1 is a schematic structural diagram of a transient motion suppressor of the present invention.

FIG. 2 is a schematic diagram of an equivalent circuit of the transient voltage suppressor shown in FIG. 1 .

FIG. 3 is a flowchart of a method for fabricating the transient voltage suppressor shown in FIG. 1 .

4-12 are schematic structural diagrams of each step of the manufacturing method shown in FIG. 3 .

【Description of main component symbols】

Transient voltage suppressor 100; diodes 101, 102, 103, 104, 105; steps S1-S10

【Detailed ways】

The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Please refer to FIG. 1 , which is a schematic structural diagram of a transient voltage suppressor 100 of the present invention. The transient voltage suppressor 100 includes an N-type substrate, a first trench and a second trench formed on the surface of the N-type substrate, and a first P-type diffusion region formed on the surface of the first trench The second P-type diffusion region formed on the surface of the second trench, the N-type epitaxy formed on the surface of the N-type substrate and the first and second P-type diffusion regions, and the N-type epitaxy formed on the surface the silicon oxide layer on the N-type epitaxy, extending through the N-type epitaxy and extending to two third trenches in the N-type substrate and on both sides of the first P-type diffusion region, penetrating the N-type epitaxy and extending to The N-type substrate corresponds to the two fourth trenches on both sides of the second P-type diffusion region, the silicon oxide in the third trench, the silicon oxide in the fourth trench, The first trench and a first through hole passing through the silicon oxide layer, a second through hole corresponding to the second trench and passing through the silicon oxide layer, are formed on the surface of the N-type epitaxial layer and extend into a P-type implanted region in the N-type substrate, an N-type implanted region formed on the surface of the P-type implanted region, an opening through the silicon oxide layer and corresponding to the N-type implanted region, formed in the The P-type implantation layer, the first metal layer and the second metal layer on the side of the N-type substrate away from the N-type epitaxy.

Wherein, the first metal layer is formed on the silicon oxide layer and the silicon oxide and passes through the first through hole and the second through hole and the first trench and the second trench. N-type epitaxial connection, and the first metal layer is also connected to the N-type implantation region through the opening. The second metal layer is formed on the surface of the P-type implanted layer away from the N-type substrate and is connected to the N-type substrate.

Further, in this embodiment, the P-type implanted region is located between the two third trenches and the two fourth trenches. The depth of the third trench in the N-type substrate is smaller than that of the first trench, and the depth of the fourth trench in the N-type substrate is smaller than that of the second trench depth.

Please refer to FIG. 2 , which is a schematic diagram of an equivalent circuit of the transient voltage suppressor 100 shown in FIG. 1 . The P-type implanted region and the N-type substrate form a first diode 101, and the N-type substrate and the P-type diffusion region in the first trench form a first diode 102. The first diode 102 The P-type diffusion region in the trench and the N-type epitaxy in the first trench constitute a third diode 103; the N-type substrate and the P-type diffusion region in the second trench also constitute a third diode 103. The tetrode 104 , the P-type diffusion region in the second trench and the N-type epitaxy in the second trench form the fifth diode 105 .

Please refer to FIGS. 3 to 10 . FIG. 3 is a flowchart of the manufacturing method of the transient voltage suppressor 100 shown in FIG. 1 , and FIGS. 4 to 10 are schematic structural diagrams of each step of the manufacturing method shown in FIG. 3 .

The manufacturing method of the transient voltage suppressor 100 includes the following steps S1-S10.

Step S1, please refer to FIG. 4, providing an N-type substrate, forming an oxide layer on the N-type substrate, using the first photoresist as a mask to etch the oxide layer and forming the N-type substrate through the N-type substrate. The oxide layer extends to the first trench and the second trench in the N-type substrate. The etching may be dry etching. The material of the oxide layer may be silicon oxide.

Step S2 , referring to FIG. 5 , performs P-type diffusion to form a first P-type diffusion region on the surface of the first trench and a second P-type diffusion region on the surface of the second trench.

Step S3, referring to FIG. 6, remove the oxide layer, and form N-type epitaxy in the N-type substrate, the first trench and the second trench of the first and second P-type diffusion regions .

Step S4, referring to FIG. 7, a silicon oxide layer is formed on the surface of the N-type epitaxy away from the N-type substrate, and two sides corresponding to the first P-type diffusion region are formed through the silicon oxide layer, the N-type epitaxy extends to the n-type substrate and two third trenches on both sides of the first P-type diffusion region, and forms through the silicon oxide layer corresponding to both sides of the second P-type diffusion region , the N-type epitaxy extends to the two fourth trenches on both sides of the n-type substrate and the second P-type diffusion region. The third and fourth trenches may be formed by dry etching using a photoresist as a mask.

In step S5, referring to FIG. 8, the two third trenches and the two fourth trenches are filled with silicon oxide.

In step S6 , referring to FIG. 9 , the silicon oxide layer is etched with a second photoresist, thereby forming an opening through the silicon oxide layer, and the N-type epitaxy is used to perform P-type ion implantation on the N-type epitaxy. The etching may also be dry etching.

In step S7, referring to FIG. 10, thermal annealing is performed so as to correspond to the opening and extend from the N-type epitaxy to the P-type implanted region in the N-type substrate.

Step S8 , referring to FIG. 11 , a first through hole penetrating the silicon oxide layer and corresponding to the first trench and a second through hole penetrating the silicon oxide layer and corresponding to the second trench are formed.

Step S9, please refer to FIG. 12, a first metal layer is formed on the silicon oxide layer, the first metal layer is connected to the N-type epitaxy through the first through hole and the second through hole, the The first metal layer is also connected to the N-type implantation region through the opening.

Step S10, referring to FIG. 1, grinding and thinning the N-type substrate away from the N-type epitaxial surface to form a P-type implantation layer, which is formed on the surface of the P-type implantation layer away from the N-type substrate second metal layer.

The transient voltage suppressor 100 of the present invention and the transient voltage suppressor 100 obtained by the manufacturing method, on the basis of the traditional structure, are improved to integrate multiple diodes together, and the two groups of diodes connected in reverse series reduce the Device capacitance, the introduction of a unidirectional diode reduces the reliability problems caused by high current during use. The improved transient voltage suppression, 100 can achieve dual bidirectional protection function, and the protection characteristics and reliability of the device have been improved.

Further, the P-type injection region can undergo multiple thermal processes, the junction is deep, the P-type concentration is low, and the breakdown voltage of the PN junction is very high, so it does not actually work within the working range of the device, so The equivalent circuit is not drawn, but the purpose of setting this structure is to quickly leak current so as not to burn the system in some extreme cases (the device temperature is very high, which leads to thermal breakdown of the PN junction), and it can also improve the normal operation of the device. thermal resistance coefficient.

The above are only the embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the inventive concept of the present invention, but these belong to the present invention. scope of protection.

Claims (10)

1. A transient voltage suppressor, characterized in that: the transient voltage suppressor comprises an N-type substrate, a first trench and a second trench formed on the surface of the N-type substrate, and a first trench and a second trench formed on the surface of the N-type substrate. the first P-type diffusion region on the surface of the first trench, the second P-type diffusion region formed on the surface of the second trench, the N-type substrate and the first and second P-type diffusion regions N-type epitaxy on the surface of the region, a silicon oxide layer formed on the N-type epitaxy, through the N-type epitaxy and extending to the two sides of the N-type substrate and the first P-type diffusion region A third trench, two fourth trenches penetrating the N-type epitaxy and extending to both sides of the N-type substrate and the second P-type diffusion region, and silicon oxide in the third trenches , a silicon oxide located in the fourth trench, a first through hole corresponding to the first trench and penetrating the silicon oxide layer, a second through hole corresponding to the second trench and penetrating the silicon oxide layer a via hole, a P-type implanted region formed on the surface of the N-type epitaxial layer and extending into the N-type substrate, an N-type implanted region formed on the surface of the P-type implanted region, penetrating the silicon oxide layer, and An opening corresponding to the N-type implantation region and a P-type implantation layer formed on the side of the N-type substrate away from the N-type epitaxy. 2 . The transient voltage suppressor of claim 1 , wherein the transient voltage suppressor further comprises a first metal layer, the first metal layer is formed on the silicon oxide layer and passes through the The first through hole and the second through hole are connected with the N-type epitaxy on the first trench and the second trench, and the first metal layer is also connected with the N-type implantation region through the opening . 3. The transient voltage suppressor of claim 2, wherein the transient voltage suppressor further comprises a second metal layer, the second metal layer is formed on the P-type injection layer away from the The surface of the N-type substrate. 4 . The transient voltage suppressor of claim 1 , wherein the P-type implant region is located between the two third trenches and the two fourth trenches. 5 . 5 . The transient voltage suppressor of claim 1 , wherein the depth of the third trench in the N-type substrate is smaller than the depth of the first trench, and the fourth trench The depth of the trench in the N-type substrate is less than the depth of the second trench. 6. A method for making a transient voltage suppressor, wherein the method comprises the following steps: An N-type substrate is provided, an oxide layer is formed on the N-type substrate, the oxide layer is etched using a first photoresist as a mask, and the N-type substrate is formed through the oxide layer and extending to the N a first trench and a second trench in the type substrate; performing P-type diffusion to form a first P-type diffusion region on the surface of the first trench and a second P-type diffusion region on the surface of the second trench; removing the oxide layer to form an N-type epitaxy in the N-type substrate, the first trench and the second trench in the first and second P-type diffusion regions; A silicon oxide layer is formed on the surface of the N-type epitaxy away from the N-type substrate, and two sides corresponding to the first P-type diffusion region are formed through the silicon oxide layer, the N-type epitaxy and extending to the Two third trenches on both sides of the N-type substrate and the first P-type diffusion region are formed corresponding to the two sides of the second P-type diffusion region through the silicon oxide layer, the N-type epitaxy and extending to two fourth trenches on both sides of the N-type substrate and the second P-type diffusion region; filling the two third trenches and the two fourth trenches with silicon oxide; etching the silicon oxide layer with a second photoresist, thereby forming an opening through the silicon oxide layer, and using the opening to perform P-type ion implantation on the N-type epitaxy; thermally annealing a P-type implanted region corresponding to the opening and extending from the N-type epitaxy to the N-type substrate; forming a first via through the silicon oxide layer and corresponding to the first trench and a second via through the silicon oxide layer and corresponding to the second trench; and A P-type implantation layer is formed on the N-type substrate away from the N-type epitaxial surface. 7. The method for making a transient voltage suppressor according to claim 6, wherein the method further comprises the following steps: A first metal layer is formed on the silicon oxide layer, the first metal layer is connected to the N-type epitaxy through the first through hole and the second through hole, and the first metal layer also passes through the An opening is connected to the N-type implanted region. 8. the manufacture method of transient voltage suppressor as claimed in claim 7, is characterized in that: described method also comprises the following steps: carry out grinding thinning to described N-type substrate away from described N-type epitaxial surface and then form In the P-type injection layer, a second metal layer is formed on the surface of the P-type injection layer away from the N-type substrate. 9 . The method for fabricating a transient voltage suppressor according to claim 6 , wherein the P-type implantation region is located between the two third trenches and the two fourth trenches. 10 . 10 . The method for fabricating a transient voltage suppressor according to claim 6 , wherein the depth of the third trench in the N-type substrate is smaller than the depth of the first trench, and the depth of the first trench is 10 . The depth of the fourth trench in the N-type substrate is smaller than the depth of the second trench.

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