CN108122757B - Semiconductor structure and method of making the same - Google Patents

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. In the manufacturing method of the semiconductor structure provided by the present invention, it includes providing a substrate; forming a fin structure on the substrate; forming a silicon germanium layer on both sides of the fin structure exposed on the substrate; A spacer is formed on the side of the silicon germanium layer away from the fin structure; a first gate metal layer is formed on the side of the spacer away from the silicon germanium layer; and a first gate metal layer is formed on the first gate metal layer A ferroelectric layer is formed on a side away from the spacer; and a second gate metal layer is formed on a side of the ferroelectric layer away from the first gate metal layer. The semiconductor structure thus obtained can improve the situation of short channel damage (SCE) caused by the high dopant concentration of the short channel in the prior art, and can reduce the contact resistance, so as to obtain more The low power supply voltage (Vdd) significantly improves the performance of the semiconductor structure.

Description

Semiconductor structure and method of making the same

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.

Background technique

In the advanced complementary metal-oxide-semiconductor (CMOS) industry, with the arrival of 22nm and smaller dimensions, in order to improve the short-channel effect and improve the performance of the device, the Fin Field-effect transistor (FinFET) is composed of Its unique structure is widely adopted.

FinFET is a special metal-oxide-semiconductor field-effect transistor whose structure is usually formed on a silicon-on-insulator substrate, including narrow and independent silicon strips as a vertical channel structure, also known as a fin, in the fin Gate structures are provided on both sides of the . Specifically, as shown in FIG. 1 , a FinFET structure in the prior art includes: a substrate 10 , a source electrode 11 , a drain electrode 12 , a fin 13 , and a gate structure 14 surrounding and above the fin 13 .

However, FinFETs still have areas that need to be improved, such as high contact resistance and short-channel damage during fabrication.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which can improve short channel damage and reduce contact resistance.

In order to solve the technical problem, the present invention provides a method for manufacturing a semiconductor structure, including:

providing a substrate;

forming a fin structure on the substrate;

forming silicon germanium layers on both sides of the exposed fin structure on the substrate;

forming a spacer on a side of the silicon germanium layer away from the fin structure;

forming a first gate metal layer on the side of the spacer away from the silicon germanium layer;

forming a ferroelectric layer on a side of the first gate metal layer facing away from the spacer; and

A second gate metal layer is formed on the side of the ferroelectric layer away from the first gate metal layer.

Optionally, for the manufacturing method of the semiconductor structure, the width of the silicon germanium layer is 5 nm-50 nm.

Optionally, for the manufacturing method of the semiconductor structure, the substrate has a first oxide layer, the fin structure penetrates the first oxide layer, and the upper surface of the fin structure is higher than the the upper surface of the first oxide layer.

Optionally, for the manufacturing method of the semiconductor structure, the step of forming a spacer on the side of the silicon germanium layer away from the fin structure includes:

forming a mask layer on the fin structure;

forming a spacer material layer, the spacer material layer covering the mask layer, the silicon germanium layer and the first oxide layer;

forming a sacrificial layer covering the sidewall material layer;

removing the sacrificial layer and the spacer material layer on the first oxide layer, and removing the sacrificial layer above the mask layer, the remaining spacer material layer covers the mask layer and the silicon germanium layer, and the remaining sacrificial layer on the side of the sidewall material layer away from the silicon germanium layer;

forming a second oxide layer on the first oxide layer;

A portion of the sacrificial layer higher than the fin structure and a portion of the spacer material layer higher than the fin structure are removed to expose the mask layer, and the remaining spacer material layer forms a spacer.

Optionally, for the manufacturing method of the semiconductor structure, the step of forming a first gate metal layer on the side of the sidewall spacer away from the silicon germanium layer includes:

removing the sacrificial layer to form an opening;

A first gate metal layer is formed in the opening.

Optionally, for the manufacturing method of the semiconductor structure, the width of the first gate metal layer is

Optionally, for the manufacturing method of the semiconductor structure, the step of forming a ferroelectric layer on the side of the first gate metal layer away from the spacer includes:

reducing a part of the thickness of the second oxide layer;

Using an atomic layer deposition process to form a ferroelectric material layer on the second oxide layer;

The ferroelectric layer is formed by etching the ferroelectric material layer.

Optionally, for the manufacturing method of the semiconductor structure, the material of the ferroelectric layer is bismuth ferrite or lithium tantalate.

Optionally, for the manufacturing method of the semiconductor structure, the width of the ferroelectric layer is 1 nm-20 nm.

Optionally, for the manufacturing method of the semiconductor structure, the width of the second gate metal layer is

The present invention also provides a semiconductor structure, comprising:

a substrate,

a fin structure on the substrate;

silicon germanium layers on both sides of the fin structure exposed on the substrate;

a spacer on the side of the silicon germanium layer away from the fin structure;

a first gate metal layer on the side of the spacer away from the silicon germanium layer;

a ferroelectric layer on the side of the first gate metal layer facing away from the spacer;

a second gate metal layer on the side of the ferroelectric layer away from the first gate metal layer.

Optionally, for the semiconductor structure, the width of the silicon germanium layer is 5 nm-50 nm.

Optionally, for the semiconductor structure, the substrate has a first oxide layer, the fin structure penetrates the first oxide layer, and the upper surface of the fin structure is higher than the first oxide layer the upper surface of the layer.

Optionally, for the semiconductor structure, the width of the first gate metal layer is

Optionally, for the semiconductor structure, the material of the ferroelectric layer is bismuth ferrite or lithium tantalate.

Optionally, for the semiconductor structure, the ferroelectric layer has a width of 1 nm-20 nm.

Optionally, for the semiconductor structure, the width of the second gate metal layer is

The method for manufacturing a semiconductor structure provided by the present invention includes providing a substrate; forming a fin structure on the substrate; forming a silicon germanium layer on both sides of the fin structure exposed on the substrate; A sidewall spacer is formed on the side of the silicon germanium layer away from the fin structure; a first gate metal layer is formed on the side of the sidewall spacer away from the silicon germanium layer; and a first gate metal layer is formed on the side away from the first gate metal layer A ferroelectric layer is formed on one side of the spacer; and a second gate metal layer is formed on a side of the ferroelectric layer away from the first gate metal layer. The semiconductor structure thus obtained can improve the situation of short channel damage (SCE) caused by the high dopant concentration of the short channel in the prior art, and can reduce the contact resistance, so as to obtain more The low power supply voltage (Vdd) significantly improves the performance of the semiconductor structure.

Description of drawings

1 is a schematic diagram of a FinFET device structure in the prior art;

Fig. 2 is the flow chart of the manufacturing method of the semiconductor structure in the present invention;

3 is a schematic diagram of a substrate provided in an embodiment of the present invention;

4 is a schematic diagram of forming a fin structure in an embodiment of the present invention;

5 is a schematic diagram of forming silicon germanium layers on both sides of the fin structure in an embodiment of the present invention;

6-8 are schematic diagrams of forming sidewalls in an embodiment of the present invention;

9 is a schematic diagram of forming a first gate metal layer in an embodiment of the present invention;

10 is a schematic diagram of forming a ferroelectric layer in an embodiment of the present invention;

FIG. 11 is a schematic diagram of forming a second gate metal layer according to an embodiment of the present invention.

Detailed ways

The semiconductor structure of the present invention and its manufacturing method will be described in more detail below with reference to schematic diagrams, wherein preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still realize the present invention. beneficial effect. Therefore, the following description should be construed as widely known to those skilled in the art and not as a limitation of the present invention.

The invention is described in more detail by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present invention will become apparent from the following description and claims. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

The core idea of the present invention is to provide a method for fabricating a semiconductor structure, so as to improve the performance of the semiconductor structure (eg, a CMOS structure). The manufacturing method of the semiconductor structure includes:

Step S11, providing a substrate;

Step S12, forming a fin structure on the substrate;

Step S13, forming silicon germanium layers on both sides of the exposed fin structure on the substrate;

Step S14, forming a sidewall on the side of the silicon germanium layer away from the fin structure;

Step S15, forming a first gate metal layer on the side of the sidewall spacer away from the silicon germanium layer;

Step S16, forming a ferroelectric layer on the side of the first gate metal layer away from the spacer; and

Step S17, forming a second gate metal layer on the side of the ferroelectric layer away from the first gate metal layer.

The semiconductor structure and the manufacturing method thereof of the present invention will be described in detail below with reference to FIGS. 2 to 11 . 2 is a flowchart of a method for manufacturing a semiconductor structure in an embodiment of the present invention; FIGS. 3-11 are schematic structural diagrams of a method for manufacturing a semiconductor structure in an embodiment of the present invention during the manufacturing process.

Please refer to FIG. 2 and FIG. 3 , in the manufacturing method of the semiconductor structure of the present invention, specifically, for step S11 , the constituent material of the substrate 100 can be undoped single crystal silicon, impurity-doped single crystal silicon Crystalline silicon, silicon-on-insulator (SOI), etc. As an example, in this embodiment, the substrate 100 is made of a single crystal silicon material. A buried layer (not shown in the figure) and the like may also be formed in the substrate 100 . In addition, for PMOS, an N well (not shown in the figure) may also be formed in the substrate 100, and before the gate structure is formed, one or more small doses of boron implantation may be performed on the entire N well, Used to adjust the threshold voltage Vth of the PMOS.

As shown in FIG. 4 , the step S12 is to form the fin structure 102 on the substrate 100 ; specifically, a mask layer 101 may be formed on the substrate 100 first, and the mask layer is located on the At the area where the fin structure 102 is formed, the mask layer 101 is used as a mask to etch the substrate 100 to form a protrusion as the fin structure 102 , and then a first oxide is formed on the substrate 100 The layer 103 is, for example, silicon oxide, and the first oxide layer 103 can be formed by a deposition process or a thermal oxidation process. The first oxide layer 103 covers part of the thickness of the fin structure 102, that is, the fin structure 102 penetrates the first oxide layer 103, and the upper surface of the fin structure 102 is higher than the first oxide layer upper surface of layer 103 . According to needs, the fin structure 102 can also be heavily doped. Of course, the doping dose is not limited here, and those skilled in the art can flexibly choose according to needs.

Then, please refer to FIG. 5 , step S13 is to form a silicon germanium (SiGe) layer 104 on both sides of the fin structure 102 exposed on the substrate 100 ; this step S13 can be completed by using the prior art, such as using silicon-containing This is accomplished by chemical vapor deposition (CVD) of the gas with a germanium-containing gas. For example, the width of the silicon germanium layer 104 (ie, the dimension in the lateral direction as shown in the figure, the same below) can be 5 nm-50 nm, so as to better realize the effect of adjusting the stress.

Step S14 is to form a sidewall spacer 106 on the side of the silicon germanium layer 104 away from the fin structure 102 ; specifically, please refer to FIG. 6 , firstly, a sidewall material layer 1051 is formed, and the sidewall material layer 1051 covers the The mask layer 101 , the silicon germanium layer 104 and the first oxide layer 103 ; the spacer material layer 1051 is, for example, a high-K dielectric layer, and the dielectric constant can be greater than or equal to 10. Here, the spacer material layer 1051 is mainly formed near the silicon germanium layer 104 , as shown in FIG.

Then, a sacrificial layer 106 is formed, and the sacrificial layer 106 covers the spacer material layer 1051; in the embodiment of the present invention, the material of the sacrificial layer 106 is, for example, polysilicon, and the sacrificial layer 106 will be removed later, so as to After forming the first gate metal layer 108 (as shown in FIG. 9 ).

Of course, after the sidewall material layer 1051 is formed, a one-step etching process may be performed to remove a thin layer on the first oxide layer 103, and then the sacrificial layer 106 is formed.

Next, referring to FIG. 7 , the sacrificial layer 106 and the spacer material layer 1051 on the first oxide layer 103 are removed, and the sacrificial layer 106 above the mask layer 101 is removed, and the remaining spacer material layer 1051 covers the The mask layer 101 and the silicon germanium layer 104 are formed, and the remaining sacrificial layer 106 is located on the side of the spacer material layer 1051 away from the silicon germanium layer 104 to form the structure shown in FIG. formed by etching. Here, since the sidewall material layer under the sacrificial layer 106 is relatively thin and will not adversely affect subsequent processes, it is not shown in the figure.

After that, referring to FIG. 8 , a second oxide layer 107 is formed on the first oxide layer 103 ; the material of the second oxide layer 107 may be the same as that of the first oxide layer 103 , such as silicon oxide.

After the second oxide layer 107 is formed, a platforming process is performed to remove the part of the sacrificial layer 106 higher than the fin structure 102 and the part of the spacer material layer 1051 higher than the fin structure 102, exposing the The mask layer 101 and the remaining sidewall material layer 1051 form sidewall spacers 105 .

Specifically, for step S15 , please refer to FIG. 9 , the first gate metal layer 108 is formed on the side of the spacer 105 away from the silicon germanium layer 104 , and the sacrificial layer 106 may be removed first to form an opening , for example, it can be done by wet etching; then a first gate metal layer 108 is formed in the opening, which can be formed by a sputtering process, and the width of the first gate metal layer 108 is

After that, as shown in FIG. 10 , for step S16 , a ferroelectric layer 109 is formed on the side of the first gate metal layer 108 away from the spacer 105 , which may be a part of thinning the second oxide layer 107 The thickness can be achieved by wet etching, and then an atomic layer deposition process is used to form a ferroelectric material layer on the second oxide layer 107 , and then the ferroelectric material layer is further etched to form the ferroelectric layer 109 . Specifically, the width of the ferroelectric layer is 1 nm-20 nm, the material of the ferroelectric layer 109 may be bismuth ferrite (BiFeO ₃ ) or lithium tantalate (LiTaO ₃ ), and of course, other ferroelectric layers may also be used. Substances, the present invention will not list them all here.

Finally, referring to FIG. 11 , step S17 is performed to form a second gate metal layer 110 on the side of the ferroelectric layer 109 away from the first gate metal layer 108 . width is

So far, the fabrication of the semiconductor structure of the present invention is completed. Please continue to refer to FIG. 11 . The semiconductor structure of the present invention includes:

a substrate 100;

a first oxide layer 103 on the substrate 100;

the fin structure 102 on the substrate 100 penetrating the first oxide layer 103;

The silicon germanium layer 104 on both sides of the fin structure 102 exposed on the substrate 100, specifically, the width of the silicon germanium layer 104 is 5nm-50nm;

the sidewall spacer 105 on the side of the silicon germanium layer 104 away from the fin structure 102;

The first gate metal layer 108 is located on the side of the sidewall spacer 105 away from the silicon germanium layer 104 . Specifically, the width of the first gate metal layer 108 is

a second oxide layer 107 on the first oxide layer 103;

The ferroelectric layer 109 on the side of the first gate metal layer 108 facing away from the sidewall spacer 105 on the substrate 100 (specifically, on the second oxide layer 107 ), specifically, the ferroelectric layer The material of 109 is bismuth ferrite or lithium tantalate, and the width of the ferroelectric layer is 1nm-20nm;

The second gate metal layer 110 located on the side of the ferroelectric layer 109 away from the first gate metal layer 108, specifically, the width of the second gate metal layer 110 is

To sum up, the method for manufacturing a semiconductor structure provided by the present invention includes providing a substrate; forming a fin structure on the substrate; forming two sides of the fin structure exposed on the substrate a silicon germanium layer; a sidewall spacer is formed on the side of the silicon germanium layer away from the fin structure; a first gate metal layer is formed on the side of the sidewall spacer away from the silicon germanium layer; A ferroelectric layer is formed on the side of the gate metal layer facing away from the spacer; and a second gate metal layer is formed on the side of the ferroelectric layer facing away from the first gate metal layer. The semiconductor structure thus obtained can improve the situation of short channel damage (SCE) caused by the high dopant concentration of the short channel in the prior art, and can reduce the contact resistance, so as to obtain more The low power supply voltage (Vdd) significantly improves the performance of the semiconductor structure.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (17)

1. a kind of manufacturing method of semiconductor structure, comprising:

One substrate is provided；

Fin structure is formed over the substrate；

The two sides of the fin structure of exposure form germanium-silicon layer over the substrate；

Side wall is formed away from the side of the fin structure in the germanium-silicon layer；

First grid metal layer is formed away from the side of the germanium-silicon layer in the side wall；

Ferroelectric layer is formed away from the side of the side wall in the first grid metal layer；And

Second grid metal layer is formed away from the side of the first grid metal layer in the ferroelectric layer.

2. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the width of the germanium-silicon layer is 5nm- 50nm。

3. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that have the first oxidation on the substrate Layer, the fin structure run through first oxide layer, and the upper surface of the fin structure is higher than the upper of first oxide layer Surface.

4. the manufacturing method of semiconductor structure as claimed in claim 3, which is characterized in that deviate from the fin in the germanium-silicon layer The side of formula structure forms the step of side wall and includes:

Mask layer is formed in the fin structure；

Spacer material layer is formed, the spacer material layer covers the mask layer, germanium-silicon layer and first oxide layer；

Sacrificial layer is formed, the sacrificial layer covers the spacer material layer；

Removal is located at sacrificial layer and spacer material layer in first oxide layer, and removes the sacrifice being located above mask layer Layer, remaining spacer material layer covers the mask layer and germanium-silicon layer, remaining sacrificial layer are located at the spacer material layer and deviate from The side of the germanium-silicon layer；

The second oxide layer is formed in first oxide layer；

The part that the sacrificial layer is higher than the fin structure higher than the part of the fin structure and spacer material layer is removed, cruelly Expose the mask layer, the remaining spacer material layer forms side wall.

5. the manufacturing method of semiconductor structure as claimed in claim 4, which is characterized in that deviate from the SiGe in the side wall Layer side formed first grid metal layer the step of include:

The sacrificial layer is removed to form opening；

First grid metal layer is formed in said opening.

6. the manufacturing method of semiconductor structure as claimed in claim 1 or 5, which is characterized in that the first grid metal layer Width be

7. the manufacturing method of semiconductor structure as claimed in claim 4, which is characterized in that carried on the back in the first grid metal layer Side from the side wall forms the step of ferroelectric layer and includes:

The segment thickness of second oxide layer is thinned；

Ferroelectric material layer is formed in second oxide layer using atom layer deposition process；

It etches the ferroelectric material layer and forms the ferroelectric layer.

8. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the material of the ferroelectric layer is ferrous acid Bismuth or lithium tantalate.

9. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the width of the ferroelectric layer is 1nm- 20nm。

10. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the second grid metal layer Width is

11. a kind of semiconductor structure, comprising:

One substrate,

Fin structure on the substrate；

The germanium-silicon layer of the fin structure two sides of exposure on the substrate；

Positioned at the germanium-silicon layer away from the side wall of the side of the fin structure；

Positioned at the side wall away from the first grid metal layer of the side of the germanium-silicon layer；

Positioned at the first grid metal layer away from the ferroelectric layer of the side of the side wall；

Positioned at the ferroelectric layer away from the second grid metal layer of the side of the first grid metal layer.

12. semiconductor structure as claimed in claim 11, which is characterized in that the width of the germanium-silicon layer is 5nm-50nm.

13. semiconductor structure as claimed in claim 11, which is characterized in that there is the first oxide layer on the substrate, it is described Fin structure runs through first oxide layer, and the upper surface of the fin structure is higher than the upper surface of first oxide layer.

14. semiconductor structure as claimed in claim 11, which is characterized in that the width of the first grid metal layer is

15. semiconductor structure as claimed in claim 11, which is characterized in that the material of the ferroelectric layer is bismuth ferrite or tantalic acid Lithium.

16. semiconductor structure as claimed in claim 11, which is characterized in that the width of the ferroelectric layer is 1nm-20nm.

17. semiconductor structure as claimed in claim 11, which is characterized in that the width of the second grid metal layer is