CN108958348B - A kind of band gap reference of high PSRR - Google Patents

Abstract

A kind of band gap reference of high PSRR, belongs to electronic circuit technology field.Including power supply automatic biasing module, starting module, band-gap reference nucleus module and biasing module, supply voltage is converted to the first power rail signal as the power rail of biasing module by the 7th NMOS tube by power supply auto bias circuit, starting module and power supply automatic biasing module are that biasing module establishes biasing together, and biasing module provides biasing for band-gap reference nucleus module；The second switch and third switching tube of start-up circuit work when power supply is established and prevent entire circuit from resting on nought state, enter the backed off after random of normal operating conditions in circuit；Resistor network in start-up circuit is used to adjust the negative temperature coefficient voltage of band-gap reference nucleus module, and the positive temperature coefficient voltage superposition that the negative temperature coefficient voltage and band-gap reference nucleus module after adjusting generate generates reference voltage.The present invention has the characteristics that higher power supply rejection ability, structure is simple, precision is high and stability is high.

Description

A Bandgap Reference Source with High Power Supply Rejection Ratio

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to the design of a bandgap reference circuit with high power supply rejection ratio.

Background technique

In the design fields of high-performance analog integrated circuits, digital-analog hybrids, digital and power management systems, reference voltage sources are very important and commonly used modules, and are often used in circuits such as analog and digital converters, power converters, and power amplifiers. Performance directly affects the accuracy and stability of the entire system. Since the output of the bandgap reference circuit is connected to the error amplifier or operational amplifier and becomes part of the differential input of the error amplifier, if the power supply ripple or noise cannot be well suppressed in the bandgap reference circuit, then the ripple Voltage and power supply noise will become part of the input signal to the error amplifier, and then be amplified and seriously affect the output signal of the circuit. In the application of power management chips, the current trend is gradually moving towards low power supply operating voltage and low power consumption. As the operating voltage decreases, the accuracy of the signal-to-noise vs. bandgap reference becomes more prominent. Therefore, at lower and lower supply voltages, bandgap references with high power supply rejection PSR become more and more important.

The traditional bandgap reference source is shown in Figure 1, including error amplifier A1, mirror current source composed of PMOS transistors M1, M2, and M3, resistors R14, R15, and PNP bipolar transistors Q1, Q2, and Q3. Then the expression of the obtained reference voltage V _REF is:

Where V _EBQ3 is the voltage difference between the emitter and the base of the bipolar transistor Q3; K is Boltzmann's constant, q is the quantity of electricity per unit charge, T is temperature, and N is the size ratio of PNP bipolar transistors Q1 and Q2. By adjusting the ratio R ₁₅ /R ₁₄ of the resistors R14 and R15, a reference voltage V _REF that is basically independent of temperature can be obtained.

The traditional bandgap reference circuit itself has good power supply rejection characteristics. In the actual circuit, the frequency characteristics of the power supply rejection ratio (Power Supply Rejection Ratio, PSRR) performance are not the same in the entire input voltage range. Early voltage and trench Track length modulation effects generally lead to changes in power supply rejection ratio PSRR. That is, the output impedance of the transistor varies with steady-state bias conditions (drain-source voltage or collector-emitter voltage). The core idea of improving the power supply rejection ratio PSRR is to increase the effective impedance from the reference output voltage V _REF to the input power supply voltage VDD. If you want to design a high-precision complete bandgap reference circuit, you usually need to add additional circuits to improve the power supply voltage suppression capability of the circuit. This method will lead to increased circuit complexity and additional power consumption; on the other hand, in In conventional bandgap reference generation circuits with op amps, due to asymmetry, the op amp suffers from input "offset" that affects the overall performance of the circuit while also limiting its accuracy.

Contents of the invention

The purpose of the present invention is to propose a bandgap reference source with a high power supply rejection ratio for the above-mentioned traditional bandgap reference circuit that needs to add additional circuits to improve the power supply voltage rejection ratio, resulting in circuit complexity and increased power consumption. , the power supply rejection ratio is improved in the internal circuit of the bandgap reference source, and the bandgap reference source proposed by the present invention may not use an operational amplifier structure, which avoids the problem of limiting the accuracy of the bandgap reference source due to the introduction of input offset of the operational amplifier.

Technical scheme of the present invention is:

A bandgap reference source with high power supply rejection ratio, including a power supply self-bias module, a startup module, a bandgap reference core module and a bias module,

The power supply self-bias module includes a first resistor R1, a second resistor R2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first capacitor C1, a second capacitor C2, and a seventh NMOS transistor MNH1 and the first switching tube,

The power supply voltage VDD passes through the series structure of the first resistor R1 and the second resistor R2 to generate a gate bias signal of the seventh NMOS transistor MNH1, which is connected to the gate of the seventh NMOS transistor MNH1 and grounded to GND after passing through the first capacitor C1;

The drain of the seventh NMOS transistor MNH1 is connected to the power supply voltage VDD, and its source outputs the first power rail signal VDD1 as the power rail of the bias module;

The first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected in a diode connection form and connected in series in sequence, and the gate bias signal of the seventh NMOS transistor MNH1 passes through the first PMOS transistor MP1, the second PMOS transistor MP2 and The series structure of the third PMOS transistor MP3 flows through the first switch transistor and then grounded to GND;

The second capacitor C2 is connected between the control terminal of the first switch tube and the ground GND;

The starting module includes a second switch tube and a third switch tube, and includes a third resistor R3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10 the resistor network,

The second switch tube and the third switch tube form a current mirror with the first switch tube respectively, and the second switch tube and the third switch tube are turned on during the power-on stage to generate the first start signal and the second start signal. After power-on is completed Turn off the second switch tube and the third switch tube;

One end of the third resistor R3 is connected to the second start signal, and the other end is connected to one end of the fifth resistor R5 and used as the input end of the resistor network;

One end of the sixth resistor R6 is connected to the other end of the fifth resistor R5 and the first start signal, and the other end is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8;

One end of the ninth resistor R9 is connected to one end of the tenth resistor R10, the other end of the seventh resistor R7 and the other end of the eighth resistor R8, and the other end is connected to the other end of the tenth resistor R10 and grounded to GND;

The power supply self-bias module and the start-up module establish a bias for the bias module, and the bias module provides a bias for the bandgap reference core module;

The bandgap reference core module is used to generate a positive temperature coefficient voltage and a negative temperature coefficient current, the negative temperature coefficient current is connected to the input end of the resistance network and generates a negative temperature coefficient voltage on the resistance network, the negative temperature coefficient The temperature coefficient voltage is superimposed with the positive temperature coefficient voltage to generate a reference voltage V _REF .

Specifically, the seventh NMOS transistor MNH1 is a pressure-resistant transistor.

Specifically, the bias module includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, an eleventh PMOS transistor MP11, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, the sixth NMOS transistor MN6, the sixth NPN transistor NPN6, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13,

The source of the fourth PMOS transistor MP4 is connected to the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the eleventh PMOS transistor MP11 and connected to the first power rail signal VDD1, and its drain is connected to the seventh NMOS transistor MNH1 The gate bias signal of the signal after passing through the series structure of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3, the gate of which is connected to the gate and drain of the eleventh PMOS transistor MP11 and the third The drain of the NMOS transistor MN3;

The gate of the sixth PMOS transistor MP6 is connected to the drain of the sixth NMOS transistor MN6 and the gate and drain of the fifth PMOS transistor MP5 and connected to the current mirror of the startup module, and its drain is connected to the gate of the sixth NMOS transistor MN6 pole and generate a second power rail signal VDD2 to provide bias for the bandgap reference core module;

The gate of the third NMOS transistor MN3 is connected to the gate and drain of the fourth NMOS transistor MN4 and connected to the first power rail signal VDD1 after passing through the eleventh resistor R11, and its source is grounded to GND after passing through the twelfth resistor R12. ;

The gate-drain of the fifth NMOS transistor MN5 is short-circuited and connected to the source of the fourth NMOS transistor MN4, and its source is grounded to GND;

The base of the sixth NPN transistor NPN6 is connected to the reference voltage V _REF , its collector is connected to the source of the sixth NMOS transistor MN6 , and its emitter is grounded to GND after passing through the thirteenth resistor R13 .

Specifically, the first switch tube is a first NPN transistor NPN1, the base and collector of the first NPN transistor NPN1 are interconnected and connected to the gate bias signal of the seventh NMOS transistor MNH1 through the first PMOS transistor MP1 , The signal after the series structure of the second PMOS transistor MP2 and the third PMOS transistor MP3, the emitter of which is grounded.

Specifically, the bandgap reference core module includes a fourth NPN transistor NPN4, a fifth NPN transistor NPN5, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, a first NMOS transistor MN1, a second NMOS transistor MN2, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10,

The base of the fourth NPN transistor NPN4 is connected to the base of the fifth NPN transistor NPN5, the drain of the first NMOS transistor MN1, and the gate and drain of the tenth PMOS transistor MP10 to output the reference voltage V _REF , which The collector is connected to the gate and drain of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8 and grounded to GND after passing through the third capacitor C3, and its emitter is connected to the fifth NPN transistor NPN5 after passing through the fourth resistor R4 emitter;

The source of the eighth PMOS transistor MP8 is connected to the sources of the seventh PMOS transistor MP7, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 and connected to the second power rail signal VDD2, and its drain is connected to the fifth NPN transistor NPN5 The collector and the gate of the ninth PMOS transistor MP9 are grounded to GND after passing through the fourth capacitor C4;

The gate-drain of the second NMOS transistor MN2 is short-circuited and connected to the gate of the first NMOS transistor MN1 and the drain of the ninth PMOS transistor MP9, and its source is connected to the source of the first NMOS transistor MN1 and grounded to GND.

Specifically, the second switch tube is a second NPN type transistor NPN2, and the third switch tube is a third NPN type transistor NPN3,

The base of the second NPN transistor NPN2 is connected to the control terminal of the first switching tube, its emitter outputs the first start signal, and its collector is connected to the gate of the fifth PMOS transistor MP5 in the bias module. The bias module establishes a bias signal;

The base of the third NPN transistor NPN3 is connected to the control terminal of the first switching tube, its emitter outputs the second startup signal, and its collector is connected to the fourth NPN transistor NPN4 in the bandgap reference core module. The collector and the emitter of the fourth NPN transistor NPN4 are connected to the input terminal of the resistor network after passing through the fourth resistor R4.

Working principle of the present invention is:

In the present invention, the power supply self-bias module converts the power supply voltage VDD into the first power rail signal VDD1 through the seventh NMOS transistor MNH1 as the power rail of the bias module, and the bias module is then used as the bandgap reference core according to the first power rail signal VDD1 The module provides bias; the second switch tube and the third switch tube of the startup module work when the power supply is established to prevent the entire circuit from staying in the zero state, and exit after the circuit enters a normal working state; the power supply self-bias module and the startup module together are The bias module establishes a bias; the startup circuit also adjusts the negative temperature coefficient voltage generated by the bandgap reference core module through a resistor network, and the adjusted negative temperature coefficient voltage is superimposed on the positive temperature coefficient voltage generated by the bandgap reference core module to generate A temperature-independent reference voltage V _REF ; since the second power rail signal VDD2 of the bandgap reference core module is isolated from the first power rail signal VDD1 through the sixth PMOS transistor MP6 in the bias module, and the first power rail signal VDD1 is isolated from the power supply voltage VDD through the seventh NMOS transistor MNH1, so that the generated reference voltage V _REF has a higher power supply rejection ratio.

The beneficial effects of the present invention are: the reference voltage V _REF produced by the present invention is isolated from the power supply voltage VDD and will not be affected by noise from the power supply voltage VDD, and has higher power supply suppression PSR capability; through the bandgap reference core module Increasing the negative feedback loop stabilizes the voltage value of the reference voltage V _REF and further improves the power supply rejection ratio of the bandgap reference source; the circuit structure of the present invention is simple, and avoids the limitation caused by the input offset of the operational amplifier caused by the use of the operational amplifier structure The problem of the accuracy of the bandgap reference source.

Description of drawings

Figure 1 is a schematic diagram of a traditional bandgap reference source with an operational amplifier structure.

FIG. 2 is a circuit structure diagram of an implementation of a high power supply rejection ratio bandgap reference source in an embodiment of the present invention.

FIG. 3 is a diagram of the simulation results of the power supply rejection ratio of a high power supply rejection ratio bandgap reference source proposed by the present invention.

FIG. 4 is a simulation result diagram of temperature characteristics of a bandgap reference source with a high power supply rejection ratio proposed by the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

A bandgap reference source with a high power supply rejection ratio proposed by the present invention includes a power supply self-bias module, a start-up module, a bandgap reference core module and a bias module, wherein the structure of the power supply self-bias module is shown in Figure 2, The power supply self-bias module includes a first resistor R1, a second resistor R2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first capacitor C1, a second capacitor C2, a seventh NMOS transistor MNH1 and The first switching tube, the power supply voltage VDD passes through the series structure of the first resistor R1 and the second resistor R2 to generate a gate bias signal of the seventh NMOS transistor MNH1, which is connected to the gate of the seventh NMOS transistor MNH1 and passed through the first capacitor C1 Ground GND; the drain of the seventh NMOS transistor MNH1 is connected to the power supply voltage VDD, and its source outputs the first power rail signal VDD1 as the power rail of the bias module; the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 is connected in a diode connection form and serially connected in series, the gate bias signal of the seventh NMOS transistor MNH1 passes through the series structure of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3, and then flows through the first switch transistor ground GND; the second capacitor C2 is connected between the control terminal of the first switch tube and the ground GND.

The structure of the start-up circuit is shown in Figure 2, including the second switch tube and the third switch tube as well as the third resistor R3, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, and the ninth resistor The resistance network of R9 and the tenth resistor R10, the second switch tube and the third switch tube form a current mirror with the first switch tube respectively, and the second switch tube and the third switch tube are turned on during the power-on stage to generate the first startup signal and the second start signal, turn off the second switch tube and the third switch tube after the power-on is completed; one end of the third resistor R3 is marked as node C connected to the second start signal, and the other end is marked as node D connected to the fifth One end of the resistor R5 is connected to the negative temperature coefficient current generated by the core module of the bandgap reference as the input terminal of the resistor network, and the negative temperature coefficient voltage in the core module of the bandgap reference is adjusted by adjusting the resistor network; one end of the sixth resistor R6 is marked as junction Point B is connected to the other end of the fifth resistor R5 and the first start signal, and the other end is connected to one end of the seventh resistor R7 and one end of the eighth resistor R8; one end of the ninth resistor R9 is connected to one end of the tenth resistor R10, the seventh The other end of the resistor R7 and the other end of the eighth resistor R8 are connected to the other end of the tenth resistor R10 and grounded to GND.

Wherein the first switch tube, the second switch tube and the third switch tube can be in the form of a triode or a MOS tube. This embodiment takes the form of an NPN triode as an example. As shown in FIG. Transistor NPN1, the base and collector interconnection of the first NPN type triode NPN1 is marked as node A and connected to the gate bias signal of the seventh NMOS transistor MNH1 through the first PMOS transistor MP1, the second PMOS transistor MP2 and the third The emitter of the signal after the series structure of the PMOS transistor MP3 is grounded. The second switching tube is the second NPN transistor NPN2, the third switching tube is the third NPN transistor NPN3, the base of the second NPN transistor NPN2 is connected to the control terminal of the first switching tube, and its emitter outputs the first start signal , its collector is connected to the bias module and helps the bias module to establish a bias signal; the base of the third NPN transistor NPN3 is connected to the control terminal of the first switching tube, its emitter outputs the second start signal, and its collector Connect the collector of the fourth NPN transistor NPN4 in the bandgap reference core module, and the emitter of the fourth NPN transistor NPN4 pass through the fourth resistor R4 and connect to the input end of the resistor network.

The power supply self-bias module and the start-up module can be regarded as a branch circuit. When the power supply VDD is powered on and the circuit is started, when the power supply voltage VDD is powered on and exceeds the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor After the sum of the gate-source voltage and the base-emitter voltage of the first NPN transistor NPN1 is 3V _gs +V _be , this branch can be turned on, and the operating point of the circuit begins to be established until the power supply voltage VDD is powered on. The current of each branch and the voltage of each node can be determined.

Considering the application conditions of the circuit, the power rail of the power supply self-bias module and the start module branch can be selected as VDD=12V, and if the BCD process of 0.35um is used, the standard power supply voltage is 5V, that is, the first power rail The signal VDD1 can be selected as 5V, and the seventh NMOS transistor MNH1 for voltage conversion needs to be a voltage-resistant transistor, preferably a voltage-resistant LDMOS transistor.

The bias module establishes a bias signal under the control of the power supply self-bias module and the start-up module to provide bias for the bandgap reference core module. As shown in Figure 2, an implementation form of the bias module is given, including the fourth PMOS Tube MP4, fifth PMOS tube MP5, sixth PMOS tube MP6, eleventh PMOS tube MP11, third NMOS tube MN3, fourth NMOS tube MN4, fifth NMOS tube MN5, sixth NMOS tube MN6, sixth NPN type The transistor NPN6, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13, the source of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the eleventh PMOS transistor MP11 The pole is connected to the first power rail signal VDD1, and its drain is connected to the signal after the gate bias signal of the seventh NMOS transistor MNH1 passes through the series structure of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3, Its gate is connected to the gate and drain of the eleventh PMOS transistor MP11 and the drain of the third NMOS transistor MN3; the gate of the sixth PMOS transistor MP6 is connected to the drain of the sixth NMOS transistor MN6 and the drain of the fifth PMOS transistor MP5 The gate and the drain are connected to the collector of the second NPN transistor NPN2 in the startup module, and the drain is connected to the gate of the sixth NMOS transistor MN6 to generate the second power rail signal VDD2 to provide bias for the bandgap reference core module; The gate of the third NMOS transistor MN3 is connected to the gate and drain of the fourth NMOS transistor MN4 and connected to the first power rail signal VDD1 after passing through the eleventh resistor R11, and its source is grounded to GND after passing through the twelfth resistor R12; The gate-drain of the fifth NMOS transistor MN5 is short-circuited and connected to the source of the fourth NMOS transistor MN4, and its source is grounded to GND; the base of the sixth NPN transistor NPN6 is connected to the reference voltage V _REF , and its collector is connected to the sixth NMOS transistor MN6 The source, the emitter of which is grounded to GND after passing through the thirteenth resistor R13.

The bandgap reference core module is used to generate positive temperature coefficient voltage and negative temperature coefficient current. The negative temperature coefficient current is connected to the input terminal of the resistor network in the startup module, and the negative temperature coefficient voltage is generated on the resistor network. The generated negative temperature coefficient voltage is the same as the positive temperature coefficient voltage. The temperature coefficient voltage is superimposed to generate the reference voltage V _REF . As shown in Figure 2, an implementation form of the bandgap reference core module is given, including the fourth NPN transistor NPN4, the fifth NPN transistor NPN5, the fourth resistor R4, and the fourth resistor R4. The third capacitor C3, the fourth capacitor C4, the first NMOS transistor MN1, the second NMOS transistor MN2, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10, the fourth NPN transistor The base of NPN4 is connected to the base of the fifth NPN transistor NPN5, the drain of the first NMOS transistor MN1 and the gate and drain of the tenth PMOS transistor MP10 to output the reference voltage V _REF , and its collector is connected to the seventh PMOS transistor The gate and drain of MP7 and the gate of the eighth PMOS transistor MP8 are grounded to GND after passing through the third capacitor C3, and its emitter is connected to the emitter of the fifth NPN transistor NPN5 after passing through the fourth resistor R4; the eighth PMOS transistor The source of MP8 is connected to the source of the seventh PMOS transistor MP7, the ninth PMOS transistor MP9 and the tenth PMOS transistor MP10 and connected to the second power rail signal VDD2, and its drain is connected to the collector of the fifth NPN transistor NPN5 and the ninth The gate of the PMOS transistor MP9 is grounded to GND after passing through the fourth capacitor C4; the gate-drain of the second NMOS transistor MN2 is short-circuited and connected to the gate of the first NMOS transistor MN1 and the drain of the ninth PMOS transistor MP9, and its source is connected to The source of the first NMOS transistor MN1 is grounded to GND.

The working process and working principle of this embodiment are as follows.

The power supply self-bias module provides a constant gate bias voltage for the seventh NMOS transistor MNH1, and reduces a gate-source voltage Vgs of a seventh NMOS transistor MNH1 to generate a first power rail signal VDD1. When the first power rail signal VDD1 is established, the bias module generates two gate-source voltages Vgs voltage through the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 connected by two diodes, thereby generating a primary voltage on the twelfth resistor R12 The bias current provides a bias point for the eleventh PMOS transistor MP11. The current flowing through the fourth PMOS transistor MP4 and the current of the self-bias module of the power supply are superimposed on the base-collector short-circuited first NPN-type transistor NPN1 to generate a base voltage, and the current mirror structure is the second NPN-type transistor NPN2 and The third NPN transistor NPN3 establishes a base bias. The first NPN transistor NPN1, the second NPN transistor NPN2, and the resistance from node B to ground constitute a Wildar current mirror, mirroring the current from the bias module of the power supply to the fifth PMOS transistor MP5 connected to the diode, thereby establishing a bias module The gate voltages of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are biased. The first NPN transistor NPN1 and the third NPN transistor NPN3 and the resistance from the C node to the ground also form a Wildar current mirror, which also provides grid bias for the MOS tube connected to it. In some embodiments, the Wilson current mirror can be changed. is a cascode current mirror. The current mirrored by the sixth PMOS transistor MP6 is divided into four branches of the bandgap reference core module, and the MOS transistors connected through diodes provide bias voltages for the gate of the MOS transistor and the base of the triode in the core module of the bandgap reference.

In the startup module, the second NPN transistor NPN2 and the third NPN transistor NPN3 are startup transistors. As the power supply voltage VDD is powered on, the current flowing through the second NPN transistor NPN2 and the third NPN transistor NPN3 also changes accordingly. Large, the voltages of the first start signal and the second start signal generated by nodes B and C will increase accordingly; after the final start is completed, the second NPN transistor NPN2 and the third NPN transistor NPN3 will be turned off, so the steady state Next, the current flowing through the second NPN transistor NPN2 and the third NPN transistor NPN3 is 0.

The bandgap reference core module works as follows:

The fourth NPN transistor NPN4, the fifth NPN transistor NPN5 and the fourth resistor R4 are used to generate a positive temperature coefficient PTAT current and connect it to the resistor network in the startup module. The voltage drop across the fourth resistor R4 is the base-emitter voltage difference ΔV _BE between the fourth NPN transistor NPN4 and the fifth NPN transistor NPN5. Generally, the fourth NPN transistor NPN4 and the fifth NPN transistor NPN5 are selected. The number of parallel connections is 8:1, so the expression of the current flowing through the fourth resistor R4 is:

Since the current flowing through the second NPN transistor NPN2 and the third NPN transistor NPN3 is 0 in a steady state, the current output by the D node is only the sum of the currents flowing through the fourth NPN transistor NPN4 and the fifth NPN transistor NPN5 . In this embodiment, the mirror ratio of the current mirror composed of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 is set to 1:1, so the currents of the two branches are the same. So the voltage on node D is a negative temperature coefficient voltage

R _D is the resistance from the D node (that is, the input end of the resistor network) to the ground. The bandgap reference voltage is obtained by adding a negative temperature coefficient voltage and a positive temperature coefficient voltage according to a proportional coefficient. Since the base-emitter voltage V _BE of the triode has a negative temperature coefficient characteristic, the bandgap reference voltage V _REF can be obtained by superimposing the voltage at point D on the base-emitter voltage of the fifth NPN transistor NPN5, that is, The base voltages of the four NPN transistors NPN4 and the fifth NPN transistor NPN5 are the bandgap reference voltage, which is the reference voltage V _REF produced by the present invention:

According to the circuit technology, the temperature coefficients of NPN transistor ΔV _be and V _be are

Adjusting the ratio of the resistors according to the proportional coefficient of the formula can obtain the temperature-independent bandgap reference voltage V _REF , that is, the equivalent resistance from node B to ground in the resistor network is used to trim and change the node D to ground in the above formula Resistor R _D , thereby adjusting the negative temperature coefficient voltage in the bandgap reference core block.

The fifth NPN transistor NPN5, the ninth PMOS transistor MP9, the first NMOS transistor MN1 and the second NMOS transistor MN2 in the bandgap reference core module form a negative feedback loop, which is used to stabilize the voltage value of the reference voltage V _REF and prevent the reference voltage from V _REF fluctuates greatly when the power supply fluctuates or the load changes. When the voltage value of the reference voltage V _REF is disturbed and changes, the reference voltage V _REF is quickly pulled back to the original value through the action of the negative feedback loop. The fourth capacitor C4 is used for frequency stability compensation of the negative feedback loop.

The core idea of the bandgap reference source to achieve high power supply rejection PSR is to transfer the small signal disturbance from the power supply voltage VDD to the reference voltage V _REF through the transistor as little as possible. For the traditional bandgap reference circuit composed of op amp clamps , improving the PSR of the reference requires increasing the gain of the operational amplifier and the PSR of the operational amplifier, and this circuit improves the PSR of the reference circuit mainly through the seventh NMOS transistor MNH1 and the sixth PMOS transistor MP6 in the bias module. The power supply voltage VDD is reduced by a drain-source voltage Vgs through the seventh NMOS transistor MNH1 to obtain the first power rail signal VDD1. When there is noise in the power supply voltage VDD and a small signal disturbance occurs, the noise is passed through the drain terminal of the seventh NMOS transistor MNH1 and the first power rail The signal VDD1 is isolated so as not to interfere with the first power rail signal VDD1; the first power rail signal VDD1 generates the second power rail signal VDD2 through the sixth PMOS transistor MP6 to form isolation, further ensuring that the second power rail signal VDD2 does not It will change with the crosstalk of the power supply voltage VDD, so the reference voltage V _REF generated by the present invention is basically not affected by the noise from the power supply voltage VDD, and has high power supply suppression PSR capability.

Fig. 3 is the simulation situation of the power supply rejection capability of the bandgap reference source proposed by the present invention, it can be seen that the power supply rejection ratio PSRR of the bandgap reference source proposed by the present invention can reach 127B at low frequencies, and still has 47dB under the situation of 1MHz, Has very good power supply rejection PSR performance.

Fig. 4 is the simulation situation of the temperature characteristics of the bandgap reference source proposed by the present invention. In the temperature range of -40°C to 125°C, the temperature coefficient of the bandgap reference source is:

Among them, V _MAX and V _MIN represent the maximum and minimum values of the reference voltage V _REF in FIG. 4 , respectively.

In summary, the bandgap reference source proposed by the present invention isolates the power supply voltage VDD from the generated reference voltage V _REF through two layers of isolation, so that the reference voltage V _REF generated by the present invention is basically not affected by the power supply voltage VDD. Noise effect, better power supply suppression PSR ability; adjust the negative temperature coefficient voltage of the bandgap reference core module through the resistor network of the start-up module, and add a negative feedback loop design to the bandgap reference core module to stabilize the reference voltage The voltage value of V _REF further improves the power supply rejection ratio of the bandgap reference source; the effect of improving the power supply rejection ratio can be achieved without adding additional circuits, the circuit structure is simple, and the input offset of the op amp caused by the use of the op amp structure is avoided. The problem of introducing and limiting the accuracy of the bandgap reference source.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (6)

1. a kind of band gap reference of high PSRR, which is characterized in that including power supply automatic biasing module, starting module, band Gap benchmark nucleus module and biasing module,

The power supply automatic biasing module includes first resistor (R1), second resistance (R2), the first PMOS tube (MP1), the 2nd PMOS Manage (MP2), third PMOS tube (MP3), first capacitor (C1), the second capacitor (C2), the 7th NMOS tube (MNH1) and first switch Pipe,

Supply voltage (VDD) is by generating the 7th NMOS tube after first resistor (R1) and the cascaded structure of second resistance (R2) (MNH1) gate bias signal connects the grid of the 7th NMOS tube (MNH1) and is grounded (GND) afterwards by first capacitor (C1)；

The drain electrode of 7th NMOS tube (MNH1) connects supply voltage (VDD), and source electrode exports the first power rail signal (VDD1) and makees For the power rail of the biasing module；

First PMOS tube (MP1), the second PMOS tube (MP2) and third PMOS tube (MP3) are connected into diode type of attachment and successively Series connection, the gate bias signal of the 7th NMOS tube (MNH1) is by the first PMOS tube (MP1), the second PMOS tube (MP2) and third The cascaded structure of PMOS tube (MP3) is grounded (GND) after passing through first switch tube；

Second capacitor (C2) connects between the control terminal and ground (GND) of first switch tube；

The starting module include second switch and third switching tube and including 3rd resistor (R3), the 5th resistance (R5), 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9) and the tenth resistance (R10) resistor network,

Second switch and third switching tube constitute current mirror with first switch tube respectively, and second switch is connected in power up phase With third switching tube to generate the first enabling signal and the second enabling signal, shutdown second switch and third after the completion of powering on Switching tube；

One end of 3rd resistor (R3) connects second enabling signal, and the other end connects one end of the 5th resistance (R5) and work For the input terminal of the resistor network；

One end of 6th resistance (R6) connects the other end of the 5th resistance (R5) and first enabling signal, the other end connect One end of 7th resistance (R7) and one end of the 8th resistance (R8)；

One end of 9th resistance (R9) connects the other end and the 8th resistance of one end of the tenth resistance (R10), the 7th resistance (R7) (R8) the other end, the other end connect the other end of the tenth resistance (R10) and ground connection (GND)；

The power supply automatic biasing module and the starting module are that the biasing module establishes biasing, and the biasing module is described Band-gap reference nucleus module provides biasing；

The band-gap reference nucleus module is for generating positive temperature coefficient voltage and negative temperature parameter current, the negative temperature coefficient Electric current connects the input terminal of the resistor network and generates negative temperature coefficient voltage, the negative temperature system on the resistor network Number voltage and the positive temperature coefficient voltage superposition generate reference voltage (V_REF)。

2. the band gap reference of high PSRR according to claim 1, which is characterized in that the 7th NMOS tube It (MNH1) is pressure pipe.

3. the band gap reference of high PSRR according to claim 1, which is characterized in that the biasing module includes 4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 11st PMOS tube (MP11), third NMOS tube (MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 6th NPN type triode (NPN6), Eleventh resistor (R11), twelfth resistor (R12) and thirteenth resistor (R13),

The source electrode of 4th PMOS tube (MP4) connects the 5th PMOS tube (MP5), the 6th PMOS tube (MP6) and the 11st PMOS tube (MP11) source electrode simultaneously connects the first power rail signal (VDD1), and the grid of drain electrode the 7th NMOS tube (MNH1) of connection is inclined Signal of the confidence number after the cascaded structure of the first PMOS tube (MP1), the second PMOS tube (MP2) and third PMOS tube (MP3), The grid of its grid the 11st PMOS tube (MP11) of connection and drain electrode and the drain electrode of third NMOS tube (MN3)；

The grid of 6th PMOS tube (MP6) connect the drain electrode of the 6th NMOS tube (MN6) and the grid of the 5th PMOS tube (MP5) and The current mirror of the starting module is drained and connects, the grid of drain electrode the 6th NMOS tube (MN6) of connection simultaneously generates second source Rail signal (VDD2) provides biasing for the band-gap reference nucleus module；

The grid of third NMOS tube (MN3) connects the grid of the 4th NMOS tube (MN4) and drains and pass through eleventh resistor (R11) After connect the first power rail signal (VDD1), source electrode is grounded (GND) afterwards by twelfth resistor (R12)；

The grid leak of 5th NMOS tube (MN5) is shorted and connects the source electrode of the 4th NMOS tube (MN4), and source electrode is grounded (GND)；

The base stage of 6th NPN type triode (NPN6) connects the reference voltage (V_REF), collector connects the 6th NMOS tube (MN6) source electrode, emitter are grounded (GND) afterwards by thirteenth resistor (R13).

4. the band gap reference of high PSRR according to claim 1, which is characterized in that the first switch tube is First NPN type triode (NPN1), the base stage sum aggregate electrode interconnection of the first NPN type triode (NPN1) simultaneously connect the 7th NMOS tube (MNH1) gate bias signal is by the first PMOS tube (MP1), the string of the second PMOS tube (MP2) and third PMOS tube (MP3) Signal after being coupled structure, emitter ground connection.

5. the band gap reference of high PSRR according to claim 3, which is characterized in that the band-gap reference core Module includes the 4th NPN type triode (NPN4), the 5th NPN type triode (NPN5), the 4th resistance (R4), third capacitor (C3), the 4th capacitor (C4), the first NMOS tube (MN1), the second NMOS tube (MN2), the 7th PMOS tube (MP7), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9) and the tenth PMOS tube (MP10),

The base stage of 4th NPN type triode (NPN4) connects base stage, the first NMOS tube of the 5th NPN type triode (NPN5) (MN1) grid of drain electrode and the tenth PMOS tube (MP10) and drain electrode simultaneously export the reference voltage (V_REF), collector connects The grid for connecing the 7th PMOS tube (MP7) is followed by with the grid of drain electrode and the 8th PMOS tube (MP8) and by third capacitor (C3) Ground (GND), emitter connect the emitter of the 5th NPN type triode (NPN5) by the 4th resistance (R4) afterwards；

The source electrode of 8th PMOS tube (MP8) connects the 7th PMOS tube (MP7), the 9th PMOS tube (MP9) and the tenth PMOS tube (MP10) source electrode simultaneously connects the second source rail signal (VDD2), drain electrode the 5th NPN type triode (NPN5) of connection Collector and the grid of the 9th PMOS tube (MP9) are simultaneously grounded (GND) afterwards by the 4th capacitor (C4)；

The grid leak of second NMOS tube (MN2) is shorted and connects the grid of the first NMOS tube (MN1) and the leakage of the 9th PMOS tube (MP9) Pole, source electrode connect the source electrode of the first NMOS tube (MN1) and ground connection (GND).

6. the band gap reference of high PSRR according to claim 5, which is characterized in that the second switch is Second NPN type triode (NPN2), the third switching tube are third NPN type triode (NPN3),

The base stage of second NPN type triode (NPN2) connects the control terminal of the first switch tube, emitter output described the One enabling signal, collector connect the grid of the 5th PMOS tube (MP5) in the biasing module as biasing module foundation Offset signal；

The base stage of third NPN type triode (NPN3) connects the control terminal of the first switch tube, emitter output described the Two enabling signals, collector connect the collector of the 4th NPN type triode (NPN4) in the band-gap reference nucleus module, the The emitter of four NPN type triodes (NPN4) connects the input terminal of the resistor network by the 4th resistance (R4) afterwards.