CN113220057B - High-noise-resistance floating band-gap reference source - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a high-noise-resistance floating band-gap reference source. The circuit comprises a starting and biasing part, a floating band gap reference core circuit and a negative feedback operational amplifier clamping part, the suppression performance of the reference on power supply noise is improved by utilizing a pre-power supply rail technology and a feedback technology, a reference voltage value for power supply reference is generated through the relation between triode emitter junction voltage and temperature, and finally the high anti-noise reference voltage value for power supply reference is converted into reference voltage for ground reference through a negative feedback operational amplifier. The circuit has the capability of working in a severe noise environment driven by the high-voltage grid, and can provide a stable reference value for a high-voltage grid driving system.

Description

A High Noise Immunity Floating Bandgap Reference

technical field

The invention belongs to the technical field of electronic circuits, in particular to a floating bandgap reference source with high anti-noise.

Background technique

Bandgap references are widely used in various fields of analog integrated circuits. In the high-voltage gate drive, the design of the bandgap reference source is more elegant due to the huge noise and harsh process conditions brought about by its violent switching action. Compared with the power supply rejection performance of the bandgap reference source in the general system, in the high voltage gate drive system, the influence of ground noise on the reference voltage should also be concerned. As shown in Figure 1, the floating bandgap reference structure can effectively isolate the noise of the power supply and the ground. A good bandgap reference source can bring good performance to the entire gate drive system. Therefore, in the harsh working environment of high-voltage gate drive, it is of great significance to realize a bandgap reference source with high noise immunity.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the above problems, to propose a high noise-resistant floating reference circuit, which has the ability to work under the harsh noise environment of high-voltage gate drive, and can provide a stable reference value for the high-voltage gate drive system.

The technical scheme of the present invention is:

A highly anti-noise floating bandgap reference source, as shown in FIG. 2, includes a first LDPMOS transistor, a second LDPMOS transistor, a third LDPMOS transistor, a first LDNMOS transistor, a second LDNMOS transistor, a first PMOS transistor, and a third LDPMOS transistor. Two PMOS transistors, the third PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the third NMOS transistor Nine NMOS transistors, tenth NMOS transistor, eleventh NMOS transistor, first resistor, second resistor, third resistor, fourth resistor, fifth resistor, sixth resistor, seventh resistor, eighth resistor, ninth resistor , the tenth resistor, the first capacitor, the second capacitor, the third capacitor, the NPN tube, the first PNP tube, the second PNP tube, the first Zener diode and the second Zener diode; wherein,

The source of the first LDPMOS tube is connected to the power supply, and the gate is connected to the drain; the source of the second LDPMOS tube is connected to the power supply, and the gate is connected to the drain of the first LDPMOS tube; the source of the third LDPMOS tube is connected to the power supply, and the gate is connected to the power supply. The electrode is connected to the drain of the first LDPMOS transistor;

The drain of the first LDNMOS transistor is connected to the drain of the first LDPMOS transistor, the gate of the first LDNMOS transistor is connected to the power supply through the first resistor, and the source of the first LDNMOS transistor is connected to the ground through the second resistor; The drain is connected to the drain of the first LDPMOS tube, the gate of the second LDNMOS tube is connected to the drain of the second LDPMOS tube, and the source of the second LDNMOS tube is grounded through the third resistor and the second resistor in turn; the second LDNMOS tube The connection point between the gate and the drain of the second LDPMOS transistor is also grounded through the first capacitor;

The drain of the first NMOS transistor is connected to the power supply through the first resistor, the gate of the first NMOS transistor is connected to the source of the second LDNMOS transistor, and the source of the first NMOS transistor is grounded; the drain of the first NMOS transistor is connected to the first resistor The connection point of the first Zener diode is connected to the cathode of the first Zener diode, and the anode of the first Zener diode is grounded;

The drain of the second NMOS transistor is connected to the drain of the second LDPMOS transistor, the gate of the second NMOS transistor is connected to the source of the second LDNMOS transistor, and the source of the second NMOS transistor is grounded;

The collector of the NPN tube is connected to the power supply, the base of the NPN tube is connected to the cathode of the second Zener diode, and the anode of the second Zener diode is grounded;

The drain of the fourth NMOS transistor is connected to the drain of the third LDPMOS transistor, the gate of the fourth NMOS transistor is connected to the emitter of the NPN transistor; the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor, and the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The gate is connected to the collector of the first PNP tube, and the source of the third NMOS tube is grounded;

The drain of the fifth NMOS tube is connected to the emitter of the NPN tube, the gate of the fifth NMOS tube is connected to the source of the fourth NMOS tube, the source of the fifth NMOS tube is connected to the negative electrode of the second capacitor, and the positive electrode of the second capacitor is connected to the collector of the first PNP tube;

The drain of the sixth NMOS transistor is connected to the source of the fifth NMOS transistor, the gate of the sixth NMOS transistor is connected to the source of the second LDNMOS transistor, and the source of the sixth NMOS transistor is grounded;

The drain of the seventh NMOS tube is connected to the collector of the first PNP tube, the gate of the seventh NMOS tube is connected to the collector of the second PNP tube, and the source of the seventh NMOS tube is grounded;

The emitter of the first PNP tube is connected to the emitter of the NPN tube through the fourth resistor, the base of the first PNP tube is connected to the drain of the third PMOS tube; the emitter of the second PNP tube passes through the fifth resistor and the fourth resistor in turn. The resistor is followed by the emitter of the NPN tube, and the base of the second PNP tube is connected to the drain of the third PMOS tube;

The drain of the eighth NMOS transistor is connected to the collector of the second PNP transistor, the gate and the drain of the eighth NMOS transistor are interconnected, and the source of the eighth NMOS transistor is grounded;

The source of the first PMOS tube is connected to the emitter of the NPN tube through the sixth resistor, the gate of the first PMOS tube is connected to the drain of the third PMOS tube; the source of the second PMOS tube is connected to the NPN tube through the sixth resistor The emitter of the second PMOS tube is connected to the emitter of the NPN tube through the ninth resistor;

The drain of the ninth NMOS transistor is connected to the drain of the first PMOS transistor, the gate and drain of the ninth NMOS transistor are interconnected, the source of the ninth NMOS transistor is grounded; the drain of the tenth NMOS transistor is connected to the second PMOS transistor The drain of the tenth NMOS transistor is connected to the drain of the first PMOS transistor, and the source of the tenth NMOS transistor is grounded;

The source of the third PMOS tube is connected to the emitter of the NPN tube through the seventh resistor, and the gate of the third PMOS tube is connected to the emitter of the NPN tube through the ninth resistor;

The drain of the eleventh NMOS transistor is connected to the drain of the third PMOS transistor, the gate of the eleventh NMOS transistor is connected to the drain of the second PMOS transistor, and the drain and the gate of the eleventh NMOS transistor are connected to the drain of the second PMOS transistor. Three capacitors and eighth resistor;

The connection point between the gate of the second PMOS transistor, the gate of the third PMOS transistor and the ninth resistor is grounded through the fourth resistor.

The beneficial effects of the present invention are as follows: a floating reference source circuit with high anti-noise is provided, which can work stably in a high-voltage grid driving system.

Description of drawings

Figure 1 shows the basic floating bandgap reference structure;

2 is a schematic diagram of a circuit structure of the present invention;

Fig. 3 is the schematic diagram of the high anti-noise principle of the present invention;

4 is a simulation diagram of a reference voltage temperature coefficient of the present invention;

FIG. 5 is a simulation diagram of the noise suppression effect of the reference voltage on the ground/power supply of the present invention.

Detailed ways

Below in conjunction with accompanying drawing, the technical scheme of the present invention is described in detail:

Figure 2 shows the complete circuit structure of the high anti-noise floating bandgap reference source proposed by the present invention. The circuit can be roughly divided into three parts: start and bias part, floating bandgap reference core circuit, negative feedback op amp clamping part, and ground reference generation part.

The working principle of the invention is as follows: using the pre-power rail technology and feedback technology to improve the reference's suppression performance to the power supply noise, and then generating the reference voltage value for the power supply reference through the relationship between the transistor emitter junction voltage and temperature, and finally passing the negative feedback operational amplifier. Converts a high noise immunity reference voltage value referenced to the power supply to a reference voltage referenced to ground.

The marked part on the left in Figure 2 is the start-up circuit, and the working process of the start-up circuit is as follows. When the chip is not powered on, the source terminal of MNH1 is connected to the ground through R2, and the initial potential is 0. When VCC starts to be powered on, the gate terminal of MNH1 is pushed high, the MNH1 tube is turned on, and the branch where the high-voltage LDPMOS tube MPH1 is located is powered on. , at this time MPH1, MPH2 and MNH2 form a positive feedback loop to speed up the power-on of the bias part, and the gates of MN2 and MNH2 are both pushed high, but the MN2 tube does not reach the threshold at this time. When the current continues to increase, MN1 and MN2 are turned on and start to reduce the gate voltage of MNH2, thereby gradually cutting off the startup branch, negative feedback loops MN1 and MNH2 are formed, and the bias circuit current is gradually stabilized. The bias module is V _GS /R type, which generates a fixed bias current, and the gate terminal voltage of MN2 is used as a bias voltage to lead to other parts for bias. Capacitor C1 is a compensation capacitor, which is used to reduce the frequency of the main pole and prevent the bandwidth from being too large and the coupling of high-frequency noise signals. The Zener tube Z1 is used for clamping pressure during the startup process, protecting the gate end of the MNH1 tube and preventing the breakdown of the gate oxide. MPH3 forms a high-voltage current mirror with MPH1, which is used to supply power to the following circuits. It is used for the VGS clamping protection inside the bias circuit and the high voltage resistance of the high-voltage tube VDS, so that the circuit can work safely when the power is fast.

The internal power rail of the floating bandgap reference is powered by the NPN, and the core part of the floating reference and the negative feedback clamp op amp are powered by the NPN amplifying the current. The pre-power rail technology is used here to improve the performance of the reference voltage to suppress power supply noise, where the pre-power rail voltage is:

The working principle of the bandgap reference core circuit is as follows. PNP1, PNP2 and R5 generate positive temperature PTAT currents. The pressure drop across R5 is the difference between the two tubes Veb. Set PNP2:PNP1=8:1, so the current flowing through R5 is

Since MN8 and MN9 form a current mirror, the positive temperature PTAT voltage on R4 can be obtained as

Since V _EB of PNP is a negative temperature-dependent voltage, the floating reference voltage value can be obtained from the emitter of NPN to the base of PNP1 and PNP2:

According to the temperature coefficient of the NPN transistor ΔV _be and V _be according to the circuit process:

The temperature-independent floating bandgap reference voltage V _ref can be obtained by adjusting the resistance value of the resistor according to the proportional coefficient of the formula. Since the floating bandgap reference is obtained with reference to a relatively clean pre-power rail, and the NMOS transistors MN7 and MN8 at the bottom isolate the ground noise, it has good anti-noise capability.

The bandgap voltage reference circuit has a negative feedback loop to stabilize the floating voltage reference value, preventing the reference value from generating large fluctuations when the power supply jitters or the load changes. The main negative feedback loop of the present invention is composed of MN3, MN4, NPN, R4, and PNP1 to ensure the stability of the loop, and the positive feedback loop is composed of MN3, MN4, NPN, R1, PNP2, MN7, and MN8 to accelerate the reference state is established. At the same time, a small loop composed of MN4 and NPN is introduced into the pre-power rail generation part to stabilize the pre-power rail voltage. The use of china tubes Z2 and Z3 protects the tubes from breakdown during start-up. When the voltage value of V _ref is disturbed and changed, V _ref is quickly pulled back to the original value by the action of the negative feedback loop. Capacitor C2 is used to compensate the frequency stability of the negative feedback loop. Since the junction capacitance between the lower plate of C2 and the substrate has leakage at high temperature, the leakage will be introduced into the reference core or feedback circuit, so the introduction of MN5, The MN6 tube, the MN6 source follower formed by MN5, absorbs the leakage of the parasitic capacitance of C2 at high temperature, and at the same time eliminates the zero point of the right half plane brought by C2 as the Miller capacitance.

MP1, MP2, MP3, MN9, MN10, MN11, R6, R7, R8, and C3 constitute a clamp negative feedback op amp, which is used to transfer the voltage value of the floating reference core to the ground reference, which is convenient for subsequent voltage comparison. The principle of high noise immunity of the invention is shown in Figure 3, where the voltage of V _ref is the floating reference voltage value, which is obtained by referring to the pre-power rail. The parasitic inductance will generate high-frequency common-mode noise on the ground. At this time, the floating reference value generated by the reference structure will not be disturbed (the high voltage noise of the floating reference is formed by MN3 at high frequency. The diode-connected MOS1: 1. It is derived from the ground noise, and the low voltage noise is derived from the MOS1:1 transfer of the MOS1:1 in the form of a diode connection at high frequencies, so the difference can be offset to the ground noise), so the reference structure has good ground resistance. Noise ability, can isolate ground noise. When the high-frequency noise disappears, the feedback loop of the reference is established. At this time, the reference voltage to ground can be compared with the floating reference voltage value through the clamped negative feedback op amp to obtain a clean output reference voltage to the ground.

As shown in FIG. 4, it is the stability coefficient of the floating reference voltage value of the present invention

According to the formula:

A temperature coefficient of 22.46ppm/°C is obtained

As shown in Figure 5, after adding the small signal interference source to the ground, the gain of the output reference can be seen, and the ground noise can be effectively isolated in the low frequency band.

Claims (1)

1. A high noise-resistant floating band-gap reference source is characterized by comprising a first LDPMOS (laser diode channel metal oxide semiconductor) tube, a second LDPMOS tube, a third LDPMOS tube, a first LDNMOS (laser diode channel metal oxide semiconductor) tube, a second LDNMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a first capacitor, a second capacitor, a third capacitor, an NPN (negative-positive-negative-positive-negative) transistor, a first PNP tube, a second PNP tube, a first Zener diode and a second Zener diode; wherein,

the source electrode of the first LDPMOS tube is connected with the power supply, and the grid electrode of the first LDPMOS tube is interconnected with the drain electrode of the first LDPMOS tube; the source electrode of the second LDPMOS tube is connected with the power supply, and the grid electrode of the second LDPMOS tube is connected with the drain electrode of the first LDPMOS tube; the source electrode of the third LDPMOS tube is connected with the power supply, and the grid electrode of the third LDPMOS tube is connected with the drain electrode of the first LDPMOS tube;

the drain electrode of the first LDNMOS tube is connected with the drain electrode of the first LDPMOS tube, the grid electrode of the first LDNMOS tube is connected with the power supply after passing through the first resistor, and the source electrode of the first LDNMOS tube is grounded after passing through the second resistor; the drain electrode of the second LDNMOS tube is connected with the drain electrode of the first LDPMOS tube, the grid electrode of the second LDNMOS tube is connected with the drain electrode of the second LDPMOS tube, and the source electrode of the second LDNMOS tube is grounded after passing through the third resistor and the second resistor in sequence; the connection point of the grid electrode of the second LDNMOS tube and the drain electrode of the second LDPMOS tube is grounded through a first capacitor;

the drain electrode of the first NMOS tube is connected with a power supply through a first resistor, the grid electrode of the first NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the first NMOS tube is grounded; the connection point of the drain electrode of the first NMOS tube and the first resistor is connected with the cathode of the first Zener diode, and the anode of the first Zener diode is grounded;

the drain electrode of the second NMOS tube is connected with the drain electrode of the second LDPMOS tube, the grid electrode of the second NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the second NMOS tube is grounded;

the collector of the NPN tube is connected with the power supply, the base of the NPN tube is connected with the cathode of the second Zener diode, and the anode of the second Zener diode is grounded;

the drain electrode of the fourth NMOS tube is connected with the drain electrode of the third LDPMOS tube, and the grid electrode of the fourth NMOS tube is connected with the emitting electrode of the NPN tube; the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the collector electrode of the first PNP tube, and the source electrode of the third NMOS tube is grounded;

the drain electrode of the fifth NMOS tube is connected with the emitting electrode of the NPN tube, the grid electrode of the fifth NMOS tube is connected with the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube is connected with the negative electrode of the second capacitor, and the positive electrode of the second capacitor is connected with the collector electrode of the first PNP tube;

the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube, the grid electrode of the sixth NMOS tube is connected with the source electrode of the second LDNMOS tube, and the source electrode of the sixth NMOS tube is grounded;

the drain electrode of the seventh NMOS tube is connected with the collector electrode of the first PNP tube, the grid electrode of the seventh NMOS tube is connected with the collector electrode of the second PNP tube, and the source electrode of the seventh NMOS tube is grounded;

the emitter of the first PNP tube is connected with the emitter of the NPN tube through a fourth resistor, and the base of the first PNP tube is connected with the drain of the third PMOS tube; an emitter of the second PNP tube is connected with an emitter of the NPN tube after passing through the fifth resistor and the fourth resistor in sequence, and a base of the second PNP tube is connected with a drain of the third PMOS tube;

the drain electrode of the eighth NMOS tube is connected with the collector electrode of the second PNP tube, the grid electrode and the drain electrode of the eighth NMOS tube are interconnected, and the source electrode of the eighth NMOS tube is grounded;

the source electrode of the first PMOS tube is connected with the emitting electrode of the NPN tube through a sixth resistor, and the grid electrode of the first PMOS tube is connected with the drain electrode of the third PMOS tube; the source electrode of the second PMOS tube is connected with the emitting electrode of the NPN tube through a sixth resistor, and the grid electrode of the second PMOS tube is connected with the emitting electrode of the NPN tube through a ninth resistor;

the drain electrode of the ninth NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode and the drain electrode of the ninth NMOS tube are interconnected, and the source electrode of the ninth NMOS tube is grounded; the drain electrode of the tenth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the tenth NMOS tube is connected with the drain electrode of the first PMOS tube, and the source electrode of the tenth NMOS tube is grounded;

the source electrode of the third PMOS tube is connected with the emitting electrode of the NPN tube through a seventh resistor, and the grid electrode of the third PMOS tube is connected with the emitting electrode of the NPN tube through a ninth resistor;

the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the eleventh NMOS tube is connected with the drain electrode of the second PMOS tube, and a third capacitor and an eighth resistor are connected between the drain electrode and the grid electrode of the eleventh NMOS tube;

and the connection points of the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the ninth resistor are grounded through a fourth resistor.

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