CN109450417B - A start suppression circuit that overshoots for LDO - Google Patents
A start suppression circuit that overshoots for LDO Download PDFInfo
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Abstract
The invention discloses a starting overshoot suppression circuit for an LDO (low dropout regulator), which comprises a first overshoot suppression circuit, a second overshoot suppression circuit and a control circuit, wherein the first overshoot suppression circuit is connected between a power supply end and an output end of an error amplifier of the LDO; the first overshoot suppression circuit comprises a first switch control unit and a voltage clamping unit which are connected in series, wherein an enabling signal of the first switch control unit is obtained by inverting an enabling signal of the LDO and delaying for a first preset time, so that a grid voltage of a power tube of the LDO is clamped to a first preset value through the voltage clamping unit within the first preset time when the LDO is started, and the grid-source voltage of the power tube is maintained at a second preset value, so that the current output to a load by the LDO is limited. The invention realizes the suppression of the overshoot voltage during the starting of the LDO by using simpler circuit design, smaller circuit area and ultra-low circuit power consumption, thereby realizing smaller starting overshoot.
Description
Technical Field
The invention relates to the technical field of power management, in particular to a circuit for suppressing a starting overshoot voltage for an LDO (low dropout regulator).
Background
With the increasing growth of consumer electronic products, portable electronic products such as smart phones, tablet computers, and notebook computers have become an indispensable part of people's daily life, and the strong growth of the above products also makes hybrid integrated circuits and SOCs (System on chips) develop rapidly, often requiring multiple low dropout linear regulators (LDO) in one chip to supply power, so as to meet the low power consumption requirement of digital circuits.
The service life of a circuit working under the LDO voltage is influenced by the applied voltage, the service life of a digital circuit is seriously influenced by the excessive overshoot voltage in the starting process of the LDO, and even the breakdown of a device can be caused, so that the suppression of the overshoot voltage in the starting process of the LDO is particularly important. The conventional way to suppress the overshoot of LDO start-up is to control the peak current during start-up through an additional proprietary circuit, so as to suppress the overshoot of output voltage. For example, in the patent document CN 105408829A, "slow start for LDO regulator", a high bandwidth path is provided in parallel with a high gain path, which includes a comparator, a delay unit, and a switching device, and the high bandwidth path is specifically used for suppressing the start overshoot, and the principle is to achieve the purpose of controlling the start overshoot by monitoring the output voltage and feedback-controlling the current flowing to the load. However, the additional proprietary circuit undoubtedly increases the circuit area and the circuit power consumption, and cannot meet the design requirements of low power consumption and small area of most of the electronic products today.
The above background disclosure is only for the purpose of assisting understanding of the inventive concept and technical solutions of the present invention, and does not necessarily belong to the prior art of the present patent application, and should not be used for evaluating the novelty and inventive step of the present application in the case that there is no clear evidence that the above content is disclosed before the filing date of the present patent application.
Disclosure of Invention
The invention mainly aims to overcome the defects of the prior art and provides a start overshoot suppression circuit for an LDO (low dropout regulator), which realizes suppression of an overshoot voltage during starting of the LDO by using a simpler circuit design, a smaller circuit area and ultra-low circuit power consumption, thereby realizing smaller start overshoot.
The invention provides the following technical scheme for achieving the purpose:
a start overshoot suppression circuit for an LDO (low dropout regulator) comprises a first overshoot suppression circuit, a first output end and a second output end, wherein the first overshoot suppression circuit is connected between a power supply end and an output end of an error amplifier of the LDO; the first overshoot suppression circuit comprises a first switch control unit and a voltage clamping unit which are connected in series, wherein an enabling signal of the first switch control unit is obtained by inverting an enabling signal of the LDO and delaying for a first preset time, so that a grid voltage of a power tube of the LDO is clamped to a first preset value through the voltage clamping unit within the first preset time when the LDO is started, and the grid-source voltage of the power tube is maintained at a second preset value, so that the current output to a load by the LDO is limited.
The start overshoot suppression circuit for the LDO can control the current flowing to the load from the power supply by using the delay signal generated by the clock of the LDO in the starting process of the LDO, and can realize the suppression of the start overshoot by using a smaller circuit area without a special peripheral circuit.
Furthermore, the start overshoot suppression circuit further comprises a second overshoot suppression circuit connected to the output end of the LDO, and the second overshoot suppression circuit comprises a load current detection unit, a current-voltage conversion unit and a voltage comparison unit; the load current detection unit is connected to a power tube of the LDO and used for monitoring the current flowing from the LDO to a load in real time; the current-voltage conversion unit is connected in series with the load current detection unit and is used for converting the current collected by the load current detection unit into voltage; the input end of the voltage comparison unit is connected to the current-voltage conversion unit, and the output end of the voltage comparison unit is connected to the output end of an error amplifier in the LDO, and the voltage comparison unit is used for pulling up the output end of the error amplifier according to the output voltage of the current-voltage conversion unit so as to limit the current output by the power tube to a load. The starting overshoot suppression circuit can better suppress the starting overshoot.
In a word, the start overshoot suppression circuit provided by the invention can directly control the gate voltage of the power tube of the LDO by using the delay signal generated by the clock of the LDO in the starting process of the LDO, so as to control the current flowing to the load, and meanwhile, the overcurrent protection circuit in the linear voltage regulator can be reasonably utilized, so that the sharp current flowing to the load in the starting process is avoided.
Drawings
FIG. 1 is a circuit schematic of a conventional low dropout linear regulator;
FIG. 2 is a schematic diagram of a start-up overshoot suppression circuit for a conventional LDO according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a start-up overshoot suppression circuit for a conventional LDO according to a preferred embodiment of the present invention;
FIG. 4 is a timing diagram of the operation of the circuit shown in FIG. 3;
fig. 5 is a schematic circuit diagram of a start overshoot suppression circuit according to another preferred embodiment of the present invention, which is used in a conventional LDO.
Detailed Description
The invention is further described with reference to the following figures and detailed description of embodiments.
A conventional low dropout regulator (hereinafter referred to as "LDO") mainly includes an error amplifier EA and a power transistor M1 serving as an output of a final stage in an amplifier circuit, as shown in fig. 1. The source of the power transistor M1 is connected to two series power resistors Rf1 and Rf2, and the source is grounded through a capacitor, which is not described herein again since the conventional LDO and circuit connection thereof belong to the prior art.
The invention provides a starting overshoot suppression circuit with small circuit area and low power consumption in order to overcome the defects of the existing LDO starting overshoot suppression scheme, as shown in fig. 2, the starting overshoot suppression circuit for the LDO according to the embodiment of the invention includes a first overshoot suppression circuit 100, the first overshoot suppression circuit 100 is connected between the power supply terminal (VDD) and the output terminal EA _ out of the error amplifier EA of the LDO, and includes a first switch control unit and a voltage clamping unit connected in series, and the enable signal of the first switch control unit is obtained by inverting the enable signal of the LDO and delaying for a first predetermined time, so that the gate voltage of the power tube M1 of the LDO is clamped to a first predetermined value by the voltage clamping unit within the first predetermined time when the LDO is started, and the gate-source Voltage (VGS) of the power tube M1 is maintained at a second predetermined value, so that the current output by the LDO to the load is limited.
The first preset time t0 is greater than 0, t0 is set according to the LDO starting setup time required by the LDO application system, and the larger t0 is, the better the suppression effect of the invention on the LDO starting overshoot is. The LDO generally supplies power to a digital circuit inside an SOC (system on chip), so that an application system of the LDO generally refers to an application environment of the LDO, for example, the system on chip, and the setup time of the LDO needs to be defined from the overall timing, and the larger t0 is within the allowable range of the system, the better the overshoot suppression effect is.
During the time of LDO starting t 0: the first switch control unit is in a switch-on state, so that the voltage clamping unit is connected into the LDO to suppress the start overshoot, and in the time period, the gate voltage of the power tube M1 is clamped to a first preset value VDD-VD1 by the voltage clamping unit, so that VGS of the power tube M1 is maintained at a second preset value VD1, and the current output to a load by the power tube M1 can be limited. And VDD is the power supply voltage of the error amplifier EA, and VD1 is the conduction voltage drop of the voltage clamping unit. After the LDO is started for time t0, the first switch control unit is turned off, and the power tube M1 starts to supply normal current to the load.
In a specific embodiment, the first switch control unit includes a first switch SW1, and the voltage clamping unit includes a one-way conducting device, and a conducting direction of the one-way conducting device is directed to the output terminal (EA _ out) from the power supply terminal of the error amplifier EA. In a more preferred embodiment, the first switch control unit is a switch SW1, the voltage clamping unit is a diode D1, an anode of the diode D1 is connected to the power supply terminal of the error amplifier EA, and a cathode of the diode D1 is connected to the output terminal EA _ out of the error amplifier EA. In other embodiments, the diode D1 may be replaced by a PMOS transistor or an NMOS transistor.
The LDO and the switching tube SW1 are both defined to be turned on when the signal is '1' and turned off when the signal is '0'. Referring to fig. 4, which shows the operation timing of the start overshoot suppression circuit of the present invention, the enable signal S1 of the switch SW1 is obtained by inverting the enable signal of the LDO and delaying for time t0. When the enable signal EN of the LDO changes from '0' to '1' (i.e., the LDO is turned on), the current Iin output from the VDD terminal increases momentarily, and after a delay time t0, the enable signal S1 of the switching tube SW1 changes from '1' to '0'. And in the t0 time of the LDO starting: the grid voltage of the power tube M1 is clamped to VDD-VD1 by the voltage clamping unit, so that VGS (grid source voltage) of the power tube M1 is maintained at the conduction voltage drop VD1 of the diode D1, and thus, the current output to the load by the power tube M1 can be limited, and the load is prevented from being impacted by instantaneous large current to generate overshoot voltage. After the LDO is turned on for time t0, the enable signal S1 of the switch SW1 changes from '1' to '0', the switch SW1 is turned off, the first overshoot suppression circuit 100 is turned off, and the power tube M1 starts to provide a stable working current to the load. As can be seen from fig. 4, the voltage Vout of the load increases steadily from the start of the LDO within the time t0, and after the time t0, the first overshoot suppression circuit 100 is turned off, and Vout is a constant value, and the start overshoot voltage does not occur. The start-up overshoot suppression effect of the embodiment of the invention is good.
As shown in fig. 3 and 5, the embodiment of the invention further provides a more preferable start overshoot suppression circuit, and compared with the foregoing technical solution illustrated in fig. 2, the start overshoot suppression circuit illustrated in fig. 3 and 5 adds a second overshoot suppression circuit 200 connected to the LDO output terminal.
As shown in fig. 3 and 5, the second overshoot suppression circuit 200 includes a load current detection unit 201/201', a current-voltage conversion unit 202, and a voltage comparison unit 203; the load current detection unit 201/201' is connected to a power tube M1 of the LDO, and is configured to monitor a current flowing from the LDO to a load in real time; the current-voltage conversion unit 202 is connected in series to the load current detection unit 201/201 'and is used for converting the current collected by the load current detection unit 201/201' into voltage; the input end of the voltage comparing unit 203 is connected to the current-voltage converting unit 202, and the output end thereof is connected to the output end EA _ out of the error amplifier EA in the LDO, for pulling up the output end of the error amplifier according to the output voltage of the current-voltage converting unit 202, so as to limit the current magnitude output from the power tube M1 to the load.
In a specific embodiment, as shown in fig. 3 and 5, the current-voltage conversion unit 202 includes a first resistor R1 connected between the load current detection unit 201/201' and the voltage comparison unit 203. The first resistor R1 can convert the current detected by the load current detection unit 201 into a voltage for the subsequent voltage comparison unit 203.
In one implementation, as shown in fig. 3, the load current detection unit 201 includes a second power transistor M2, a gate of the second power transistor M2 is connected to the output end EA _ out of the error amplifier EA, a source of the second power transistor M2 is connected to the current-voltage conversion unit 202, and a drain of the second power transistor M2 is connected to the drain of the power transistor M1. The second power transistor M2 serves as a mirror image tube of the power tube M1, and once the power tube M1 flows a large current in the LDO starting process, the second power transistor M2 also flows a large current in a corresponding proportion, so that the monitoring of the load current is realized, and particularly, the peak current in the LDO starting process is to be monitored.
As shown in fig. 5, in another specific embodiment, the load current detection unit 201 'includes not only the second power transistor M2 but also a sixth power transistor M6 connected in parallel with M2, and the gate of M6 is connected to the gate of the second power transistor M2 through a switch SW', the drains of the second power transistor M2 and the sixth power transistor M6 are connected to the drain of the power transistor M1 in common, and the sources of the second power transistor M2 and the sixth power transistor M6 are connected to the current-voltage conversion unit 202 in common; and, the switch tube SW 'is in an on state within a first predetermined time when the LDO is turned on, so that the second power transistor M2 and the sixth power transistor M6 are connected in parallel to form the load current detection unit 201'.
As shown in fig. 3 and 5, the voltage comparison unit 203 includes third to fifth power transistors M3 to M5, a first current source I1, and a second current source I2; the grid and the drain of the third power transistor M3 and the grid of the fourth power transistor M4 are connected to the first current source I1, and the other end of the first current source I1 is grounded; the drain electrode of the fourth power transistor M4 and the gate electrode of the fifth power transistor M5 are connected to the second current source I2, and the other end of the second current source I2 is grounded; a source of the third power transistor M3 is connected to a first end of the current-voltage conversion unit 202, and a source of the fourth power transistor M4 and a drain of the fifth power transistor M5 are commonly connected to a second end of the current-voltage conversion unit 202, wherein the first end of the current-voltage conversion unit 202 is the end connected to the load current detection unit 201; the source of the fifth power transistor M5 is connected to the output terminal ea _ out of the error amplifier. Within a first preset time when the LDO is started, when the load current detection unit 201/201' detects a current greater than a preset threshold, the voltage difference of the voltage drop of the source of the third power transistor M3 is amplified by the third power transistor M3 and the fourth power transistor M4 through a single-stage common source, the amplified signal reaches the gate of the fifth power transistor M5, the fifth power transistor M5 is triggered to be turned on, and the output end of the error amplifier is pulled up through the source of the fifth power transistor M5 to limit the current output from the power transistor M1 to the load. In a more preferred scheme, the second to fourth power transistors are PMOS transistors, and the fifth power transistor is an NMOS transistor.
In a more preferred embodiment, as shown in fig. 3, the start overshoot suppression circuit further includes an over-current protection branch connected in parallel with the current-voltage conversion unit 202, and the over-current protection branch is turned on after the LDO is started for a first predetermined time, and is connected in parallel with the current-voltage conversion unit 202 to implement over-current protection of the LDO. Furthermore, the over-current protection branch comprises a second resistor R2 and a second switch control unit SW2 which are connected in series, and the second switch control unit SW2 is turned on after the LDO is started for the first predetermined time to control the over-current protection branch to be turned on, so that the resistors R1 and R2 are connected in parallel to realize the over-current protection function of the LDO. The second switch control unit SW2 is preferably a switch tube.
In another more preferred embodiment, as shown in fig. 5, the start overshoot suppression circuit further includes a third switch control unit SW3, where SW3 is connected between the second end of the current-voltage conversion unit 202 and the gate of the sixth power transistor M6, and is turned on after the LDO is started for a first predetermined time to pull up the gate of the sixth power transistor M6, turn off the sixth power transistor M6, and further connect the second power transistor M2 in parallel with the current-voltage conversion unit 202 to implement the over-current protection of the LDO. The third switch control unit SW3 is preferably a switch tube.
The principle of start-up overshoot suppression is described below for the embodiments shown in fig. 3 and 5, respectively. The LDO is defined to be turned on when the enable signal EN is "1" and turned off when the enable signal EN is "0", and similarly, the SW2, SW3, and SW' are also defined to be turned on when the signal EN is "1" and turned off when the signal EN is "0".
Referring to fig. 3 and 4, when the enable signal EN of the LDO changes from '0' to '1' (i.e., the LDO is turned on), the current Iin output via the VDD terminal (the operating power supply terminal of the error amplifier) instantaneously becomes large, during the t0 period of the LDO being turned on (i.e., during the t0 period after the enable signal EN of the LDO changes from 0 to 1): the enable signal S2 of the SW2 connected in series with the resistor R2 is still 0, sw2 is turned off, when the current I detected by the second power transistor M2 increases, the voltage drop across the resistor R1 also increases, the source voltage of the third power transistor M3 (source voltage = VDD-I × R1) decreases, the decreased voltage difference Δ V is subjected to single-stage common source amplification by the third power transistor M3 and the fourth power transistor M4, the amplified signal reaches the gate of the fifth power transistor M5, the fifth power transistor M5 is triggered to be turned on, the output end ea _ out of the error amplifier is pulled up by the source of M5, and the current output to the load by the power transistor M1 is further limited. The preset threshold of the current during starting may be set according to a specific application environment, and once the current detected by M2 is greater than the preset threshold, the amplified signal of the voltage difference of the voltage drop at the source end of the power transistor M3 may trigger the power transistor M5 to be turned on. And after the LDO is started for time t0 (i.e. the enable signal EN of the LDO changes from 0 to 1 and the time t0 elapses): and an enable signal S2 of the SW2 is changed into 1, the SW2 is switched on, a branch where the second resistor R2 is located is switched on, and the branch is connected with the first resistor R1 in parallel to realize the overcurrent protection function of the LDO. As can be seen from fig. 4, during the setup time t0 after the start-up of the LDO, the voltage Vout of the load increases steadily from the start-up of the LDO, and after the time t0, vout is a constant value and no start-up overshoot voltage occurs. The start-up overshoot suppression effect of the embodiment of the invention is good.
As shown in fig. 5, for this embodiment, the enable signal of the switch SW 'is obtained by inverting the enable signal of the LDO and delaying for time t0, and the enable signal of SW3 is the inverted signal of the enable signal of SW'. After the enable signal of the LDO changes from 0 to 1 (i.e., the LDO is turned on) and the time t0 elapses, the enable signal of SW' changes from 1 to 0, so that during the time t0 when the LDO is turned on: the signal of the switching tube SW' is 1 and is in an on state, the third switch control unit SW3 is turned off, at this time, the power transistors M2 and M6 are used as a load current detection device to monitor the load current, when the current flowing to the load is monitored to be increased, the source voltage of the third power transistor M3 is decreased, especially when the current detected by the power transistors M2 and M6 exceeds a preset threshold, the voltage difference of the decreased source of the power transistor M3 is amplified by the third power transistor M3 and the fourth power transistor M4 and then reaches the gate of the fifth power transistor M5, the fifth power transistor M5 is triggered to be turned on, the output end ea _ out of the error amplifier is pulled up by the source of the power transistor M5, and the current output by the power transistor M1 to the load is further limited. After the time t0 of the LDO starting, the signal of SW 'is changed from 1 to 0, SW' is switched off, SW3 is switched on, the grid electrode of the sixth power switch tube M6 is pulled high, the sixth power switch tube M6 is switched off, and thus the second power transistor M2 is connected with the first resistor R1 in parallel to realize the overcurrent protection function of the LDO.
In summary, the first overshoot suppression circuit 100 of the start overshoot suppression circuit for LDO of the present invention has been verified in the AW1760 product, so as to better suppress the start overshoot. The efficacy of the LDO start overshoot suppression circuit with both the first and second overshoot suppression circuits 100 and 200 in the preferred embodiment (fig. 3 and 5) has been verified by PVT simulation in the AW1788 product, and the start overshoot can be well limited within a certain range. The purpose of suppressing the starting overshoot of the LDO with small area and low power consumption is achieved.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several equivalent substitutions or obvious modifications can be made without departing from the spirit of the invention, and all the properties or uses are considered to be within the scope of the invention.
Claims (12)
1. A start-up overshoot suppression circuit for an LDO, comprising: the first overshoot suppression circuit (100) is connected between a power supply end and an output end (EA _ out) of an Error Amplifier (EA) of the LDO, and the second overshoot suppression circuit (200) is connected to the output end of the LDO;
the first overshoot suppression circuit (100) comprises a first switch control unit and a voltage clamping unit which are connected in series, and an enable signal of the first switch control unit is obtained by inverting an enable signal of the LDO and delaying for a first preset time, so that a gate voltage of a power tube (M1) of the LDO is clamped to a first preset value through the voltage clamping unit within the first preset time when the LDO is started, and a gate-source voltage of the power tube (M1) is maintained at a second preset value, so that the current output to a load by the LDO is limited;
the second overshoot suppression circuit (200) comprises: a second power transistor (M2), a first resistor (R1), a second resistor (R2), a second switch control unit (SW 2) and a voltage comparison unit (203);
the grid electrode of a power tube (M1) of the LDO is connected with the grid electrode of a second power transistor (M2), the grid electrode of the second power transistor (M2) is connected with the output end (EA _ out) of the Error Amplifier (EA), the source electrode of the second power transistor is connected with a power supply voltage VDD through a first resistor (R1), and the drain electrode of the second power transistor is connected with the drain electrode of the power tube (M1);
the input end of the voltage comparison unit (203) is connected with the common end of the first resistor (R1) and the second power transistor (M2), and the output end of the voltage comparison unit is connected with the output end (EA _ out) of the Error Amplifier (EA) in the LDO;
the second resistor (R2) and the second switch control unit (SW 2) are connected in series between a power supply voltage VDD and an input end of the voltage comparison unit (203);
the second power transistor is used as a mirror image tube of a power tube (M1) of the LDO and used for monitoring the current flowing from the LDO to a load in real time; the first resistor (R1) is used for converting the current collected by the second power transistor (M2) into voltage; the voltage comparison unit (203) is used for pulling up the output end of the error amplifier according to the output voltage of the first resistor (R1) so as to limit the current magnitude output to a load by a power tube (M1) of the LDO;
the second switch control unit (SW 2) is switched on after the LDO is started for the first preset time, so that the first resistor (R1) and the second resistor (R2) are connected in parallel to realize the overcurrent protection function of the LDO.
2. A start overshoot suppression circuit as in claim 1, wherein: the first predetermined time is t0, t0 > 0 and t0 is set according to the LDO start-up time required by the LDO application system.
3. A start overshoot suppression circuit as claimed in claim 1, wherein: the first preset value is VDD-VD1, VDD is the power supply voltage of the error amplifier, and VD1 is the conduction voltage drop of the voltage clamping unit; the second predetermined value is VD1.
4. A start overshoot suppression circuit as claimed in claim 1, wherein: the first switch control unit comprises a first switch tube (SW 1).
5. A start overshoot suppression circuit as in claim 1 or 4, wherein: the voltage clamping unit comprises a one-way conduction device, and the conduction direction of the one-way conduction device is directed to the output end (EA _ out) from the power supply end of the Error Amplifier (EA).
6. A start overshoot suppression circuit as claimed in claim 1, wherein:
the voltage comparison unit (203) comprises a third power transistor, a fourth power transistor, a fifth power transistor, a first current source (I1) and a second current source (I2);
the grid and the drain of the third power transistor (M3) and the grid of the fourth power transistor (M4) are connected to a first current source (I1) together, and the other end of the first current source (I1) is grounded; the drain electrode of the fourth power transistor (M4) and the grid electrode of the fifth power transistor (M5) are connected to a second current source (I2) together, and the other end of the second current source (I2) is grounded;
the source electrode of the third power transistor (M3) is connected to the common end of the first resistor and the second power transistor, and the source electrode of the fourth power transistor (M4) and the drain electrode of the fifth power transistor (M5) are connected to the power supply voltage in common; the source of the fifth power transistor (M5) is connected to the output end (ea _ out) of the error amplifier;
when the second power transistor detects a current larger than a preset threshold value within a first preset time when the LDO is started, the voltage difference of the voltage drop of the source electrode of the third power transistor (M3) is subjected to single-stage common source amplification through the third power transistor (M3) and the fourth power transistor (M4), an amplified signal reaches the grid electrode of the fifth power transistor (M5), the fifth power transistor (M5) is triggered to be conducted, and the output end of the error amplifier is pulled up through the source electrode of the fifth power transistor (M5) so as to limit the current output to a load by the power transistor (M1).
7. A start-up overshoot suppression circuit for an LDO, comprising: the first overshoot suppression circuit (100) is connected between a power supply end and an output end (EA _ out) of an Error Amplifier (EA) of the LDO, and the second overshoot suppression circuit (200) is connected to the output end of the LDO;
the first overshoot suppression circuit (100) comprises a first switch control unit and a voltage clamping unit which are connected in series, wherein an enabling signal of the first switch control unit is obtained by inverting an enabling signal of the LDO and delaying for a first preset time, so that a gate voltage of a power tube (M1) of the LDO is clamped to a first preset value through the voltage clamping unit within the first preset time when the LDO is started, and a gate-source voltage of the power tube (M1) is maintained at a second preset value, so that the current output to a load by the LDO is limited;
the second overshoot suppression circuit (200) comprises: the power supply comprises a second power transistor (M2), a sixth power transistor (M6), a switching tube (SW'), a third switch control unit (SW 3), a first resistor (R1) and a voltage comparison unit (203);
the grid electrode of a power tube (M1) of the LDO is connected with the grid electrode of the second power transistor (M2), the grid electrode of the power tube (M1) of the LDO is further connected with the grid electrode of a sixth power transistor (M6) through the switch tube (SW'), the grid electrode of the sixth power transistor (M6) is further connected with a power supply voltage VDD through a third switch control unit (SW 3), the grid electrode of the second power transistor (M2) is connected with the output end (EA _ out) of the Error Amplifier (EA), the source electrode of the second power transistor is connected with the power supply voltage VDD through the first resistor (R1), and the drain electrode of the second power transistor is connected with the drain electrodes of the power tube (M1) and the sixth power transistor (M6);
the input end of the voltage comparison unit (203) is connected with the common end of the first resistor (R1) and the second power transistor (M2), and the output end of the voltage comparison unit is connected with the output end (EA _ out) of the Error Amplifier (EA) in the LDO;
the second power transistor (M2) and the sixth power transistor are used as mirror image tubes of a power tube (M1) of the LDO and are used for monitoring the current flowing from the LDO to a load in real time; the first resistor (R1) is used for converting the current collected by the second power transistor (M2) and the sixth power transistor into voltage; the voltage comparison unit (203) is used for pulling up the output end of the error amplifier according to the output voltage of the first resistor (R1) so as to limit the current magnitude output to a load by a power tube (M1) of the LDO;
the switch tube (SW') is in an on state within a first preset time when the LDO is started, so that the second power transistor (M2) and the sixth power transistor (M6) are connected in parallel;
after the first preset time of starting the LDO, the third switch control unit (SW 3) is switched on to pull the grid of the sixth power transistor (M6) high, so that the sixth power transistor (M6) is switched off, and the overcurrent protection of the LDO is realized.
8. A start overshoot suppression circuit as claimed in claim 7, wherein: the first predetermined time is t0, t0 > 0 and t0 is set according to the LDO startup setup time required by the LDO application system.
9. A start overshoot suppression circuit as in claim 7, wherein: the first preset value is VDD-VD1, VDD is the power supply voltage of the error amplifier, and VD1 is the conduction voltage drop of the voltage clamping unit; the second predetermined value is VD1.
10. A start overshoot suppression circuit as claimed in claim 7, wherein: the first switch control unit comprises a first switch tube (SW 1).
11. A start overshoot suppression circuit as claimed in claim 7 or 10, wherein: the voltage clamping unit comprises a one-way conduction device, and the conduction direction of the one-way conduction device is from the power supply end of the Error Amplifier (EA) to the output end (EA _ out).
12. A start overshoot suppression circuit as claimed in claim 7, wherein: the voltage comparison unit (203) comprises a third power transistor, a fourth power transistor, a fifth power transistor, a first current source (I1) and a second current source (I2);
the grid and the drain of the third power transistor (M3) and the grid of the fourth power transistor (M4) are connected to a first current source (I1) together, and the other end of the first current source (I1) is grounded; the drain electrode of the fourth power transistor (M4) and the grid electrode of the fifth power transistor (M5) are connected to a second current source (I2) together, and the other end of the second current source (I2) is grounded;
the drain electrode of the third power transistor (M3) is connected to the first end of the current-voltage conversion unit (202), and the source electrode of the fourth power transistor (M4) and the drain electrode of the fifth power transistor (M5) are connected to the power supply voltage in common; the source of the fifth power transistor (M5) is connected to the output terminal (ea _ out) of the error amplifier;
when the second power transistor and the sixth power transistor detect currents larger than a preset threshold value within a first preset time when the LDO is started, the voltage difference of the voltage drop of the source electrode of the third power transistor (M3) is subjected to single-stage common-source amplification through the third power transistor (M3) and the fourth power transistor (M4), the amplified signal reaches the grid electrode of the fifth power transistor (M5), the fifth power transistor (M5) is triggered to be conducted, and the output end of the error amplifier is pulled up through the source electrode of the fifth power transistor (M5) so as to limit the current output to a load by the power transistor (M1).
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| CN112398326B (en) * | 2019-08-13 | 2022-04-05 | 国民技术股份有限公司 | Soft start device and method based on multi-output device, power supply and chip |
| CN113325910A (en) * | 2021-05-13 | 2021-08-31 | 博流智能科技（南京）有限公司 | Soft start system and control method suitable for low dropout linear regulator |
| CN113644639B (en) * | 2021-08-27 | 2025-02-18 | 成都芯源系统有限公司 | EFUSE switch circuit and control method |
| CN114510112A (en) * | 2022-01-12 | 2022-05-17 | 电子科技大学 | A Transient Enhancement Circuit for Low-Power Fully Integrated Low-Dropout Linear Regulators |
| CN114415774B (en) * | 2022-01-21 | 2025-01-21 | 南京元络芯科技有限公司 | An LDO circuit to solve the LDO power-on transition |
| CN114583676B (en) * | 2022-03-29 | 2023-09-12 | 拓尔微电子股份有限公司 | Circuit and method for reducing LDO output voltage overshoot |
| CN114546017B (en) * | 2022-04-27 | 2022-08-16 | 南京芯力微电子有限公司 | Undervoltage area current clamping circuit of linear voltage stabilizer and linear voltage stabilizer |
| CN115826661A (en) * | 2022-12-30 | 2023-03-21 | 思瑞浦微电子科技（苏州）股份有限公司 | Low dropout regulator based on quick response load change |
| CN118585026B (en) * | 2024-08-02 | 2024-10-18 | 成都瓴科微电子有限责任公司 | LDO overcurrent protection circuit |
| CN119002615B (en) * | 2024-10-25 | 2025-01-24 | 成都市易冲半导体有限公司 | A low voltage drop linear regulator and electronic equipment |
| CN119165914B (en) * | 2024-11-20 | 2025-05-30 | 苏州悉芯射频微电子有限公司 | An undershoot voltage generating circuit |
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| US7402987B2 (en) * | 2005-07-21 | 2008-07-22 | Agere Systems Inc. | Low-dropout regulator with startup overshoot control |
| KR101620345B1 (en) * | 2009-04-07 | 2016-05-12 | 삼성전자주식회사 | LDO regulator and semiconductor device having the same |
| JP5527070B2 (en) * | 2010-07-13 | 2014-06-18 | 株式会社リコー | Constant voltage circuit and electronic device using the same |
| US8598861B2 (en) * | 2011-12-19 | 2013-12-03 | O2Micro Inc. | Circuit and method for providing a reference signal |
| KR101409736B1 (en) * | 2012-09-05 | 2014-06-20 | 주식회사 실리콘웍스 | Low Dropout Circuit Enabling Controlled Start-up And Method For Controlling Thereof |
| CN104423407B (en) * | 2013-08-28 | 2016-05-25 | 联发科技（新加坡）私人有限公司 | Low pressure difference linear voltage regulator and starting method thereof, electronic installation and chip |
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| CN105988495B (en) * | 2015-02-09 | 2018-02-02 | 钜泉光电科技(上海)股份有限公司 | A kind of LDO overshoot protections circuit |
| US9602001B1 (en) * | 2015-11-06 | 2017-03-21 | National Cheng Kung University | Buck converter with a variable-gain feedback circuit for transient responses optimization |
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