CN109856876B - Array substrate, display panel, display device and driving method - Google Patents

Abstract

The present application discloses an array substrate, a display panel, a display device and a driving method, wherein the array substrate includes N rows and M columns of pixel units, each pixel unit includes a first transistor and a second transistor arranged in series, the first transistor The source of the first transistor is used to connect to the source drive circuit, the gate of the first transistor is used to connect to the gate drive circuit, the drain of the first transistor is connected to the source of the second transistor, and the second transistor is connected to the source of the second transistor. The drains of the transistors are connected to the pixel capacitors; the gates of the second transistors in odd rows are connected to the same first control signal line; the gates of the second transistors in even rows are connected to the same second control signal line, the Both the first control signal line and the second control signal line are used for connecting with the display driving IC. The above solution can solve the problem of crosstalk.

Description

Array substrate, display panel, display device and driving method

technical field

The present invention generally relates to the field of display technology, and specifically relates to an array substrate, a display panel, a display device and a driving method.

Background technique

At present, the development of science and technology is getting faster and faster. With the rapid development of science and technology, the mobile phone industry has also developed by leaps and bounds. The only communication functions of traditional functional mobile phones can no longer meet people's requirements for mobile phones. People's requirements for mobile phones With the addition of functions such as audio and video playback, consumers pay more and more attention to the details of the content displayed on the mobile phone.

In the current mobile phone display design scheme, the TFT (Thin Film Transistor; thin film field effect transistor) that controls the GOA (Gate Driver On Array) of each row to turn on will only be turned on once in a frame (Frame). The pixel capacitor (also called the storage capacitor) of the liquid crystal is charged, and the TFT is in an off state for the rest of the time. If the TFT remains off for a long time, there will be a problem that the TFT is stressed (that is, the TFT characteristics change), and the TFT unit after being stressed cannot be completely turned off, so that the data of other rows will be charged into the pixels of the row. The problem in the pixel capacitor, which will also form a crosstalk (Crosstalk) phenomenon.

SUMMARY OF THE INVENTION

In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide an array substrate, a display panel, a display device and a driving method to solve the problem of crosstalk in the prior art.

In a first aspect, the present invention provides an array substrate, which includes N rows and M columns of pixel units, each pixel unit includes a first transistor and a second transistor arranged in series, and the source of the first transistor is used to connect to a source driving circuit , the gate of the first transistor is used to connect to the gate drive circuit, the drain of the first transistor is connected to the source of the second transistor, and the drain of the second transistor is connected to the pixel capacitor;

The gates of the second transistors in odd-numbered rows are connected to the same first control signal line; the gates of the second transistors in even-numbered rows are connected to the same second control signal line, and the first control signal line is connected to the same second control signal line. The second control signal lines are all used for connecting with the display driving IC.

Further, the first transistor and the second transistor are both TFTs.

In a second aspect, the present invention provides a display panel including the above-mentioned array substrate.

In a third aspect, the present invention provides a display device comprising the above-mentioned array substrate; or, the above-mentioned display panel.

In a fourth aspect, the present invention provides a method for driving the above-mentioned array substrate, including:

Input the first scan voltage signal to the first transistors of each row in sequence through the gate driving circuit;

When the first scan voltage signal is input to the first transistors of the odd-numbered rows, the display driver IC is used to input the first control voltage signal to the first control signal line, so that the first transistor and the second transistor of the current row are turned on for at least partial overlap;

When the first scan voltage signal is input to the first transistors of the even-numbered rows, the display driver IC is used to input the second control voltage signal to the second control signal line, so that the first and second transistors of the current row are turned on for at least partially overlapped.

Further, the first scan voltage signal, the first control voltage signal and the second control voltage signal are all square wave signals.

Further, the pulse widths of the first control voltage signal and the second control voltage signal are both larger than the pulse widths of the first scan voltage signal.

In the above solution, each pixel unit is provided with a first transistor and a second transistor in series, and only when the first transistor and the second transistor are both turned on, the corresponding pixel capacitor is charged through the source driving circuit. In addition, since the gates of the second transistors in the odd-numbered rows are connected to the same first control signal line; the gates of the second transistors in the even-numbered rows are connected to the same second control signal line, the When the transistors and the second transistors are both turned on, the second transistors in the remaining odd or even rows are also turned on. Since the array substrate is scanned row by row in one frame, for each row scanned, the corresponding odd or even rows The second transistor of the row performs a switching action, which avoids the problem of being stressed due to the transistor being in the off state for a long time, so that at least the second transistor can be completely turned off, that is, when the pixel capacitor in the current row is being charged, The second transistors in other rows are completely turned off, which solves the problem of crosstalk that occurs because the transistors cannot be completely turned off after being stressed. In addition, since both the first control signal line and the second control signal line are used to connect to the display driver IC, the display driver IC outputs the voltage signal that controls the on-off of the second transistor, rather than the gate driver circuit to generate and control the second transistor. The on-off voltage signal of the two transistors makes it applicable to the existing gate drive circuit. In the case that the gate drive circuit does not need to be modified, the design complexity and difficulty are reduced, and the subsequent gate drive circuit does not need to be modified. The formation process of the invention utilizes rapid mass production.

Description of drawings

Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is a schematic diagram of a circuit principle of an array substrate provided by an embodiment of the present invention;

FIG. 2 is a timing diagram for driving the first transistor and the second transistor to be turned off according to an embodiment of the present invention.

Detailed ways

The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the related invention, but not to limit the invention. In addition, it should be noted that, for the convenience of description, only the parts related to the invention are shown in the drawings.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

As shown in FIG. 1, the array substrate provided by the present invention includes N rows and M columns of pixel units 1, each pixel unit 1 includes a first transistor 2 and a second transistor 3 arranged in series, and the source of the first transistor 2 is used for connecting Source drive circuit, the gate of the first transistor 2 is used to connect to the gate drive circuit, the drain of the first transistor 2 is connected to the source of the second transistor 3, and the drain of the second transistor 3 is connected to the pixel capacitor 4; an odd number The gates of the second transistors 3 of the rows are connected to the same first control signal line Control_odd; the gates of the second transistors 3 of the even rows are connected to the same second control signal line Control_even, and the first control signal lines Control_ Both the odd and the second control signal lines Control_even are used to connect with the display driving IC.

Among them, N and M are both natural numbers, which can be set according to the resolution. For example, FIG. 1 shows 1920 rows and 1080 columns. The intersection of 1920 rows of gate lines and 1080 columns of source lines defines 1920 rows and 1080 columns of pixel units arranged in a matrix. Among them, 1920 rows of gate lines are marked as Gate1, Gate2, Gate3...Gate1918, Gate1919, Gate1920; 1080 columns of source lines are marked as Source line1, Source line2, Source line3...Sourceline1078, Source line1079, Source line1080, need It should be noted that the signal in each line below uses the same item number as the line on which it is located. For example, if the gate line in the first row is marked as Gate1, the first scan voltage signal on the gate line is also marked as Gate1; The gate line of the second row is marked as Gate2, then the first scan voltage signal on the gate line is also marked as Gate2, and so on. The sources of the first transistors 2 in each column are connected to the source driving circuit through the corresponding source lines. The gates of the first transistors 2 in each row are connected to the gate driving circuit through the corresponding gate lines.

The gate drive circuit is used to input the first scan voltage signal to the corresponding first transistor 2 through each gate line to control the on-off of the first transistor 1, and the source drive circuit is used to pass each source line, in the current When both the first transistor 2 and the second transistor 3 of the row are turned on, data is written into the pixel capacitor 4 of the current row, that is, the pixel capacitor 4 of the current row is charged. When the first transistor 2 of the current row is turned on, the display driver IC (Integrated Circuit; integrated circuit) is connected through the corresponding first control signal line or the second control signal line to connect to the corresponding odd or even row. The second transistor 3 is input with a control voltage signal, so that the second transistor 3 in the corresponding odd or even row is turned on. If the current row is an odd row, the control voltage signal is input to the second transistors 3 of all odd rows through the first control signal line Control_odd; if the current row is even row, then the second control signal line Control_even is used to input the control voltage signal to all even rows The second transistor 3 of the input control voltage signal.

In the above scheme, each pixel unit 1 is provided with a first transistor 2 and a second transistor 3 in series, and only when the first transistor 2 and the second transistor 3 are both turned on, the corresponding pixel capacitance is connected to the corresponding pixel capacitance through the source driving circuit. 4 to charge. In addition, since the gates of the second transistors 3 in the odd-numbered rows are connected to the same first control signal line; the gates of the second transistors 3 in the even-numbered rows are connected to the same second control signal line. When the first transistor and the second transistor 3 are both turned on, the second transistors 3 in the remaining odd or even rows are also turned on. Since the array substrate is scanned row by row in one frame, then for each row scanned, the corresponding The second transistor 3 of the odd-numbered or even-numbered rows performs a switching operation, which avoids the problem of being stressed due to the transistor being in the off state for a long time, so that at least the second transistor 3 can be completely turned off, that is, the switching operation is performed in the current row. When the pixel capacitor is charged, the second transistors 3 in other rows are completely turned off, which solves the problem of crosstalk that occurs because the transistors cannot be completely turned off after being stressed. Also, since the first control signal line Control_odd and the second control signal line Control_even are both used to connect with the display driver IC, the display driver IC outputs the control voltage signal for controlling the on-off of the second transistor 3, rather than through the display driver IC. The gate drive circuit is used to generate a control voltage signal that controls the on-off of the second transistor 3, so that it can be applied to the existing gate drive circuit, and the design complexity and difficulty are reduced without modification of the gate drive circuit. , and do not need to modify the formation process of the subsequent gate drive circuit, and use the rapid mass production.

Further, the first transistor 2 and the second transistor 3 are both TFTs.

In a second aspect, an embodiment of the present invention further provides a display panel, including the above-mentioned array substrate. The specific structure of the array substrate can be referred to in the above-mentioned embodiment, and details are not repeated here.

In a third aspect, an embodiment of the present invention further provides a display device, including the above-mentioned array substrate; or the above-mentioned display panel. The display device is, for example, but not limited to, a monitor, a mobile phone, a tablet computer, and the like.

In a fourth aspect, an embodiment of the present invention further provides a method for driving an array substrate, including sequentially inputting a first scan voltage signal to the first transistors 2 in each row through a gate driving circuit;

When the first scan voltage signal is input to the first transistor 2 of the odd-numbered row, the first control voltage signal Control_odd is input to the first control signal line through the display driver IC, so that the first transistor 2 of the current row is connected to the first transistor 2 of the current row. The turn-on times of the two transistors 3 at least partially overlap;

When the first scan voltage signal is input to the first transistor 2 of the even row, the display driver IC is used to input the second control voltage signal Control_even to the second control signal line, so that the first transistor 2 of the current row is connected to the second control signal line. The turn-on times of the two transistors 3 at least partially overlap.

Specifically, as shown in FIG. 2 , the first scan voltage signal, the first control voltage signal and the second control voltage signal are all square wave signals. The first scan voltage signal is generated by a gate drive circuit, which is similar to a shift register. It generates a square wave signal to control the on-off of the first transistor in one row, and when another square wave signal is generated, it controls the next row. The on-off of the first transistor, and so on, perform on-off control of the first transistor row by row, that is, perform row-by-row scanning. In this way, when the rising edge of the first control voltage signal Control_odd and the first scanning voltage signals Gate1, Gate3... The scan voltage signal completes a pull-down action. Similarly, when the first control voltage signal Control_even and the first scan voltage signal Gate2, Gate4... or Gate1920 are turned on at the rising edge, the first transistor 2 and the second transistor corresponding to the even row are turned on. When the transistor is 3, the first scan voltage signal of the odd row completes a pull-down action.

For example, when the gate driving circuit inputs the first scanning voltage signal Gate1 to the first transistor 2 in the first row, the display driving IC inputs the first control voltage signal Control_odd to the first control signal line, the first scanning voltage signal Gate1 At least part of the time overlap with the first control voltage signal Control_odd. In the overlapped part, the first transistor 2 and the second transistor 3 are both turned on. At this time, the pixel capacitor of the corresponding pixel is charged through the source drive circuit. At this time , and the second transistors 3 in the remaining odd-numbered rows perform an on-off operation once.

When the gate driving circuit inputs the first scanning voltage signal Gate2 to the first transistor 2 in the second row, the display driving IC inputs the first control voltage signal Control_even to the first control signal line, the first scanning voltage signal Gate2 and The first control voltage signal Control_even overlaps at least part of the time. In the overlapped part, the first transistor 2 and the second transistor 3 are both turned on. At this time, the pixel capacitor of the corresponding pixel is charged through the source driving circuit. At this time, The second transistors 3 in the remaining even-numbered rows perform an on-off operation once.

When the gate driving circuit inputs the first scanning voltage signal Gate3 to the first transistor 2 in the third row, the display driving IC inputs the first control voltage signal Control_odd to the first control signal line, the first scanning voltage signal Gate3 and the first control signal line A control voltage signal Control_odd overlaps at least part of the time. In the overlapped part, the first transistor 2 and the second transistor 3 are both turned on. At this time, the pixel capacitor of the corresponding pixel is charged through the source driving circuit. At this time, the rest The second transistors 3 in the odd-numbered rows perform an on-off operation once.

When the gate driving circuit inputs the first scanning voltage signal Gate4 to the first transistor 2 in the fourth row, the display driving IC inputs the first control voltage signal Control_even to the first control signal line, the first scanning voltage signal Gate4 and the first control signal line A control voltage signal Control_even overlaps at least part of the time. In the overlapped part, the first transistor 2 and the second transistor 3 are both turned on. At this time, the pixel capacitor of the corresponding pixel is charged through the source driving circuit. At this time, the rest The second transistors 3 in the even-numbered rows perform an on-off operation once.

By analogy, the scanning of all rows in a frame is completed. During the scanning of all rows in a frame, the second transistor 3 performs multiple on-off actions, which avoids the transistor being in the off state for a long time. The problem is that at least the second transistor 3 can be completely turned off, that is, when the pixel capacitor 4 in the current row is being charged, the second transistors 3 in other rows are completely turned off, which solves the problem that the transistor cannot be completely turned off after being stressed, and The problem of crosstalk arises.

Further, the pulse widths of the first control voltage signal Control_odd and the second control voltage signal Control_even are both larger than the pulse width of the first scan voltage signal. As a preferred manner, the pulse widths of the first control voltage signal Control_odd and the second control voltage signal Control_even are equal to Width2, the pulse width of the first scan voltage signal is Width1, Width ₂ >Width ₁ , that is, the first The duty cycle of the first control voltage signal Control_odd and the second control voltage signal Control_even is greater than the duty cycle of the first scan voltage signal. Width ₂ >Width ₁ can ensure that the first transistor 2 and the second transistor 3 have a long enough common turn-on time, so that the pixel capacitor 4 has a sufficient charging time. In order to ensure the charging time, a preferred implementation is that the high-level period of the first scan voltage signal is completely included in the high-level period of the first control voltage signal/second control voltage signal.

The above description is only a preferred embodiment of the present application and an illustration of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solution formed by the specific combination of the above-mentioned technical features, and should also cover, without departing from the inventive concept, the above-mentioned technical features or their Other technical solutions formed by any combination of equivalent features. For example, a technical solution is formed by replacing the above-mentioned features with the technical features disclosed in this application (but not limited to) with similar functions.

Claims (1)

1. A driving method for an array substrate, wherein the array substrate comprises N rows and M columns of pixel units, each pixel unit comprises a first transistor and a second transistor arranged in series, and the source of the first transistor is connected to the source drive circuit, the gate of the first transistor is used to connect to the gate drive circuit, the drain of the first transistor is connected to the source of the second transistor, the drain of the second transistor Connect the pixel capacitor; The gates of the second transistors in odd-numbered rows are connected to the same first control signal line; the gates of the second transistors in even-numbered rows are connected to the same second control signal line, and the first control signal line is connected to the same second control signal line. The second control signal lines are all used for connecting with the display driver IC; The driving method includes: Input the first scan voltage signal to the first transistors of each row in sequence through the gate driving circuit; When the first scan voltage signal is input to the first transistors of the odd-numbered rows, the display driver IC is used to input the first control voltage signal to the first control signal line, so that the first transistor and the second transistor of the current row are turned on for at least partial overlap; When the first scan voltage signal is input to the first transistors of the even-numbered rows, the display driver IC is used to input the second control voltage signal to the second control signal line, so that the first and second transistors of the current row are turned on for at least partial overlap; the first scan voltage signal, the first control voltage signal and the second control voltage signal are all square wave signals; The pulse width of the first control voltage signal and the second control voltage signal are both larger than the pulse width of the first scan voltage signal.

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