CN100456089C - A pixel structure of a liquid crystal display array substrate and its manufacturing method - Google Patents
A pixel structure of a liquid crystal display array substrate and its manufacturing method Download PDFInfo
- Publication number
- CN100456089C CN100456089C CNB2006100572434A CN200610057243A CN100456089C CN 100456089 C CN100456089 C CN 100456089C CN B2006100572434 A CNB2006100572434 A CN B2006100572434A CN 200610057243 A CN200610057243 A CN 200610057243A CN 100456089 C CN100456089 C CN 100456089C
- Authority
- CN
- China
- Prior art keywords
- electrode
- layer
- insulation course
- transparent pixels
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
本发明公开了一种液晶显示器阵列基板的像素结构，包括玻璃基板，形成于玻璃基板上的栅线，栅电极，数据线，源电极，漏电极，掺杂层，有源层，第一绝缘层，第二绝缘层，透明像素电极，钝化层，其特征在于：透明像素电极和栅线、栅电极之间有横向的隔断槽；透明像素电极和数据线、源电极之间有纵向的隔断槽。本发明同时也公开了制造该像素结构的方法。本发明适用于TFT的4mask工艺中有ITO直接沉积在源、漏电极上，并进行钝化层刻蚀的工艺中。在不增加现有工艺和设计成本的基础上，本发明可以提高生产的成品率，同时降低产品修复的数目，从而降低生产成本。
The invention discloses a pixel structure of an array substrate of a liquid crystal display, comprising a glass substrate, a gate line formed on the glass substrate, a gate electrode, a data line, a source electrode, a drain electrode, a doped layer, an active layer, and a first insulating layer. layer, a second insulating layer, a transparent pixel electrode, and a passivation layer, which are characterized in that: there is a transverse partition groove between the transparent pixel electrode and the grid line and the gate electrode; there is a vertical groove between the transparent pixel electrode and the data line and the source electrode. partition slot. The invention also discloses a method for manufacturing the pixel structure. The present invention is applicable to the process in which ITO is directly deposited on the source and drain electrodes and the passivation layer is etched in the 4mask process of TFT. On the basis of not increasing the cost of the existing process and design, the invention can increase the yield of production and reduce the number of product repairs, thereby reducing the production cost.
Description
Technical field
The present invention is applicable in the manufacturing field of thin film transistor (TFT) (TFT), and particularly being applied to has transparent pixels electrode (ITO) directly to be deposited on source, the drain electrode in 4 masks (mask) technology of TFT, and carries out in the technology of passivation layer etching.
Background technology
Usually, in the conventional mask manufacturing process of tft array, adopt as Fig. 1 structure shown in Figure 2.
The process sequence of this structure: at first, on the glass substrate 20 of cleaning, deposit grid metal level (as: Mo earlier, Al/Nd, Cu etc.), on metal, deposit ground floor insulating layer film (as: SiNx) again, the active tunic of deposition on the ground floor insulation course, and then dopant deposition tunic (as: a-Si or p-Si).Adopting for the first time, mask obtains grid island figure: doped layer 29, active layer 28, ground floor insulation course 25, gate electrode 26.Then, deposition second layer insulation course 24 on doped layer 29, deposit transparent metal electrode layer (as: tin indium oxide) on second layer insulation course 24.Adopt second layer mask to arrive and define channel part and the transparent pixels electrode part that we need, and expose doped layer 29.Then, sedimentary origin leaks metal level, and uses the metal electrode of mask formation for the third time.Last deposit passivation layer 21, etching exposes transparent pixels electrode 27 parts then.
When the transparent pixels electrode 27 of this technology and source electrode 23, drain electrode 22 at two adjacent step process, so when taking place to cause transparent pixels electrode 27 or gate electrode 26, source electrode 23, drain electrode 22 residual easily in the technology owing to reasons such as dust or photoresist are residual, these two electrodes are short-circuited easily, perhaps influence memory capacitance, in the array processes test, must repair.Manufacturing cost and hold facility time have been increased.
Summary of the invention
The objective of the invention is to overcome the defective of prior art, on the basis that does not increase existing technology and design cost, improve the yield rate of producing, reduce the number that product is repaired simultaneously, thereby reduce production costs.
To achieve these goals, the invention provides a kind of dot structure of LCD (Liquid Crystal Display) array substrate, comprising: comprise glass substrate, be formed at the grid line on the glass substrate, gate electrode, data line, the source electrode, drain electrode, doped layer, active layer, the ground floor insulation course, second layer insulation course, transparent pixels electrode, passivation layer is characterized in that: have between transparent pixels electrode and grid line, the gate electrode between horizontal partition grooves and/or transparent pixels electrode and data line, the source electrode partition grooves is longitudinally arranged.
To achieve these goals, the present invention also provides a kind of one pixel structure process method of LCD (Liquid Crystal Display) array substrate simultaneously, comprise the steps: the first step, on the glass substrate of cleaning, deposit the grid metal earlier, on metal, deposit the ground floor insulation course again, on the ground floor insulation course, deposit active layer, and then the dopant deposition layer; Adopt mask definition for the first time to obtain grid island figure, i.e. doped layer, active layer, ground floor insulation course, gate electrode; Second step, deposition second layer insulation course on doped layer, deposit transparent metal electrode on second time insulation course; Adopt the definition of second layer mask to obtain channel part and transparent pixels electrode part, and expose doped layer; The 3rd step, sedimentary origin, leakage metal level, and use mask definition for the third time to obtain source, leakage metal electrode; The 4th step, deposit passivation layer, and use the 4th mask definition to obtain partition grooves zone and transparent pixels electrode part.
Use the 4th mask definition in wherein said the 4th step, with figure transfer above passivation layer the time, in the horizontal, expose a part and be in second layer insulation course between transparent pixels electrode and grid line, the gate electrode; In the vertical, expose a part and be in second layer insulation course between transparent pixels electrode and data line, the source electrode; Also can be for only in the horizontal, expose a part and be in second layer insulation course between transparent pixels electrode and grid line, the gate electrode; Or only in the vertical, expose a part and be in second layer insulation course between transparent pixels electrode and data line, the source electrode, and in etching technics subsequently, need be at isolation channel zone etching passivation layer and second layer insulation course.
The present invention is with respect to prior art, and on the basis that does not increase existing technology and design cost, the present invention can improve the yield rate of production, reduces the number that product is repaired simultaneously, thereby reduces production costs.
Below, with reference to accompanying drawing and embodiments of the invention content of the present invention is described in detail.
Description of drawings
Fig. 1 is the vertical view of the TFT-LCD pixel of conventional method;
Fig. 2 is conventional method TFT-LCD pixel portion sectional view A-A ';
Fig. 3 is the vertical view of TFT-LCD pixel among the present invention;
Fig. 4 is the cross-sectional views B-B ' of TFT-LCD pixel portion among the present invention;
Fig. 5 is the sectional view C-C ' of TFT-LCD pixel portion among the present invention;
Fig. 6 is a horizontal direction partition grooves synoptic diagram of the present invention;
Fig. 7 is a longitudinal direction partition grooves synoptic diagram of the present invention;
Identify among the figure: 20, glass substrate; 21, passivation layer; 22, drain electrode; 23, source electrode; 24, second layer insulation course; 25, ground floor insulation course; 26, gate electrode; 27, transparent pixels electrode; 28, active layer; 29, doped layer; 30, horizontal partition grooves; 31, partition grooves longitudinally.
Embodiment
In common process, shown in Figure 2 as Fig. 1, use the electrode of passivation layer as protection TFT, this step process is not done deep research, the present invention proposes under the prerequisite of the etching of passivation layer having been carried out research.
The present invention utilizes common process to make the TFT device portions of TFT-LCD substrate.Its four mask exposure concrete structures such as Fig. 3, Fig. 4 and shown in Figure 5.
On the glass substrate 20 of cleaning, deposit grid metal level (as: Mo, Al/Nd at first, earlier, Cu etc.), on metal, deposit ground floor insulating layer film (as: SiNx) again, the active tunic of deposition on the ground floor insulation course, and then dopant deposition tunic (as: a-Si or p-Si).Employing mask for the first time obtains grid island figure, that is: doped layer 29, active layer 28, ground floor insulation course 25, gate electrode 26.Then, deposition second layer insulation course 24 on doped layer 29, deposit transparent metal electrode layer (as: tin indium oxide) on second layer insulation course 24.Adopt second layer mask to define channel part and transparent pixels electrode 27 parts that obtain needs, and expose doped layer 29.Then, sedimentary origin, leakage metal level, and use the source of mask formation for the third time electrode 23, drain electrode 22.Last deposit passivation layer 21.When making the PVX mask, the present invention changes: the edge of passivation layer 21 is exposed to outside the transparent pixels electrode 27.In the horizontal just, passivation layer 21 edges are between gate electrode 26, grid line and the transparent pixels electrode 27; In the vertical, passivation layer 21 edges are between source electrode 23, data line and the transparent pixels electrode 27.Then in etching technics,, etch away the passivation layer on it,, etch away passivation layer and second layer insulation course 24 in the isolation channel zone in transparent pixels electrode 27 zones.Photoetching and etching by the 4th mask so in the horizontal, formed horizontal partition grooves 30 by etching between transparent pixels electrode 27 and gate electrode 26, grid line; In the vertical, between transparent pixels electrode 27 and source electrode 23, data line, form partition grooves 31 longitudinally, as Fig. 6, shown in Figure 7.
As shown in Figure 6, transversely working as gate electrode 26, grid line or active layer 28 takes place residual, gate electrode 26, grid line and transparent pixels electrode 27 produce additional capacitors, with design load generation deviation, in common process, can only solve this problem by reparation, in the present invention by between passivation layer 21 and gate electrode 26, grid line, having formed horizontal partition grooves 30, this horizontal partition grooves 30 just can be cut off gate electrode 26, grid line is residual or active layer 28 is residual redundances in etching process, so just can not influence the function of pixel.
As shown in Figure 7, vertically fooled source electrode 23, data line takes place residual or transparent pixels electrode 27 takes place when residual, transparent pixels electrode 27 and source electrode 23 can take place in this moment, the short circuit of data line, make the disabler of TFT pixel switch, solve this problem by reparation during conventional method, pass through in the present invention at passivation layer 21 and source electrode 23, form partition grooves 31 longitudinally between the data line, this longitudinally partition grooves 31 in etching process with source electrode 23, residual or the transparent pixels electrode of data line 27 residual parts are cut off, and the function of pixel is replied again normally like this.
Adopt the mode that partition grooves laterally, is vertically all arranged to be optimum mode in the present invention.In addition, the present invention can also can only have partition grooves for horizontal direction only for longitudinal direction has partition grooves.
More than explanation and accompanying drawing have provided specific implementations of the present invention, but self-evident, the present invention can carry out various distortion by those skilled in the art and implement.But the embodiment that has been out of shape can not break away from technological thought of the present invention or prospect is individually understood, and must regard the structure and the manufacture method that comprise in the appending claims of the present invention as.
Claims (7)
1, a kind of dot structure of LCD (Liquid Crystal Display) array substrate comprises glass substrate, is formed at the grid line on the glass substrate, gate electrode, data line, source electrode, drain electrode, doped layer, active layer, ground floor insulation course, second layer insulation course, the transparent pixels electrode, passivation layer is characterized in that: horizontal partition grooves is arranged between transparent pixels electrode and grid line, the gate electrode.
2, the dot structure of a kind of LCD (Liquid Crystal Display) array substrate according to claim 1 is characterized in that: between described transparent pixels electrode and data line, the source electrode partition grooves is longitudinally arranged.
3, a kind of dot structure of LCD (Liquid Crystal Display) array substrate comprises glass substrate, is formed at the grid line on the glass substrate, gate electrode, data line, source electrode, drain electrode, doped layer, active layer, ground floor insulation course, second layer insulation course, the transparent pixels electrode, passivation layer is characterized in that: between described transparent pixels electrode and data line, the source electrode partition grooves is longitudinally arranged.
4, a kind of one pixel structure process method of LCD (Liquid Crystal Display) array substrate comprises the steps:
The first step, deposition grid metal on the glass substrate of cleaning deposits the ground floor insulation course again on metal earlier, deposits active layer on the ground floor insulation course, and then the dopant deposition layer; Adopt mask definition for the first time to obtain grid island figure, i.e. doped layer, active layer, ground floor insulation course, gate electrode;
Second step, deposition second layer insulation course on doped layer, deposit transparent metal electrode on second layer insulation course; Adopt mask definition for the second time to obtain channel part and transparent pixels electrode part, and expose doped layer;
The 3rd step, sedimentary origin, leakage metal level, and use mask definition for the third time to obtain source, leakage metal electrode;
The 4th step, deposit passivation layer, and use the 4th mask definition to obtain partition grooves zone and transparent pixels electrode part.
5, the one pixel structure process method of a kind of LCD (Liquid Crystal Display) array substrate according to claim 4, it is characterized in that: use the 4th mask definition in described the 4th step, with figure transfer above passivation layer the time, in the horizontal, expose a part and be in second layer insulation course between transparent pixels electrode and grid line, the gate electrode.
6, according to the one pixel structure process method of claim 4 or 5 described a kind of LCD (Liquid Crystal Display) array substrates, it is characterized in that: use the 4th mask definition in described the 4th step, with figure transfer above passivation layer the time, in the vertical, expose a part and be in second layer insulation course between transparent pixels electrode and data line, the source electrode.
7, the one pixel structure process method of a kind of LCD (Liquid Crystal Display) array substrate according to claim 6, it is characterized in that: use the 4th mask definition in described the 4th step, in etching technics, need be at the isolation channel zone etching passivation layer and second insulation course.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100572434A CN100456089C (en) | 2006-03-09 | 2006-03-09 | A pixel structure of a liquid crystal display array substrate and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100572434A CN100456089C (en) | 2006-03-09 | 2006-03-09 | A pixel structure of a liquid crystal display array substrate and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101034215A CN101034215A (en) | 2007-09-12 |
| CN100456089C true CN100456089C (en) | 2009-01-28 |
Family
ID=38730835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100572434A Active CN100456089C (en) | 2006-03-09 | 2006-03-09 | A pixel structure of a liquid crystal display array substrate and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100456089C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552241B (en) * | 2008-04-03 | 2010-11-03 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and liquid crystal display device |
| CN101599497B (en) * | 2009-05-19 | 2011-07-06 | 昆山龙腾光电有限公司 | Thin film transistor array substrate and method for forming same |
| KR101248005B1 (en) * | 2009-11-17 | 2013-03-27 | 엘지디스플레이 주식회사 | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
| CN102778793B (en) * | 2011-12-22 | 2015-06-24 | 北京京东方光电科技有限公司 | Liquid crystal display device as well as array substrate and manufacturing method thereof |
| CN202404339U (en) | 2012-01-12 | 2012-08-29 | 京东方科技集团股份有限公司 | Array substrate and display device comprising same |
| CN103700670B (en) * | 2013-12-20 | 2016-08-17 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN106971976B (en) * | 2017-05-15 | 2019-09-27 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN110867474B (en) * | 2019-11-26 | 2022-01-25 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel |
| CN111880346B (en) * | 2020-08-19 | 2022-11-29 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and repairing method for broken wires of wires |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183570A (en) * | 1996-11-26 | 1998-06-03 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
| US20040263724A1 (en) * | 2003-06-26 | 2004-12-30 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for repairing liquid crystal display including the same |
| CN1728363A (en) * | 2004-07-27 | 2006-02-01 | 三星电子株式会社 | Thin film transistor array panel and manufacturing method thereof |
-
2006
- 2006-03-09 CN CNB2006100572434A patent/CN100456089C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1183570A (en) * | 1996-11-26 | 1998-06-03 | 三星电子株式会社 | Liquid crystal display using organic insulating material and manufacturing methods thereof |
| US20040263724A1 (en) * | 2003-06-26 | 2004-12-30 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for repairing liquid crystal display including the same |
| CN1728363A (en) * | 2004-07-27 | 2006-02-01 | 三星电子株式会社 | Thin film transistor array panel and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101034215A (en) | 2007-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100456089C (en) | A pixel structure of a liquid crystal display array substrate and its manufacturing method | |
| CN103268878B (en) | The manufacture method of tft array substrate, tft array substrate and display unit | |
| KR101414043B1 (en) | Thin film transistor substrate | |
| US20100133541A1 (en) | Thin film transistor array substrate, its manufacturing method, and liquid crystal display device | |
| CN202033562U (en) | Liquid crystal display array base plate | |
| CN101656233B (en) | Method for manufacturing thin film transistor substrate | |
| KR100931874B1 (en) | TFT-LCD Array Board | |
| CN102881657B (en) | CMOS (complementary metal oxide semiconductor) transistor and manufacturing method thereof | |
| CN102033370B (en) | Liquid crystal display substrate and manufacturing method thereof | |
| CN101609236A (en) | Method for manufacturing thin film transistor array substrate | |
| WO2020224095A1 (en) | Array substrate, preparation method, and display apparatus | |
| KR20070074344A (en) | Thin film transistor substrate, manufacturing method thereof and liquid crystal display device including the same | |
| KR100910445B1 (en) | Method for manufacturing array substrate | |
| CN101840121B (en) | Array substrate and manufacturing method thereof | |
| CN104599959A (en) | Manufacturing method and structure of low-temperature polycrystalline silicon TFT substrate | |
| WO2021120378A1 (en) | Array substrate and method for manufacturing same | |
| US20210366942A1 (en) | Array substrate and manufacturing method thereof | |
| CN101615594A (en) | The manufacture method of thin-film transistor array base-plate | |
| CN101840118A (en) | Liquid crystal display panel and manufacture method thereof | |
| WO2019200834A1 (en) | Manufacturing method of tft array substrate and tft array substrate | |
| CN102646713B (en) | Pixel structure of thin film transistor liquid crystal display and manufacturing method thereof | |
| CN103311182B (en) | Manufacture the method for the array base palte of in-plane switching mode liquid crystal display device | |
| KR102037514B1 (en) | Thin Film Transistor Panel For Flat Panel Display Device And Method For Manufacturing The Same | |
| KR20020094809A (en) | Fabricating method of thin film transistor - liquid crystal display | |
| JP2010165866A (en) | Method of manufacturing thin film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20071019 Address after: No. 8 West Central Road, Beijing economic and Technological Development Zone Applicant after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Co-applicant after: BOE Technology Group Co., Ltd. Address before: No. 10 Jiuxianqiao Road, Beijing, Chaoyang District Applicant before: BOE Technology Group Co., Ltd. |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |