CN101706551B - Testing circuit for forecasting failure of back bias voltage unstability of integrated circuit - Google Patents

Abstract

The invention discloses a test circuit for predicting failure of integrated circuit negative bias voltage instability. It mainly includes a measuring tube (3), a constant current bias circuit, a voltage reference circuit, a hysteresis comparator circuit, a bidirectional switch circuit, and a switch tube (12). The measuring tube (3) is used to measure threshold voltage drift, the constant current bias circuit provides constant current bias for the measuring tube (3), the voltage reference circuit provides a reference voltage for the hysteresis comparator, and the bidirectional switch circuit makes the measuring tube (3) Toggle between degenerate and test. During the degradation period, the switch tube (12) turns off the hysteresis comparator, the constant current bias circuit and the voltage reference circuit to reduce power consumption; when testing, the switch tube (12) turns on the hysteresis comparator, the constant current bias circuit And the voltage reference circuit, when the source-drain voltage of the measuring tube is greater than the reference voltage, the hysteresis comparator outputs a high level, indicating that the integrated circuit is about to fail. The invention can be used to predict the failure of negative bias instability effect.

Description

A Test Circuit for Predicting the Failure of Integrated Circuit Negative Bias Instability

technical field

The invention belongs to the technical field of electronic circuits, and relates to a negative bias voltage instability failure real-time prediction circuit, which can be used for testing and life prediction of large/ultra-scale integrated circuits.

Background technique

At present, the reliability testing technology of integrated circuits has been more and more widely used and developed, such as aerospace electronics, avionics, automotive electronics and other fields. With the development of integrated circuits, the system-on-chip (SOC), including the central processing unit, memory, and peripheral circuits, has a great effect on improving system performance, reducing system energy consumption, reducing system electromagnetic interference, and improving system integration. Helping, it not only conforms to the trend of light and thin products, but also has high-efficiency integration performance, so it is replacing the main solution of integrated circuits and has become an inevitable trend in the development of current microelectronic chips. However, this also brings difficulties to failure testing of integrated circuits. Because SOC is an integrated circuit with complex structure, the embedded nature and complex relationship prevent SOC from performing fault detection, fault prediction and life prediction like traditional integrated circuits.

The integration and power density of modern integrated circuits continue to increase, and the temperature of the integrated circuit is very high when the circuit is working. When the PMOSFET at high temperature has a negative bias stress on the gate, problems such as threshold voltage drift, leakage current reduction, and transconductance degradation will occur, which will affect the function of the circuit and even lead to the failure of the integrated circuit. For the failure problem caused by the instability of negative bias voltage, there is no real-time prediction technology for this failure mode.

Contents of the invention

The object of the present invention is to provide a test circuit for real-time forecasting of the failure of the integrated circuit negative bias instability for the failure of the integrated circuit under the negative bias instability effect, so as to realize the detection of the integrated circuit under the negative bias instability effect. The failure caused by stress is tested in real time and the failure alarm is issued.

The purpose of the present invention is achieved like this:

1. Technical principles

When the integrated circuit is working, the threshold voltage of the PMOSFET under the negative bias instability stress will drift, so the present invention adopts the method of monitoring the change of the PMOSFET threshold voltage to fail the integrated circuit under the influence of the negative bias instability effect. Call the police. In the test circuit of the present invention, the gate and drain of the measuring tube PMOSFET used for testing are short-circuited, and a constant current is applied to the source end of the PMOSFET to bias it so that it is in a saturated state. When the PMOSFET is under the stress of negative bias instability, the absolute value of its threshold voltage increases continuously. At this time, the voltage between the source and drain of the PMOSFET also increases continuously, and the change of the drain-source voltage of the PMOSFET is equal to the change of the threshold voltage. As the negative bias voltage instability stress continues, when the drift of the PMOSFET threshold voltage continues to increase, the hysteresis comparator will compare the voltage between the source and drain of the PMOSFET with the set voltage, if the voltage between the source and drain of the PMOSFET is greater than Set value, the hysteresis comparator will output high level, indicating that the integrated circuit is about to fail.

2. Circuit structure

The test circuit for predicting the failure of the negative bias voltage instability of integrated circuits of the present invention includes a measuring tube PMOSFET, two NMOSFETs and a power supply to form a constant current bias circuit, a PMOSFET and two NMOSFETs to form a voltage reference circuit, five NMOSFETs and six The PMOSFET forms a hysteresis comparator circuit, three bidirectional switch circuits, an inverter, and a switching tube PMOSFET; the measuring tube PMOSFET is used to measure threshold voltage drift; the constant current bias circuit provides a constant current bias for the PMOSFET; the PMOSFET and The voltage reference circuit composed of two NMOSFETs provides a reference voltage to the hysteresis comparator circuit and provides bias to the gate of the NMOSFET; three bidirectional switch circuits switch the measuring tube PMOSFET between stress degradation and testing; the inverter Invert the gate stress of the measuring tube PMOSFET and transmit it to its drain; the switching tube PMOSFET turns off the hysteresis comparator circuit, constant current bias circuit and voltage reference circuit during the stress period of the measuring tube PMOSFET to reduce the power When testing, the switching tube turns on the hysteresis comparator circuit, constant current bias circuit and voltage reference circuit. When the voltage between the source and drain of the measuring tube PMOSFET is greater than the reference voltage V _REF , the hysteresis comparator circuit outputs a high level , indicating that the integrated circuit is about to fail.

The present invention has the following advantages:

(1) The test circuit of the present invention uses a hysteresis comparator circuit to judge the drift of the measuring tube threshold voltage, avoiding false alarms caused by recovery effects in the failure of negative bias instability.

(2) The test circuit of the present invention uses the constant current bias circuit in the circuit to bias the measuring tube without providing an additional current source.

(3) The test circuit of the present invention uses the voltage reference circuit in the circuit to provide a reference voltage for the hysteresis comparator circuit, without additionally providing a voltage reference.

(4) During the stress degradation period of the measuring tube, the hysteresis comparator circuit, the constant current bias circuit and the voltage reference circuit in the test circuit of the present invention are in a standby state, which reduces the power consumption demand of the integrated circuit.

(5) The test circuit of the present invention places the degradation process of the measuring tube in the integrated circuit, directly adopts the electrical stress experienced by the device in the integrated circuit to apply to the measuring tube, and the temperature stress experienced by the measuring tube is also the same as that of the integrated circuit, real-time It accurately reflects the change process of the temperature stress of the integrated circuit.

Description of drawings

Fig. 1 is a test schematic diagram of the present invention;

Fig. 2 is a test circuit diagram of the present invention;

Fig. 3 is the stress configuration diagram that the negative bias instability failure test tube of the present invention adds;

Fig. 4 is a simulation diagram of the negative bias instability failure prediction test circuit of the present invention.

specific implementation

The principle and test circuit of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 1 , under the stress of negative bias instability, the threshold voltage of PMOSFET will drift, and the present invention predicts the failure of negative bias instability based on this phenomenon. PMOSFET3 in Fig. 1 is a measuring tube, its grid and drain are short-circuited, and the measuring tube is in a saturated state at this time, and the constant current source 2 is connected to its source, and a constant current bias is applied to it. The voltage on the source 4 of PMOSFET3 is:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; th</span>}}<span\; class="notranslate">\; -</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; DS</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&delta;</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}}}$

where V _th is the initial threshold voltage, C _ox is the oxide layer capacitance per unit area, μ is the carrier mobility, I _DS is the saturation leakage current, W is the channel width of PMOSFET3, L is the channel length of PMOSFET3, $\mathrm{\&delta;}=\frac{\mathrm{\&gamma;}}{2{(2{\mathrm{\&psi;}}_f-V_{\mathrm{BS}})}^{1/2}},$ γ is the lining bias coefficient, ψ _F is the Fermi potential of the substrate silicon, and V _BS is the lining source voltage.

When the threshold voltage drifts under the stress of negative bias instability, the absolute value of the drift ΔV _th is equal to the voltage change ΔV _o at point 4. If V _o continues to increase, the measuring tube PMOSFET3 will fail.

With reference to Fig. 2, test circuit of the present invention comprises: measuring tube, constant current bias circuit, voltage reference circuit, hysteresis comparator circuit, three bidirectional switch circuits K1～K3, inverter 24 and switching tube PMOSFET 12. The constant current bias circuit is composed of NMOSFET 7, NMOSFET 8 and power supply, the voltage reference circuit is composed of PMOSFET 9, NMOSFET 10 and NMOSFET 11, and the hysteresis comparator circuit is composed of five NMOSFETs 17-19, 21, 23 and six A PMOSFET 13-16, 20, 22 is composed. In the circuit, NMOSFET 7, NMOSFET 8, PMOSFET 9, NMOSFET 10, and NMOSFET 11 are all gate-drain short-circuit structures. These test circuit components are all designed with standard CMOS process layout, fully compatible with other integrated circuit layout processes, and integrated in the integrated circuit layout. The connection relationship of the whole circuit is as follows:

The NMOSFET 7 is connected in series with the NMOSFET 8, and the drain of the NMOSFET 8 is connected to a power supply to form a constant current bias circuit.

The drain of the PMOSFET 9 is connected to the drain of the NMOSFET 10, the source of the NMOSFET 10 is connected to the drain of the NMOSFET 11, and the source of the NMOSFET 11 is grounded, forming a voltage reference circuit to provide a reference voltage V _REF for the hysteresis comparator.

The source of the PMOSFET 13 is connected to the source of the PMOSFET 14 and connected to the drain of the switching tube PMOSFET 12, the gate of the PMOSFET 13 is connected to the gate of the PMOSFET 14 and the drain of the PMOSFET 13 respectively, and the drain of the PMOSFET 14 is connected to the drain of the PMOSFET 14. The drains of the PMOSFET 16 are connected, and the PMOSFET 13 and the PMOSFET 14 are the load current sources of the NMOSFET 17.

The source of the PMOSFET 15 is connected to the source of the PMOSFET 16 and connected to the drain of the switching tube PMOSFET 12, the gate of the PMOSFET 15 is connected to the gate of the PMOSFET 16 and the drain of the PMOSFET 16 respectively, and the drain of the PMOSFET 15 is connected to the drain of the PMOSFET 15. The drains of the PMOSFET 13 are connected, and the PMOSFET 15 and the PMOSFET 16 are the load current sources of the NMOSFET 18.

The gate bias of NMOSFET 19 is provided by the drain voltage of NMOSFET 10, the drain is connected to the source of NMOSFET 17, and the source is grounded, which is the tail current source of the hysteresis comparator.

The drain of the PMOSFET 20 is connected to the drain of the NMOSFET 21, the source is connected to the drain of the switching tube PMOSFET12, and the gate is connected to the drain of the PMOSFET 13. The gate of the NMOSFET 21 is connected to the drain, and is connected to the gate of the NMOSFET 23, and the source of the NMOSFET 21 is grounded.

The drain of the PMOSFET 22 is connected to the drain of the NMOSFET 23, the source is connected to the drain of the switching tube PMOSFET12, and the gate is connected to the drain of the PMOSFET 16. The source of the NMOSFET (23) is grounded.

In the test circuit, the measuring tube PMOSFET 3 is used to measure the threshold voltage drift. Since the measuring tubes are integrated in the layout of the integrated circuit, they are subjected to the same temperature stress, so only negative bias stress needs to be applied to the measuring tubes. During the operation of the integrated circuit, the bidirectional switch circuits K1, K2, and K3 are switched to K1a, K2a, and K3a respectively. The source of the measuring tube is connected to the power supply, the gate is connected to the electrical stress V _stress , and the drain is connected to the inverse signal of V _stress . Studies have shown that if static stress is applied to the measuring tube, the life of the measuring tube will be greatly reduced, which cannot reflect the actual life of the integrated circuit. Therefore, the test circuit of the present invention applies a negative bias stress as shown in Figure 3 to the measuring tube. Wherein the stress waveform 5 shown in Figure 3a is loaded on the grid of the measuring tube, the waveform 5 is inverted by the inverter 24 to obtain the waveform 6 shown in Figure 3b, and the waveform is loaded on the drain of the measuring tube, and then The source of the measuring tube is connected to the power supply, so that the measuring tube is under dynamic negative bias stress. This kind of stress takes the recovery effect into consideration, and can truly reflect the degradation of the integrated circuit under the stress of negative bias instability. During the degradation of the measuring tube, the test signal of the grid of the switch tube 12 is at a high level, the switch tube 12 is cut off, the hysteresis comparator circuit, the constant current bias circuit and the voltage reference circuit are in a standby state, which reduces the power consumption of the integrated circuit need.

During measurement, the test signal of the gate of the switching tube 12 is switched to a low level, so that the switching tube is turned on. At the same time, the bidirectional switch circuits K1, K2, K3 are switched to K1b, K2b, K3b respectively. The source of the measuring tube PMOSFET3 is connected to the constant current bias circuit, and its gate and drain are grounded at the same time. At this time, the voltage V _out between the source and drain of the PMOSFET3 is transmitted to the gate of the NMOSFET 17 in the hysteresis comparator circuit. If the voltage V _out' between the source and drain of the measuring tube PMOSFET3 is less than V _REF , the PMOSFET 22 is turned off, the NMOSFET 23 is turned on, and the output of the Out point is low level. When the measuring tube degrades under the stress of negative bias instability, so that the voltage V _out` between the source and drain of the measuring tube PMOSFET 3 is greater than V _REF , the PMOSFET 22 is turned on, and the NMOSFET 23 is turned off. The output of the Out point is as shown in Figure 4 If it shows a high level, it indicates that the integrated circuit is about to fail.

Claims (10)

1. A test circuit for predicting the failure of integrated circuit negative bias voltage instability is characterized in that: it comprises measuring tube PMOSFET3, the constant current bias circuit that NMOSFET7 and NMOSFET8 and power supply form, the voltage reference that PMOSFET9 and NMOSFET10, NMOSFET11 form Circuit, five NMOSFET17, NMOSFET18, NMOSFET19, NMOSFET21, NMOSFET23 these five tubes and PMOSFET13, PMOSFET14, PMOSFET15, PMOSFET16, PMOSFET20, PMOSFET22 these six tubes form a hysteresis comparator circuit, three bidirectional switch circuits (K1, K2 , K3), an inverter (24), a switching tube PMOSFET12; the NMOSFET7, NMOSFET8, PMOSFET9, NMOSFET10, and NMOSFET11 are gate-drain short-circuit structures; the measuring tube PMOSFET3 is used for measuring threshold voltage drift; the constant current bias circuit Provide constant current bias to PMOSFET3; The voltage reference circuit that this PMOSFET9 forms with NMOSFET10 and NMOSFET11 provides reference voltage to hysteresis comparator circuit, and provides bias to the gate of NMOSFET19; Three bidirectional switch circuits (K1, K2, K3 ) makes PMOSFET3 switch between stress degradation and testing; inverter (24) inverts the gate stress of PMOSFET3 and transmits it to its drain; the switching tube PMOSFET12 closes the hysteresis comparator circuit during PMOSFET3 stress , constant current bias circuit and voltage reference circuit to reduce power consumption; when testing, the switching tube PMOSFET12 turns on the hysteresis comparator circuit, constant current bias circuit and voltage reference circuit, when the voltage between the source and drain of PMOSFET3 is greater than the reference When the voltage V _{REF is high} , the hysteresis comparator circuit outputs a high level, indicating that the integrated circuit is about to fail. 2. The test circuit according to claim 1, characterized in that: during the stress degradation period, the source of the measuring tube PMOSFET3 is connected to the power supply, the gate and the drain are respectively connected to the stress voltage of opposite phase, during the test, three bidirectional switches The circuits (K1, K2, K3) are switched at the same time, so that the source of the measuring tube PMOSFET3 is connected to the constant current bias circuit composed of NMOSFET7, NMOSFET8 and the power supply, and its gate and drain are grounded at the same time. The voltage is delivered to a hysteretic comparator circuit. 3. The test circuit according to claim 1, characterized in that: NMOSFET7 and NMOSFET8 are connected in series, the drain of this NMOSFET8 is connected to a power supply, forming a constant current bias circuit, and the source of this NMOSFET7 is connected with the drain of PMOSFET3, giving The measuring tube supplies a constant current. 4. The test circuit according to claim 1, characterized in that: the drain of the PMOSFET9 is connected to the drain of the NMOSFET10, the source of the NMOSFET10 is connected to the drain of the NMOSFET11, the source of the NMOSFET11 is grounded, and the voltage reference circuit formed is A hysteretic comparator provides a reference voltage V _REF . 5. test circuit according to claim 1 is characterized in that: the source of PMOSFET13 is connected with the source of PMOSFET14 and is connected with the drain of switching tube PMOSFET12, and the drain of PMOSFET13 gate is connected with the gate of PMOSFET14 and PMOSFET13 respectively. The drain of PMOSFET14 is connected with the drain of PMOSFET16. 6. The test circuit according to claim 1, characterized in that: the source of PMOSFET15 is connected with the source of PMOSFET16 and connected with the drain of switching tube PMOSFET12, the gate of PMOSFET15 is connected with the gate of PMOSFET16 and the drain of PMOSFET16 respectively The drain of PMOSFET15 is connected with the drain of PMOSFET13. 7. The test circuit according to claim 1, characterized in that: the source of the NMOSFET17 is connected to the source of the NMOSFET18, the drain of the NMOSFET17 is connected to the drain of the PMOSFET13, and the gate of the NMOSFET17 is connected to the drain of the NMOSFET7; The drain of the NMOSFET 18 is connected to the drain of the PMOSFET 16 , and the gate of the NMOSFET 18 is connected to the drain of the NMOSFET 11 . 8. The test circuit according to claim 1, wherein the gate of NMOSFET 19 is connected to the drain of NMOSFET 10, the drain of NMOSFET 19 is connected to the source of NMOSFET 17, and the source of NMOSFET 19 is grounded. 9. test circuit according to claim 1, is characterized in that: the drain of PMOSFET20 is connected with the drain of NMOSFET21, and the source of PMOSFET20 connects the drain of switching tube PMOSFET12, and the gate of PMOSFET20 is connected with the drain of PMOSFET13; The gate and drain of the NMOSFET 21 are connected to the gate of the NMOSFET 23 , and the source of the NMOSFET 21 is grounded. 10. test circuit according to claim 1, is characterized in that: the drain of PMOSFET22 is connected with the drain of NMOSFET23, and the source of PMOSFET22 connects the drain of switching tube PMOSFET12, and the gate of PMOSFET22 is connected with the drain of PMOSFET16; The source of this NMOSFET 23 is grounded.

Images