CN102129025A

CN102129025A - Chip test device and method

Info

Publication number: CN102129025A
Application number: CN2011100002234A
Authority: CN
Inventors: 黄新
Original assignee: Suzhou Pixcir Microelectronics Co Ltd
Current assignee: Suzhou Pixcir Microelectronics Co Ltd
Priority date: 2011-01-04
Filing date: 2011-01-04
Publication date: 2011-07-20

Abstract

The invention relates to a chip test device and a chip test method. The chip test device comprises a computer, a test board and a measuring instrument, wherein the computer is connected with the test board through a field programmable gate array (FPGA) panel. In the chip test method, various tested projects of a chip can be tested by operating the computer and automatic operation is achieve because the test board is connected with the computer through the FPGA panel; the time of a tester is also saved; and the test efficiency is improved.

Description

Apparatus for testing chip and method

Technical field

The present invention relates to the semiconductor production technical field of measurement and test, refer in particular to a kind of apparatus for testing chip and method.

Background technology

For the function of proofing chip with guarantee chip quality, after finishing, chip manufacturing must whether can reach the function that the deviser expects to judge chip earlier through test.Existing information is at first according to test philosophy test loop to be put up when test chip, imports corresponding test vector to chip to be measured then, carries out the test of respective item when waiting chip to place corresponding state again.In general, some projects are arranged usually, when needs are tested a certain project, need to set up a corresponding test loop, just have to realize this moment by manual line for the test of chip.Such as the voltage of wanting test chip, just voltage table need be connected in the circuit under test earlier; And if want the electric current of test chip, just must again reometer be connected in the circuit under test.According to the method described above, for several projects of test chip, the various corresponding circuits of manual repeatedly connection just.So, not only taken tester's plenty of time, and testing efficiency can descend significantly also.

So we wish can just can once finish by computing machine some test events automatically for the user provides a kind of new method, and test result can be fed back in the computing machine again, analyze for the tester.

Summary of the invention

The actual technical matters to be solved of the present invention is how to provide a kind of efficient, the apparatus for testing chip of robotization and method.

In order to realize above-mentioned purpose of the present invention, the invention provides a kind of device of chip testing, it comprises computing machine, test board and surveying instrument, described computing machine is connected by the FPGA plate with described test board.

The present invention also provides a kind of method of testing of chip, and its step is as follows: at first, programming makes the FPGA plate have function corresponding; Secondly, send instruction to the FPGA plate by computing machine, the relay after decoding on the control test board forms different test loops; At last, send order to the FPGA plate by computing machine, described FPGA plate sends to test board with corresponding test vector, is returned to computing machine by surveying instrument and finishes test.

The proving installation of chip of the present invention and method, owing to utilized the test loop that relay forms on the test board, so thereby can form the various test events that predefined various test loop can be realized chip fast by the computer control test board.Owing to adopt the testing procedure of robotization not only to save tester's time, but also test result passed back on the computing machine, be convenient to analyze, so improved testing efficiency.

Description of drawings

Fig. 1 is the connection diagram of apparatus for testing chip of the present invention;

Fig. 2 is the process flow diagram of chip detecting method of the present invention.

Embodiment

The present invention is further illustrated below in conjunction with drawings and Examples.

Please refer to shown in Figure 1ly, proving installation of the present invention mainly comprises computing machine, FPGA (field programmable gate array) plate, test board and testing tool.Described chip is fixed on the test board, and described test board is relevant with chip, the chip that different test boards is corresponding different; Described computing machine is connected with the FPGA plate by serial ports, and described FPGA plate is connected by winding displacement with test board again; One end of described testing tool is linked computing machine by specific communications protocol bus, and the other end is connected on the test board by test probe.So, described computing machine and described test board just can realize transmitting detecting information by the FPGA plate.

Please refer to shown in Figure 2ly, before carrying out test chip, earlier described computing machine, FPGA plate, test board and testing tool are done corresponding the connection according to shown in Figure 1.Described chip is seated on the relevant position of test board, needs during owing to test chip place certain state just can carry out the test of correlation parameter chip, so need utilize test vector.And described test vector is obtained by software emulation by the design engineer, thus need with some test vectors by downloaded to the FPGA plate.Starting program makes the firm and hard existing two kinds of functions of FPGA, and a kind of function is to make described FPGA plate control test board; Another kind of function is the described test vector of storage; Secondly, send instruction to described FPGA plate by computing machine, because the various test loops that described test board is made up of relay constitute, so the relay that above-mentioned instruction is controlled after decoding on the described test board forms different test loops, promptly described FPGA plate control test board forms test loop; At last, send order to the FPGA plate by computing machine again, described FPGA plate sends to test board with corresponding test vector, begin test, because chip is connected by testing tool with computing machine, thus just the information that tests out can be returned to computing machine by surveying instrument, to finish test.

If existing chip has N test event, at first need programming to make firm and hard existing two functions of described FPGA, not only have the function of control test board but also have the function of the described test vector of storage, be burnt on the described FPGA plate after the programming then; Then, with the test vector under the test event by downloaded to described FPGA plate; Select pattern under a certain project to be measured by computing machine, instruction is sent on the described FPGA plate, the relay after decoding on the described test board of control forms corresponding loop; Send order to described FPGA plate by computing machine again, the test vector that described FPGA plate will this project to be measured sends on the test board, transfers back in the computing machine by surveying instrument again, and a certain like this project to be measured has just been finished.And to other project to be measured, after this utilize computing machine to continue to send corresponding instruction and be used on test board, forming corresponding test loop, send a command on the test board by computing machine again, at last test result is transferred back on the computing machine, analyze for the tester.So thereby the present invention forms the various test events that predefined various test loop can be realized chip fast by the computer control test board.

Chip detecting method of the present invention owing to test board is linked to each other with computing machine by the FPGA plate, so by the operational computations machine just can test chip project various to be measured, the operation of realization robotization; And the time of having saved the tester, improved testing efficiency.

Claims

1. the device of a chip testing, it comprises computing machine, test board and surveying instrument, it is characterized in that: described computing machine is connected by the FPGA plate with described test board.

2. device as claimed in claim 1 is characterized in that: described computing machine is connected with the FPGA plate by serial ports.

3. device as claimed in claim 1 is characterized in that: described FPGA plate control test board forms test loop.

4. device as claimed in claim 1 is characterized in that: described chip is installed on the described test board.

5. device as claimed in claim 1 is characterized in that: an end of described surveying instrument links to each other with computing machine, and the other end links to each other with test board.

6. the method for testing of a kind of apparatus for testing chip as claimed in claim 1, its step is as follows:

At first, programming makes the FPGA plate have function corresponding;

Secondly, send instruction to the FPGA plate by computing machine, the relay after decoding on the control test board forms different test loops;

At last, send order to the FPGA plate by computing machine, described FPGA plate sends to test board with corresponding test vector, is returned to computing machine by surveying instrument and finishes test.

7. method as claimed in claim 6 is characterized in that: it is to instigate the FPGA plate to have two kinds of functions that described programming makes the FPGA plate have function corresponding.

8. method as claimed in claim 7 is characterized in that: described a kind of function is the control test board.

9. method as claimed in claim 7 is characterized in that: described another kind of function is the storage test vector.

10. method as claimed in claim 6 is characterized in that: after the described programming, need with some test vectors by downloaded to the FPGA plate.