CN102360566B - A radiation-resistant hardening method for SRAM programming points and its realization circuit - Google Patents

Abstract

The invention belongs to the technical field of microelectronics and particularly discloses a method and a realization circuit for reinforcing the irradiation resistance of programming points of a static random access memory (SRAM) based on a look-up table field programmable gate array (LUTFPGA). In the method, memristors are embedded into the traditional SRAM unit due to the programmable characteristics of the memristors, and then a write circuit is added. The memristors are configured into asymmetrical storage unit structures by programming the memristors during use. The memristors are in high-resistance and low-resistance states, and the process is compatible with the traditional complementary metal-oxide-semiconductor (CMOS) process. The asymmetrical structure is completely free from a single event upset (SEU) effect and a multiple bit upset (MBU) effect caused by single particles.

Description

A radiation-resistant hardening method for SRAM programming points and its realization circuit

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a radiation-resistant reinforcement method of a static random memory unit structure SRAM programming point and a realization circuit thereof. the

Background technique

Because FPGA has the advantages of high integration, high performance, low design cost and reconfigurability, it is widely used in the aviation field. In particular, their short programming times and the ability to be configured by the user any number of times make SRAM-based FPGAs very valuable in the field of remote tasks. It is generally believed that microelectronic devices are very sensitive to high-energy particles in the space environment, and the effect of ionizing radiation will lead to single event upset (Single Event Upset, SEU) in memory cells. With the continuous evolution of integrated circuit technology, SEU has become the main constraint for aerospace applications of contemporary microelectronic devices represented by deep submicron feature sizes. For the SRAM type FPGA, a large number of foreign experimental results show that this type of unhardened device has a very low switching threshold (usually LET _th <2 MeV cm ² mg-1)[2], and its application in the aviation field will face serious problems. Radiation environment reliability risk.

Traditional SRAM reinforcement structures mainly include HIT, BAE and DICE [3] and so on. Among them, the DICE (dual interlocked cell) structure is a structure that attracts the most attention in the design of redundant reinforcement, because it has four storage nodes, and the information change of a single storage node caused by the single event effect can be passed through the other three Feedback fixes for nodes. However, as the process size decreases, the distance between these storage nodes in the layout becomes smaller, and heavy ions with a certain incident angle can easily cause the storage values of sensitive nodes in the same N-well or P-well to change simultaneously, This causes the memory cell to flip. the

The present invention strengthens the traditional SRAM unit by adopting a memristor (switching resistor or memristor [1]), and designs a new storage unit rSRAM. A memristor is a memory resistor element with two terminals. It has two resistance states: high resistance state and low resistance state. If a certain value of forward voltage is added, its resistance becomes low resistance, and when a certain value of reverse voltage is added, its resistance becomes high resistance. The manufacturing process of the memristor is compatible with the traditional CMOS process, and it can be integrated in the drain of the transistor during tape-out without increasing the area. The invention adopts the idea of asymmetric storage, and the rSRAM unit is completely immune to the single event effect. the

Contents of the invention

The purpose of the present invention is to provide a method for hardening the traditional SRAM-based FPGA storage unit against radiation and its implementation circuit, so as to eliminate the problem of single event upset (SEU) and multi-bit upset (MBU) caused by single event . the

The invention provides a method for strengthening the anti-radiation of the storage unit of the FPGA based on SRAM, which uses the programmable characteristics of the memristor to embed it into the traditional SRAM unit, and then adds a write circuit; then, when using , by programming the memristor to configure it into an asymmetric memory cell structure. the

The implementation circuit based on the above-mentioned anti-radiation hardening method, that is, the improved SRAM unit, is denoted as rSRAM. the

Specifically, at least one memristor is added to the drains of the PMOS transistor and the NMOS transistor at the two storage nodes of the existing SRAM unit, and the lower electrode of the two electrodes of the memristor is connected to the drain terminal of the transistor. Both ends of the resistor are connected with at least one programming transistor. the

An rSRAM structure is shown in Figure 2, which improves the traditional SRAM unit, that is, the two storage nodes A and B of the traditional SRAM unit and the cross-coupled four transistors (M1, M2, M3, M4) Add 4 memristors between the drains, these 4 memristors are respectively recorded as R1, R2, R3, R4, each memristor has two programming transistors at both ends, a total of 6 transistors (M5, M6, M7, M8, M9, M10), in which the transistor M6 and the transistor M9 are responsible for both the state programming of the memristor and the reading and writing of the memory cell. When in use, by programming the memristors, configure the resistance states of the four memristors as follows: the memristor connected to the drain of the transistor in the OFF state is configured as a high-impedance state, and the drain of the transistor connected to the ON state is configured as a high resistance state. The poles of the memristor are configured in a low-resistance state, making it an asymmetric memory cell structure. Wherein, storage node A is a common connection point among transistors M1 , M2 and M6 , and storage node B is a common connection point among transistors M3 , M4 and M9 , as shown in FIG. 1 . the

Specifically, R1 is added between the storage node A and the transistor M1, R2 is added between the storage node A and the transistor M2, R3 is added between the storage node B and the transistor M3, and R1 is added between the storage node B and the transistor M4. R4. The two ends of R1 are respectively connected to the programming transistor M5 and the programming transistor M6, the two ends of R2 are respectively connected to the programming transistor M6 and the programming transistor M7, the two ends of R3 are respectively connected to the programming transistor M8 and the programming transistor M9, and the two ends of R4 are respectively connected to the programming transistor M9, programming transistor M10. In use, the memristor is programmed into an asymmetric memory cell structure. Specifically: if the storage node A stores "1" and the storage node B stores "0", the resistance state of the memristors R2 and R3 is configured as high resistance, and the resistance state of the memristors R1 and R4 is configured as low resistance; If the storage node A stores "0" and the storage node B stores "1", the resistance states of the memristors R2 and R3 are configured as low resistance, and the resistance states of the memristors R1 and R4 are configured as high resistance. the

When using the circuit of the present invention, the two nodes that store information (such as A and B in Figure 2), when the information stored in one of the nodes is "1", between this node and the node GND (ground) All of the memristors in VDD are programmed to a high-impedance state, and at least one of the memristors between this node and node VDD is programmed to a low-impedance state. Another node that stores information stores a value of "0", all memristors between this node and node VDD (power supply) are programmed to a high-impedance state, all memristors between this node and node GND , at least one is programmed to a low-impedance state. the

The single-ion bombardment simulation of the reinforced structure rSRAM was carried out, and the simulation results showed that the single-particle threshold of the structure reached more than 100 MeV cm ² mg-1.

The rSRAM structure of the present invention is applicable to all programming points in FPGA, such as programmable logic unit (CLB), programmable IO module (IOB), programmable interconnection, and programming points in Block RAM. Figure 3 and Figure 4 are two application examples. the

Description of drawings

Figure 1 is a traditional SRAM cell. the

Figure 2 shows the reinforced rSRAM unit. the

Figure 3 shows a possible application of rSRAM in a traditional LUT structure. the

Figure 4 shows a possible application of rSRAM in a conventional programmable interconnect switch. the

Detailed ways

Each memristor can be configured into a high- or low-resistance state through a transistor connected to its two terminals. For example, to program the memristor R1 into a low-impedance state, the NMOS transistors M5 and M6 must be turned on, P1 (source terminal of transistor M5) is connected to GND (ground point), node BL1 (source terminal of transistor M6) and The voltage difference between the nodes P1 is a positive programming voltage; if the memristor R1 is to be programmed into a high resistance state, the voltage difference between the nodes BL1 and P1 is a negative programming voltage. The programming method of R3 is the same as that of R1. Memristor R2 is programmed by turning on transistors M6, M7, the voltage difference between node BL1 and node P2 (source of transistor M7) is a positive programming voltage; to program R1 to a high-impedance state, node BL1 and node The voltage difference between P2 is the negative programming voltage. The programming method of R4 is the same as that of R2. the

To store data "1" in node A and data "0" in node B, R1 and R4 should be low resistance, and R2 and R3 should be high resistance. If data "0" will be stored in node A and data "1" will be stored in node B, R2 and R3 should be programmed as low resistance, and R1 and R4 should be programmed as high resistance. After the resistance state setting of the memristor is completed, the power is turned off, and then the power is turned on. When the power is turned on, all write transistors are turned off. After the data of the rSRAM storage unit is stable, the stored value is the value desired by the user. the

Assumption: Node A stores "1", and Node B stores "0". R1/R4 is programmed as low impedance and R2/R3 is programmed as high impedance. The sensitive nodes are the drains of transistors M2 and M3 which are in the off state when illuminated by heavy ions. When the drain of transistor M2 (or transistor M3) is hit by heavy ions, node n2 (n3) (where node n2 is the connection point of transistor M2 and memristor R2, and node n3 is the connection point of transistor M3 and memristor R3 point) the voltage decreases (increases). If there were no memristor in the circuit, the memory cell would flip due to its feedback structure. But now the existence of R2 (R3) makes the feedback time longer. At the same time, because R2 and R3 are in a high-impedance state, they play a role of voltage division, so that the voltage of nodes A and B can never reach the flipping threshold voltage. The voltage at the storage node is stabilized, thereby providing immunity to single event effects. The principle of single particle immunity is the same when node A stores "0" and node B stores "1". the

references:

[1] Wei Lu, Kuk-Hwan Kim, Ting Chang, et al, “Two-terminal resistive switches (memristors) for memory and logic applications”, ASPDAC.2011, Page(s): 217 – 223

[2] Yui C C , Swift G M, Carmichael C, et al. "SEU mitigation testing of xilinx virtex II FPGAs". In: IEEE Radiation Effects Data Workshop. Monterey: IEEE, 2003. 92-97

[3] T. Calin, M. Nicolaidis, and R. Velazco, "Upset Hardened Memory Design for Submicron CMOS Technology", IEEE Transactions on Nuclear Science, Vol 43, No. 6, December 1996, pp. 2874-2878.

Claims (3)

1. A kind of SRAM programming point anti-radiation strengthening method, it is characterized in that: First, the memristor is embedded in the existing SRAM cell, and the write circuit is added; Then, when in use, by programming the memristors, the resistance states of the four memristors are configured as follows: the memristor connected to the drain of the transistor in the OFF state is configured as a high-impedance state, and the memristor connected to the drain of the transistor in the ON state is configured as a high-impedance state. The memristor at the drain of the transistor is configured in a low-resistance state, making it an asymmetric memory cell structure. 2. A realization circuit based on the method according to claim 1, characterized in that: at least one memristor is respectively added to the drain electrodes of the PMOS transistor and the NMOS transistor at the two storage nodes of the existing SRAM unit, and the memristor The lower electrode of the two electrodes of the memristor is connected to the drain terminal of the transistor, and at least one programming transistor is connected to both ends of each memristor; When it is used, its storage node A and storage node B, when the information stored in one of the nodes is "1", all the memristor programming between this node and the node GND are in a high-impedance state, in All memristors between this node and node VDD, at least one is programmed to a low resistance state; another node storing information stores a value of "0", all memristors between this node and node VDD are programmed of all memristors between this node and node GND, at least one is programmed to a low resistance state. 3. The implementation circuit according to claim 2, characterized in that: the existing SRAM unit is improved as follows: at the 2 storage nodes A and B of the existing SRAM unit, 4 transistors (M1 , M2, M3, M4) add 4 memristors between the drains, these 4 memristors are recorded as R1, R2, R3, R4 respectively; specifically, add R1 , R2 is added between storage node A and transistor M2, R3 is added between storage node B and transistor M3, R4 is added between storage node B and transistor M4; both ends of R1 are respectively connected to programming transistor M5, programming transistor M6, R2 The two ends of R3 are respectively connected to the programming transistor M6 and the programming transistor M7, the two ends of R3 are respectively connected to the programming transistor M8 and the programming transistor M9, and the two ends of R4 are respectively connected to the programming transistor M9 and the programming transistor M10; Programming makes it an asymmetric memory cell structure; specifically: if the storage node A stores "1" and the storage node B stores "0", then the resistance state of the memristor R2 and R3 is configured as high resistance, and the memristor The resistance state of R1 and R4 is configured as low resistance; if storage node A stores "0" and storage node B stores "1", then the resistance state of memristors R2 and R3 is configured as low resistance, and memristors R1 and R4 The resistance state is configured as high resistance.

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