CN102651233B - Composite memory - Google Patents

Abstract

The invention discloses a compound memory. The composite memory contains several composite storage units. The composite memory unit includes: a floating gate subunit; and a resistance random access memory (RRAM) subunit formed on the drain of the floating gate subunit; wherein, when the RRAM subunit is used as a memory module, the floating gate subunit is used as a gate module; and the RRAM When the subunit is in a low resistance state, the floating gate subunit acts as a memory module. The invention comprehensively utilizes the advantages of high density, high reliability, small crosstalk and high tolerance of the floating gate storage mode and the advantages of low power consumption, high speed and simple structure of the RRAM storage mode.

Description

Composite memory

technical field

The invention relates to the technical field of memory in the microelectronics industry, in particular to a compound memory.

Background technique

The current semiconductor memory market is represented by volatile Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM) and non-volatile "Flash" memory (Flash). With the development and popularization of various portable digital products such as mobile storage devices, mobile phone communication devices, and digital cameras, the market demand for non-volatile data storage has further increased. In order to improve storage density and data storage reliability, based on traditional floating gate Structured Flash memory is facing severe challenges. To this end, the industry has conducted a lot of research on the next-generation non-volatile semiconductor memory technology, and various new memory technologies have been developed rapidly. For example, the improved Charge Trap Flash (CTF) memory and the revolutionary Resistive Random Access Memory (RRAM) are currently the two most representative research directions.

FIG. 1 is a schematic structural diagram of a CTF memory in the prior art of the present invention. As shown in FIG. 1 , the gate dielectric layer of a typical CTF memory includes a three-layer structure of a barrier layer, a storage layer and a tunneling layer. FIG. 2 is a schematic diagram of the principle of a CTF memory in the prior art of the present invention. As shown in Figure 2, the storage principle of the CTF memory is the same as that of the traditional floating gate memory, using the change of the threshold voltage before and after programming to realize the storage logic "0" and "1". CTF memory adopts charge separation storage technology, which effectively alleviates the contradiction between tunneling oxide layer and data retention capability. Discrete charge storage mainly uses storage nodes that are insulated from each other to store charge. For example, the SONOS (Si/SiO ₂ /Si ₃ N ₄ /SiO ₂ /Si) structure uses the deep level defects of the nitride itself as the charge storage medium, while the nanocrystalline structure uses the separated nanocrystals as the charge storage medium. Therefore, the local leakage channel in the tunnel oxide layer only causes leakage of a small amount of stored charge, which can greatly improve the charge retention capability of the storage device.

FIG. 3 is a schematic structural diagram of an RRAM memory in the prior art of the present invention. As shown in FIG. 3 , the RRAM memory cell mainly includes a resistive switch layer and upper and lower electrodes. FIG. 4 is a first schematic diagram of the storage principle of the prior art RRAM memory of the present invention. FIG. 5 is a second schematic diagram of the storage principle of the RRAM memory in the prior art of the present invention. As shown in Figure 4 and Figure 5, in the RRAM memory cell, the transition phenomenon of different resistance states (high and low resistance states) of certain thin film materials under the action of electric excitation is used to realize the stored logic "0" and "1". Research has found that RRAM has the advantages of low writing voltage, short writing and erasing time, non-destructive reading, simple structure, small required area, etc., and because of its high-speed writing and erasing characteristics, it is also considered to be the most promising A storage device that replaces traditional DRAM.

Table 1 performance comparison table of prior art CTF memory and RRAM memory of the present invention

memory CTF RRAM non-volatile have have write power high Low write voltage high Low data retention better There are fluctuations write time 1μs 10ns erase time 10ms 30ns read time 50ns 20ns write energy high Low density high high

Table 1 is a performance comparison table of CTF memory and RRAM memory in the prior art of the present invention. As shown in Table 1, the two kinds of memory have advantages and disadvantages each other. During the process of realizing the present invention, the inventor realized that the prior art has the following technical defect: the storage mode cannot be flexibly selected according to the needs of users, so as to obtain a memory with the advantages of both storage modes.

Contents of the invention

(1) Technical problems to be solved

In order to solve the above-mentioned defects, the present invention provides a composite memory, which combines the advantages of the floating gate storage method and the RRAM storage method, and flexibly selects the storage method according to user needs.

(2) Technical solutions

According to one aspect of the present invention, a composite memory unit is provided, which includes: a floating gate subunit; and a resistance random access memory (RRAM) subunit formed on the drain of the floating gate subunit; wherein, the RRAM subunit When used as a storage module, the floating gate subunit is used as a gate module; when the RRAM subunit is in a low resistance state, the floating gate subunit is used as a storage module.

Preferably, in the composite memory unit of the present invention, the floating gate subunit is a charge trapping flash CTF subunit.

Preferably, in the composite storage unit of the present invention, one electrode of the RRAM subunit is connected to the drain of the CTF subunit; the other electrode corresponding to the electrode of the RRAM subunit is used as the bit line of the composite storage unit; and the CTF subunit The gate serves as the word line of the composite memory cell.

Preferably, in the composite memory unit of the present invention, when the RRAM subunit is used as a memory module, and the CTF subunit is used as a gate module, then: when programming, the source is grounded, the word line is connected to a circuit that provides a positive bias, and the bit line It is connected to the circuit that provides the programming voltage of the RRAM subunit; or when erasing, the bit line is connected to the circuit that provides the erasing voltage; or when reading, the word line is connected to the circuit that provides the positive bias voltage, the bit line The wire is connected to a circuit that provides a read voltage.

Preferably, in the composite storage unit of the present invention, the RRAM subunit is in a low resistance state, and when the CTF subunit is used as a storage module, then: when programming, the CTF subunit adopts Fowler Nordheim (Fowler Nordheim, FN for short) Programming or channel hot electron injection (Channel Hot Electron injection, referred to as CHE) programming; or when erasing, the CTF subunit is erased by FN; or when reading, the word line of the compound memory cell and the voltage supply The circuit is connected, the bit line is connected to the circuit providing positive bias, and the source of the CTF subunit is grounded.

According to another aspect of the present invention, a compound memory is also provided. The composite memory includes a storage array, an RRAM peripheral control circuit, a floating gate peripheral control circuit and a gate circuit, wherein: the storage array includes several composite memory cells as described above, and two composite memory cells along the direction of the bit line share a source; The pass circuit is connected with the RRAM peripheral control circuit, the floating gate peripheral control circuit and the word/bit line of each storage unit, and is used to realize the selection of the storage mode of the preset composite storage unit; the RRAM peripheral control circuit is connected with the gate circuit and the gate circuit and The RRAM subunits are connected to realize the programming, erasing or reading of the RRAM subunits in the preset composite storage unit; the CTF peripheral control circuit is connected with the gate circuit and the CTF subunits to realize the preset Programming, erasing or reading of CTF subunits in composite memory cells.

(3) Beneficial effects

The present invention has following beneficial effects:

1. The present invention comprehensively utilizes the advantages of high density, high reliability, small crosstalk, and high tolerance of the floating gate storage method and the advantages of low power consumption, high speed, and simple structure of the RRAM storage method;

2. The present invention realizes the fusion of two different storage methods on a single chip, thereby meeting the storage needs of different methods, improving performance and reducing costs;

3. The preparation process of the memory of the present invention is compatible with the traditional microelectronic technology, which is beneficial to wide popularization and application.

Description of drawings

Fig. 1 is the structural representation of prior art CTF memory of the present invention;

Fig. 2 is the schematic diagram of the principle of the prior art CTF memory of the present invention;

Fig. 3 is the structural representation of the prior art RRAM memory of the present invention;

Fig. 4 is the first schematic diagram of the storage principle of the prior art RRAM memory of the present invention;

5 is a second schematic diagram of the storage principle of the prior art RRAM memory of the present invention;

6 is a schematic structural diagram of a composite storage unit according to an embodiment of the present invention;

7 is a schematic structural diagram of a composite storage unit according to an embodiment of the present invention;

Fig. 8 is the implementation flowchart of the compound storage unit of the embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a composite memory according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In a basic embodiment of the invention, a composite memory cell is presented. FIG. 6 is a schematic structural diagram of a composite storage unit according to an embodiment of the present invention. As shown in FIG. 6 , the composite memory unit of this embodiment includes: a RRAM subunit and a floating gate subunit; the RRAM subunit is formed above the drain of the floating gate subunit. Among them, the composite storage unit can be switched between two storage modes: the RRAM subunit is used as a storage module, and the CTF subunit is used as a gating module; or the RRAM subunit is in a low resistance state, and the CTF subunit is used as a storage module. In this embodiment, the floating gate subunit can be a traditional floating gate structure, preferably a charge trapping flash memory CTF subunit.

This embodiment discloses a design scheme of a multifunctional and general-purpose composite storage unit. By combining the storage technology of floating gate and RRAM in a storage array, both high-speed and low-voltage storage of RRAM subunits can be realized, and floating gate can also be realized. The high-density and high-reliability storage of the unit, the switching of different storage methods can be realized through external software control according to different storage environments.

In an exemplary embodiment of the present invention, a composite memory cell is provided. FIG. 7 is a schematic structural diagram of a composite storage unit according to an embodiment of the present invention. As shown in Figure 7, in the composite memory cell of this embodiment, one electrode of the RRAM subunit is connected to the drain of the CTF subunit; the other electrode corresponding to the electrode of the RRAM subunit is used as the bit line of the composite memory cell; and The gate of the CTF subunit serves as the word line of the compound memory unit.

In this embodiment, the drain terminal electrode of the CTF unit and the lower electrode of the RRAM are made together to form a common electrode, thereby forming a new memory unit. Through the judgment of the external environment, if a low-voltage and high-speed storage method is required, RRAM is used to store data. At this time, the CTF unit is used as a gating tube to avoid the read crosstalk problem of RRAM, and then further realize the read, write and erase of RRAM units. Operation: If you need to use CTF as a unit for storing data, first reset all RRAM cells to a low-impedance state through peripheral control circuit operations, and then perform programming, erasing, and reading operations on CTF cells.

In another exemplary embodiment of the present invention, a composite memory is provided. The composite memory includes a storage array, an RRAM peripheral control circuit, a floating gate peripheral control circuit and a gate circuit. Wherein: the memory array includes the composite memory cells disclosed above, and the two composite memory cells along the bit line direction share the source; the gating circuit is connected with the RRAM peripheral control circuit, the floating gate peripheral control circuit and the word/word of each memory cell The bit line is connected to realize the selection of the storage mode of the preset composite storage unit; the RRAM peripheral control circuit is connected to the gating circuit and the RRAM subunit to realize the programming, erasing or Reading: The CTF peripheral control circuit is connected with the gate circuit and the CTF subunit, and is used to realize programming, erasing or reading of the preset CTF subunit.

The above two embodiments have described the structural features of the composite storage unit, and the operation mode of the composite storage unit will be described below. FIG. 8 is a flow chart of implementing a composite storage unit according to an embodiment of the present invention. As shown in Figure 8, the process includes:

Step S802, sensing external environment needs;

Step S804, judging whether high-speed low-voltage storage is required, if yes, execute step S806, otherwise, execute step S812;

Step S806, determine to adopt the RRAM storage mode;

Step S808, using the CTF subunit as a gate tube;

Step S810, the corresponding RRAM subunit executes read/write/erase operations, and the process ends;

Step S812, determine to adopt the CTF storage method;

Step S814, performing RESET on all RRAM subunits to make them enter a low resistance state;

In step S816, the corresponding CTF subunit executes read/write/erase operations, and the process ends.

In this embodiment, the above step S810 specifically includes: when programming, the source is grounded, the word line is connected to a circuit that provides a positive bias voltage, and the bit line is connected to a circuit that provides a programming voltage for an RRAM subunit; or when erasing When reading, the bit line is connected to a circuit that provides an erasing voltage; or when reading, the word line is connected to a circuit that provides a positive bias voltage, and the bit line is connected to a circuit that provides a read voltage. Step S816 specifically includes: when programming, the CTF subunit adopts FN programming or channel hot electron injection CHE programming; or when erasing, the CTF subunit adopts FN erasing; or when reading, compound the word line of the memory cell It is connected with a circuit for providing a read voltage, the bit line is connected with a circuit for providing a positive bias voltage, and the source of the CTF subunit is grounded.

How the RRAM subunit and the CTF subunit implement various operations will be further discussed in detail below. FIG. 9 is a schematic structural diagram of a composite memory according to an embodiment of the present invention.

Among them, the CTF peripheral control circuit and the RRAM peripheral control circuit are connected to the storage array through the gate circuit, and the word line (WL) of the storage array is respectively connected to the word line gate tube of the CTF peripheral control circuit and the RRAM peripheral control circuit through a gate switch. The word line gating tube of the memory array is connected with the bit line gating tube of the memory array, and the bit line gating tube of the CTF peripheral control circuit and the bit line gating tube of the RRAM peripheral control circuit are connected respectively through a gating switch, and the gating switch is controlled by Strobe signal sel control. The CTF peripheral control circuit and the RRAM peripheral control circuit are respectively the peripheral control circuit of the traditional NOR floating gate memory and the RRAM peripheral control circuit of the 1T1R (one transistor one RRAM) structure.

For the composite memory as shown in FIG. 9, two cases are described.

1. When the high-speed low-voltage storage method is required, the strobe signal sel is controlled by external software (as shown in Figure 9). When sel is high level "1", the peripheral control circuit of RRAM is strobed, and RRAM is selected as the storage at this time. unit, the CTF unit acts as a gate at this time, forming a similar 1T1R structure. The SL line is grounded. When programming, a positive bias voltage V ₁ (such as 5V (guaranteed to be greater than the threshold voltage after CTF programming) is applied to the WL of the selected cell to open the channel), and the corresponding BL is programmed with RRAM Voltage V _P (usually 1~2V), when erasing, add _Verase to the corresponding BL, and when reading, add positive bias voltage V ₁ to the corresponding WL to open the channel, and add the reading voltage V _read to the corresponding BL (typically 0.2V) for reading.

2. When CTF is required as a storage unit, it is necessary to perform a Reset operation on all RRAM units to make them all low-impedance, and then set the strobe signal to "0", and the CTF peripheral control circuit is gated. The entire device is equivalent to a common CTF device, and its programming, erasing, and reading operations are consistent with common CTF devices. ground), CHE programming (eg: 10V and 8V are applied to WL and BL, SL and substrate are grounded). FN erasing can be selected for erasing (for example: apply a voltage of -15V to WL, BL and SL are floating, and the substrate is grounded); when reading, apply V _read to WL, and apply a voltage of about 1V to BL (different structures and materials will vary) Certain difference), SL is grounded.

In this embodiment, the advantages of the CTF storage device and the RRAM storage device are comprehensively utilized, and two different storage methods are realized on a single chip, thereby meeting the storage needs of different methods, improving performance, and reducing costs. Moreover, its preparation process is compatible with traditional microelectronic technology, which is conducive to wide popularization and application.

In the present invention, the selected CTF unit can be selected as the traditional SONOS (Si/SiO ₂ /Si ₃ N ₄ /SiO ₂ /Si) structure, or TANOS (TaN/AL ₂ O ₃ /Si ₃ N ₄ /SiO ₂ /Si) structure, MANOS (Metal/AL ₂ O ₃ /Si ₃ N ₄ /SiO ₂ /Si) structure, TAHOS (TaN/AL ₂ O ₃ /HIGH-K/SiO ₂ /Si) structure, MAHOS structure, or BE-SONOS structure, MAOHOS structure and similar laminated structures are all within the optional range, nanocrystalline structure, and SONOS, TANOS and other similar structures that introduce nanocrystals. Among them, the required High-K materials can be selected from Al ₂ O ₃ , HFO ₂ , TIO ₂ , HfALO, HfSiO, HfSiON and other new doped high-K media with different components.

In the present invention, the selected RRAM subunits can be unipolar devices, bipolar devices and nonpolar devices. The resistive layer material of the RRAM subunit can be perovskite oxide: R _1-x Ca _x MnO ₃ (R=Pr/La/Nd), La _0.67 Sr _0.33 MnO ₃ , SrTiO ₃ , SrZrO3, LiNbO ₃ , BaTiO ₃ ; transition metal binary oxides: NiOTiO ₂ , CuO _x , ZrO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ , Al ₂ O ₃ , CoO, HfO ₂ , MgO, VO ₂ , ZnO; solid electrolyte: SiO ₂ , WO ₃ , CuI _0.76 S _0.1 , Ag–Ge–Se, Ag-Ge-S, Ag ₂ S, Cu ₂ S, Sb ₃₅ Te ₆₅ ; organic matter: AIDCN, PVK, PS, PCm, F12TPN, PI-DPC, CuTCNQ, AgTCNQ, o-PPV, P ₃ HT; there are other materials with similar properties such as: a-Si:H, μc-Si, etc.

In the present invention, the selected common electrode material can be selected from precious metals Pt, Ag, Pd; metals W, Ti, Al, Cu commonly used in CMOS technology; metal oxides ITO, IZO, YBCO, LaAlO ₃ , SrRuO ₃ and Polycrystalline Si material.

At present, DRAM and Flash require different process flow, and in the field of single-chip system (System on chip, Soc for short), its cost is difficult to reduce. The present invention integrates RRAM and Flash storage functions in one unit, which can not only realize the high-speed storage function of DRAM, but also realize the high-density storage function of Flash, and through the control of external software, the exchange of these two functions can be realized, further Optimize the configuration of the entire storage structure. At the same time, because the preparation is completed through only one process flow, the cost is effectively reduced. Moreover, this process flow is compatible with traditional microelectronic processes, which is more conducive to widespread promotion and application.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. a composite memory, is characterized in that, this composite memory comprises storage array, RRAM peripheral control circuits, CTF peripheral control circuits and gating circuit, wherein:

Described storage array comprises several compound memory unit, and this compound memory unit comprises: CTF subelement; And the resistance random access memory RRAM subelement on the drain electrode being formed at this CTF subelement; Wherein, when described RRAM subelement is as memory module, described CTF subelement is as gating module; And described RRAM subelement is when being in low resistance state, described CTF subelement is as memory module, and along two compound memory unit common-source of bit line direction, an electrode of described RRAM subelement is connected with the drain electrode of described CTF subelement; Described RRAM subelement another electrode corresponding with described electrode is as the bit line of described compound memory unit; And the grid of described CTF subelement is as the wordline of described compound memory unit;

Described gating circuit, is connected with the word/bit line of each storage unit with described RRAM peripheral control circuits, floating boom peripheral control circuits, for realizing the selection to presetting described compound memory unit memory module;

Described RRAM peripheral control circuits, is connected with RRAM subelement with described gating circuit, for realizing programming to RRAM subelement in default compound memory unit, erasing or reading;

Described CTF peripheral control circuits, is connected with CTF subelement with described gating circuit, for realizing programming to CTF subelement in default compound memory unit, erasing or reading;

Wherein, CTF peripheral control circuits is connected with storage array by gating circuit with RRAM peripheral control circuits, the wordline of storage array is connected with the wordline gate tube of CTF peripheral control circuits and the wordline gate tube of RRAM peripheral control circuits respectively by a gating switch, the bit line of storage array is connected with the bit line strobe pipe of CTF peripheral control circuits and the bit line strobe pipe of RRAM peripheral control circuits respectively by a gating switch, and gating switch is controlled by gating signal sel:

One, when needs high velocity, low pressure storage mode, control gating signal sel is high level " 1 ", and RRAM peripheral control circuits is strobed, and now select RRAM subelement as memory module, CTF subelement is now as gating module;

Two, when needs CTF subelement is as memory module, carry out Reset operation to all RRAM unit and make it all become low resistance state, control gating signal sel reset, CTF peripheral control circuits is strobed, and now selects CTF subelement as memory module.

2. composite memory according to claim 1, is characterized in that, described RRAM subelement as memory module, when described CTF subelement is as gating module, then:

When programmed, source ground, described wordline is connected with providing the circuit of positive bias, and described bit line is connected with the circuit of the program voltage providing RRAM subelement; Or

When wiping, described bit line is connected with providing the circuit of erasing voltage; Or

When reading, described wordline is connected with providing the circuit of positive bias, and described bit line is connected with providing the circuit reading voltage.

3. composite memory according to claim 1, is characterized in that, described RRAM subelement is in low resistance state, when described CTF subelement is as memory module, then:

When programmed, CTF subelement adopts Fowler-Nordheim FN programming or channel hot electron to inject CHE programming; Or

When wiping, CTF subelement adopts FN erasing; Or

When reading, the wordline of described compound memory unit is connected with providing the circuit reading voltage, and bit line is connected with providing the circuit of positive bias, the source ground of CTF subelement.

4. composite memory according to any one of claim 1 to 3, is characterized in that, described CTF subelement is the one of following structure: rhythmo structure, nanocrystalline structure or introduce nanocrystalline rhythmo structure.

5. composite memory according to claim 4, is characterized in that: described rhythmo structure is the one in following structure: Si/SiO ₂/ Si ₃n ₄/ SiO ₂/ Si structure, TaN/AL ₂o ₃/ Si ₃n ₄/ SiO ₂/ Si structure, Metal/AL ₂o ₃/ Si ₃n ₄/ SiO ₂/ Si or TaN/AL ₂o ₃/ HIGH-K material/SiO ₂/ Si.

6. composite memory according to any one of claim 1 to 3, is characterized in that, described RRAM subelement is unipolar device, bipolar device or electrodeless device;

The change resistance layer material of described RRAM subelement is the one in following material: perovskite oxide, transition metal binary oxide, solid electrolyte, organism or a-Si:H, μ c-Si.

7. composite memory according to claim 6, is characterized in that:

Described perovskite oxide is the one in following material: R _1-xca _xmnO ₃(R=Pr/La/Nd), La _0.67sr _0.33mnO ₃, SrTiO ₃, SrZrO3, LiNbO ₃, BaTiO ₃;

Described transition metal binary oxide is the one in following material: NiOTiO ₂, CuO _x, ZrO ₂, Nb ₂o ₅, Ta ₂o ₅, Al ₂o ₃, CoO, HfO _x, MgO _x, MoO _x, VO ₂, ZnO;

Described solid electrolyte is the one in following material: SiO ₂, WO ₃, CuI _0.76s _0.1, Ag – Ge – Se, Ag-Ge-S, Ag ₂s, Cu ₂s, Sb ₃₅te ₆₅;

Described organism is the one in following material: AIDCN, PVK, PS, PCm, F12TPN, PI-DPC, CuTCNQ, AgTCNQ, o-PPV, P ₃hT.

8. composite memory according to any one of claim 1 to 3, is characterized in that: described electrode is the one in following material: Pt, Ag, Pd, W, Ti, Al, Cu, ITO, IZO, YBCO, LaAlO ₃, SrRuO ₃or polycrystalline Si.