CN103001618B - Differential switch capacitor structure low in parasitic effect and high in quality factor - Google Patents

Abstract

The invention discloses a differential switch capacitor structure low in parasitic effect and high in quality factor. Compared with the conventional differential switch capacitor structure, the differential switch capacitor structure mainly has two improvements that PMOS (p-channel metal oxide semiconductor) tubes P1 and P2 are removed, parasitic effect caused by the PMOS tubes is eliminated; and an inverter and a resistor are serially connected between an input end of a digital signal D and a drain electrode of a switch radio-frequency tube, and parasitic effect of a switch tube is reduced. The improved differential switch capacitor structure has the advantages of low parasitic effect, high quality factor and wide tuning range.

Description

The differential switched capacitor structure that the low-quality factor of a kind of ghost effect is high

Technical field

The present invention relates generally to discrete capacitor design field, the differential switched capacitor structure that especially a kind of ghost effect is low, quality factor are high.

Background technology

In recent years, the development of advancing by leaps and bounds along with wireless communication technique, multiple standards compatibility and wideband communication system become inexorable trend.As the key modules of this system, voltage controlled oscillator requires enough wide frequency coverage and harsh phase noise performance.Based on standard CMOS process varactor realize tuning LC VCO maximum can realize about 20% frequency tuning range.Meanwhile, adopt large-sized varactor easily amplitude noise to be converted into phase noise, phase noise is deteriorated.For this reason, there has been proposed employing numerical control switch capacitance technology and realize variable capacitance.But traditional switched capacitor array is made up of nmos pass transistor and capacitances in series, when NMOS tube is opened conducting resistance and when disconnecting drain terminal parasitic capacitance make that resonant tank Q value is low and phase noise performance is poor.Therefore, design parasitic effect is low, and the switching capacity that quality factor are high becomes a difficult problem for switched-capacitor design.

Fig. 1 illustrates a kind of conventional differential Switch capacitor structure realized by nmos switch pipe and metal capacitance.When switch controlling signal D is high level, nmos switch pipe N ₁, N ₂and N ₃closed, PMOS switch pipe P ₁and P ₂disconnect, switching capacity is in closure state, and now the equivalent electric circuit of Switch capacitor structure as shown in Figure 3, wherein R _oN1, R _oN2and R _oN3equivalent resistance respectively during three nmos switch pipe conductings, now switching capacity capacitance size can be expressed as:

C _ON≈C ₁//C ₂(1)

Its quality factor q can be expressed as:

$Q=\frac{1}{{\mathrm{\ω}}_0\·(C_1//C_2)\·((R_{\mathrm{ON}1}+R_{\mathrm{ON}2})//R_{\mathrm{ON}3})}---\left(2\right)$

ω in formula ₀for operating frequency, R _iON=[(μ _nc _ox) (W _i/ L) (V _gS-V _tH)] ^-1for switching tube N _iconducting resistance.Can draw from formula (2), due to the conducting resistance R of switching tube during conducting _iONexistence, the effective Q value of switching capacity reduces, thus reduces the phase noise performance of LC oscillator.

When switch controlling signal D is low level, nmos switch pipe N _iclose, PMOS switch pipe P _iclosed, switching capacity is in off-state, and now switching capacity equivalent electric circuit is as shown in Figure 4, and now switching capacity capacitance size can be expressed as:

C _OFF≈(C ₁//(C _N1par+C _par1))//(C ₂//(C _N2par+C _par2))(3)

Wherein C _parfor the parasitic capacitance that the bottom crown of metal capacitance C is formed with ground, C _nparfor the drain electrode of nmos switch pipe produces edge capacitance, its value equals W _swc _dd, wherein W _swthe width of switching tube, C _ddfor drain terminal edge unit width capacitance, unit is fF/ μm.Due to switch disconnect time, metal capacitance is not completely isolated outside resonator, but accesses in resonator after connecting with parasitic capacitance, and this effect greatly reduces the tuning range of electric capacity.

For the defect that the single-ended Switch capacitor structure of tradition exists, designer proposes the differential switched capacitor structure that a kind of ghost effect is low, quality factor are high shown in Fig. 2.Switch controlling signal D receives the grid of nmos switch pipe N1, N2 and the input of inverter INV (001,002) simultaneously, and the drain electrode of nmos switch pipe N1 meets electric capacity C ₁one end, electric capacity C ₁the other end be output P, the output of inverter INV (001) and resistance R ₁one end connect, resistance R ₁the other end connect the drain terminal of nmos switch pipe N1, the drain electrode of nmos switch pipe N2 meets electric capacity C ₂one end, electric capacity C ₂the other end be output N, the output of inverter INV (002) and resistance R ₂one end connect, resistance R ₂the other end connect the drain terminal of nmos switch pipe N2, the drain electrode of nmos switch pipe N3 is connected to the drain electrode of nmos switch pipe N1, and its source electrode is connected to the drain electrode of nmos switch pipe N2, and the grid of nmos switch pipe N3 meets digital controlled signal D.

The equivalent circuit structure when switch that Fig. 5 gives differential switched capacitor structure of the present invention closes.Due to when digital controlled signal D is high level, nmos switch pipe N _iopen, PMOS switch pipe P _idisconnect, now effective capacitance of switching capacity and the same in Fig. 1, and its effective quality factor can be expressed as:

$Q=\frac{1}{{\mathrm{\ω}}_0\·(C_1//C_2)\·(((R_{\mathrm{ON}1}+R_{\mathrm{ON}2})//R_{\mathrm{ON}3})//(R_1+R_2))}---\left(4\right)$

Due to digital signal D by inverter and resistance by E _pand E _nnode pulls down to ground, reduces NMOS tube N ₁, N ₂conducting resistance, now E _pand E _nthe DC potential of two nodes is identical, makes the two empty short, reduces the equivalent resistance of N3 pipe conducting.Therefore, under opening, the equiva lent impedance of differential switched capacitor of the present invention is very little, increases the effective quality factor of switching capacity.

When switch controlling signal D is low level, nmos switch pipe N _iclose, switching capacity is in off-state, and now switching capacity equivalent electric circuit as shown in Figure 6, due to now E _pand E _nnode is inverted on device and resistance and comes VDD, the drain-substrate PN junction of now transistor N1, N2 is presented more reverse-biased, the depletion region of PN junction is increased, substantially reduces the impact of parasitic capacitance on switching capacity of drain electrode, Simultaneous Switching electric capacity bottom crown parasitic capacitance C over the ground _paralso very little, can ignore.Switching tube N3 is also because drain-source both end voltage is VDD, and pipe is not opened, and causes its equivalent resistance infinitely great.Therefore, the filtering characteristic showing low pass of modified model Switch capacitor structure under closed condition, can be completely isolated with resonant cavity, do not affect the frequency of oscillation of LC oscillator.

In sum, differential switched capacitor structure of the present invention, reduces parasitic capacitance during closedown, reduces dead resistance during unlatching, improves switch electric tuning scope, increases the quality factor of switched capacitor array.

Summary of the invention

The problem to be solved in the present invention is: for prior art Problems existing, the invention provides the differential switched capacitor structure that a kind of ghost effect is low, quality factor are high.

For realizing above-mentioned technical problem, the solution that the present invention proposes is: the first NMOS tube (N1), the second NMOS tube (N2), the 3rd NMOS tube (N3), the first inverter INV (001), the second inverter INV (002), the first resistance (R ₁), the second resistance (R ₂), the first metal capacitance (C ₁), the second metal capacitance (C ₂), wherein the grid of the first NMOS tube (N1) meets digital controlled signal D, and drain electrode meets the first metal capacitance (C ₁) one end, source electrode connect power supply ground, the input of the first inverter INV (001) meets digital controlled signal D, export meet the first resistance (R ₁) one end, the first resistance (R ₁) the drain electrode of another termination first NMOS tube (N1), the first metal capacitance (C ₁) another termination export P, the grid of the second NMOS tube (N2) meets digital controlled signal D, drain electrode meet the second metal capacitance (C ₂) one end, source electrode connect power supply ground, the input of the second inverter INV (002) meets digital controlled signal D, export meet the second resistance (R ₂) one end, the second resistance (R ₂) the drain electrode of another termination second NMOS tube (N2), the second metal capacitance (C ₂) another termination export N, the drain electrode of the 3rd NMOS tube (N3) connects the drain electrode of the first NMOS tube (N1), and source electrode connects the drain electrode of the second NMOS tube (N2), and grid meets digital controlled signal D.

Compared with prior art, the invention has the advantages that:

1, the ghost effect of differential switched capacitor structure is reduced.Compared with conventional differential switching capacity, Switch capacitor structure breaker in middle pipe of the present invention has good switching characteristic.

2, the quality factor of differential switched capacitor structure are increased.Compared with conventional differential Switch capacitor structure, differential switched capacitor structure dead resistance of the present invention is little, increases effective quality factor.

3, improve the tuning range of differential switched capacitor.Compared with conventional differential Switch capacitor structure, switched capacitor array ghost effect of the present invention is little, increases the difference of maximum effective capacitance and minimum effective capacitance, thus improves the tuning range of differential switched capacitor.

Accompanying drawing explanation

Fig. 1 is conventional differential Switch capacitor structure schematic diagram;

Fig. 2 is differential switched capacitor structural representation of the present invention;

Schematic equivalent circuit when Fig. 3 is the closedown of conventional differential switching capacity;

Schematic equivalent circuit when Fig. 4 is the unlatching of conventional differential switching capacity;

Schematic equivalent circuit when Fig. 5 is differential switched capacitor of the present invention closedown;

Schematic equivalent circuit when Fig. 6 is differential switched capacitor of the present invention unlatching;

Embodiment

Below with reference to the drawings and specific embodiments, the present invention is described in further details.

As shown in Figure 2, the present invention is the Kind of Switched Capacitor Array that a kind of ghost effect is low, quality factor are high, and it comprises the first NMOS tube (N1), the second NMOS tube (N2), the 3rd NMOS tube (N3), the first inverter INV (001), the second inverter INV (002), the first resistance (R ₁), the second resistance (R ₂), the first metal capacitance (C ₁), the second metal capacitance (C ₂), wherein the grid of the first NMOS tube (N1) meets digital controlled signal D, and drain electrode meets the first metal capacitance (C ₁) one end, source electrode connect power supply ground, the input of the first inverter INV (001) meets digital controlled signal D, export meet the first resistance (R ₁) one end, the first resistance (R ₁) the drain electrode of another termination first NMOS tube (N1), the first metal capacitance (C ₁) another termination export P, the grid of the second NMOS tube (N2) meets digital controlled signal D, drain electrode meet the second metal capacitance (C ₂) one end, source electrode connect power supply ground, the input of the second inverter INV (002) meets digital controlled signal D, export meet the second resistance (R ₂) one end, the second resistance (R ₂) the drain electrode of another termination second NMOS tube (N2), the second metal capacitance (C ₂) another termination export N, the drain electrode of the 3rd NMOS tube (N3) connects the drain electrode of the first NMOS tube (N1), and source electrode connects the drain electrode of the second NMOS tube (N2), and grid meets digital controlled signal D.

Operation principle: when switch controlling signal D is high level, switching tube N1, N2, N3 all open, node EP and EN current potential pulled down to ground, electric capacity C1 and C2 is made to access resonator, its conducting resistance is that RON is very little, reduces equivalent parasitic resistance, adds the quality factor of switching capacity.When switch controlling signal D is low level, switching tube N1, N2, N3 all disconnect, now node EP and EN current potential are pulled near VDD, the drain electrode of switching tube N1, N2 and substrate PN junction is made to present larger reverse-biased, drain edge parasitic capacitance CNipar is very little, and the drain-source voltage of Simultaneous Switching pipe N3, all close to VDD, makes the two empty disconnected, reduce effective capacitance of access resonator when switching capacity is closed, increase its tuning range.

Claims (1)

1. the differential switched capacitor structure that ghost effect is low, quality factor are high, is characterized in that: the first NMOS tube (N1), the second NMOS tube (N2), the 3rd NMOS tube (N3), the first inverter (001), the second inverter (002), the first resistance (R ₁), the second resistance (R ₂), the first metal capacitance (C ₁), the second metal capacitance (C ₂), wherein the grid of the first NMOS tube (N1) meets digital controlled signal D, and drain electrode meets the first metal capacitance (C ₁) one end, source ground, the first inverter INV(001) input meet digital controlled signal D, export meet the first resistance (R ₁) one end, the first resistance (R ₁) the drain electrode of another termination first NMOS tube (N1), the first metal capacitance (C ₁) another termination export P, the grid of the second NMOS tube (N2) meets digital controlled signal D, drain electrode meet the second metal capacitance (C ₂) one end, source ground, the second inverter INV(002) input meet digital controlled signal D, export meet the second resistance (R ₂) one end, the second resistance (R ₂) the drain electrode of another termination second NMOS tube (N2), the second metal capacitance (C ₂) another termination export N, the drain electrode of the 3rd NMOS tube (N3) connects the drain electrode of the first NMOS tube (N1), and source electrode connects the drain electrode of the second NMOS tube (N2), and grid meets digital controlled signal D.