CN103579109B - A kind of manufacture method of integrated optoelectronic circuit - Google Patents

Abstract

The invention relates to semiconductor technology, in particular to a method for manufacturing an optoelectronic integrated circuit. The main steps of the manufacturing method of the present invention are: processing the silicon wafer so that a part of the silicon wafer has an oxide layer; isolating the part of the silicon wafer with the oxide layer and the part without the oxide layer; The photoelectric device is manufactured in part, and the electronic device is manufactured on the oxide layer. The photoelectric device adopts a vertical structure, and the electronic device adopts an SOI process. The beneficial effect of the invention is that the photodiode and the integrated circuit module are integrated on the same chip, which effectively reduces packaging difficulty and cost, reduces parasitic effects, and improves reliability. The invention is particularly applicable to the manufacture of optoelectronic integrated circuits.

Description

A method of manufacturing an optoelectronic integrated circuit

technical field

The invention relates to semiconductor technology, in particular to a method for manufacturing an optoelectronic integrated circuit.

Background technique

An optoelectronic integrated circuit (OEIC) is an integrated circuit that integrates optoelectronic devices and electronic devices to achieve a specific function in an optical communication system or an optical information processing system.

In the past, ordinary optoelectronic integrated circuits were monolithically integrated using manufacturing methods compatible with traditional standard silicon-based processes. This integration method reduces the assembly steps in hybrid circuits, and its reliability and speed have also been significantly optimized. However, the electrical isolation between the optoelectronic device and the electronic device in this integration method is poor, and the photogenerated carriers generated by the optoelectronic device and the carriers in the electronic device will interfere with each other. In addition, the conventional process also needs to consider the photoelectric Compatibility issues between devices and electronic device processes. However, the optoelectronic integrated circuit proposed in this paper is manufactured by monolithic integrated local SOI process, and the chip is isolated into SOI-based modules and conventional silicon substrate areas by SIMOX or SDB processes. , while optoelectronic devices are fabricated in a conventional silicon substrate area using a vertical structure, and the two modules are interconnected through metal. The optoelectronic integrated circuit adopting the integrated method in this paper can effectively synthesize the respective advantages of optoelectronic devices and integrated circuit modules, reduce the problem of process compatibility, and realize the optimization of performance.

Contents of the invention

What the present invention aims to solve is to propose a method for single-chip integration of longitudinal photodetectors and integrated circuit modules in optoelectronic integrated circuits using SOI technology, aiming at the process integration problem of existing optoelectronic integrated circuits.

The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a method for manufacturing an optoelectronic integrated circuit, characterized in that it comprises the following steps:

a. Treat the silicon wafer so that a part of the silicon wafer has an oxide layer;

b. Isolate the part of the silicon wafer with the oxide layer and the part without the oxide layer;

c. Manufacture optoelectronic devices on the part of the silicon wafer without an oxide layer, and manufacture electronic devices on the oxide layer, the optoelectronic devices adopt a vertical structure, and the electronic devices adopt SOI technology.

Specifically, the specific method of step a is:

a1. Using a silicon wafer as a semiconductor substrate 301, a mask plate 303 is set on the epitaxial layer 302 of the semiconductor substrate 301, oxygen ion implantation is performed, and an oxide layer 304 is formed in the epitaxial layer 302 whose surface does not cover the mask plate 303;

a2. Form the oxide layer 304 into an insulating layer 305 by heat treatment;

a3. Removing the mask plate 303 .

Further, the specific method of step b is:

Using groove etching, a plurality of isolation layers 306 are etched on the insulating layer 305, and the isolation layers 306 isolate the epitaxial layer 302 on the insulating layer 305 into multiple parts.

Specifically, the specific method of step a is:

a1. Bonding a silicon wafer 401 with an oxide layer and a silicon wafer 402 without an oxide layer into an SOI structure;

a2. Remove a part of the SOI structure synthesized in step a1 by wet etching, specifically removing part of the silicon wafer 402 without the oxide layer and the silicon wafer 401 with the oxide layer connected to this part, and the removed oxide layer The portion of silicon wafer 401 includes the oxide layer of the portion;

a3. growing an epitaxial layer 403 on the structure obtained in step a2;

a4. Process the structure obtained in step a3 to a desired thickness by polishing.

Further, the specific method of step b is:

A plurality of isolation layers are provided on the oxide layer of the silicon wafer 401 with an oxide layer to isolate the silicon wafer on the oxide layer into multiple parts.

Still further, the arranging of the plurality of isolation layers is isolation by means of forming trench isolation or V-shaped groove isolation by etching.

The beneficial effect of the invention is that the photodiode and the integrated circuit module are integrated on the same chip, which effectively reduces packaging difficulty and cost, reduces parasitic effects, and improves reliability.

Description of drawings

Fig. 1 is the structural representation of embodiment 1;

Fig. 2 is the cross-sectional schematic diagram of embodiment 1;

3 is a schematic diagram of covering the mask plate 303 and performing oxygen ion implantation in the manufacturing process flow of embodiment 1;

4 is a schematic diagram of forming an oxide layer 304 in the manufacturing process flow of Embodiment 1;

5 is a schematic diagram of forming an insulating layer 305 in the manufacturing process flow of Embodiment 1;

6 is a schematic diagram after removing the mask plate 303 in the manufacturing process flow of embodiment 1;

FIG. 7 is a schematic diagram of etching an isolation layer 306 in the manufacturing process flow of Embodiment 1;

FIG. 8 is a schematic diagram of bonding a silicon wafer 401 with an oxide layer (N+ doped) and a silicon wafer 402 without an oxide layer into an SOI structure in the manufacturing process flow of Example 2;

Fig. 9 is a schematic diagram after removing a part of the SOI structure by wet etching in the manufacturing process flow of embodiment 2;

Fig. 10 is a schematic diagram after growing an epitaxial layer in the manufacturing process flow of embodiment 2;

Fig. 11 is the schematic diagram after adopting polishing process to process to required thickness in the manufacturing process flow of embodiment 2;

Fig. 12 is a schematic diagram after trench isolation in the manufacturing process flow of embodiment 2;

FIG. 13 is a schematic diagram after isolation by V-shaped grooves in the manufacturing process flow of Example 2. FIG.

detailed description

Below in conjunction with accompanying drawing and embodiment, describe technical solution of the present invention in detail:

The invention improves the manufacturing method on the basis of the general photoelectric integrated circuit technology, so that the photodiode and the integrated circuit module are integrated on the same chip, which effectively reduces the packaging difficulty and cost, reduces the parasitic effect, and improves the reliability . Compared with the mainstream technology, the present invention has the following advantages: the integrated photoelectric integrated circuit adopted can effectively reduce packaging difficulty and cost, reduce parasitic effects, and improve reliability; the adopted photodiode is made into a vertical structure, which effectively improves The response speed of the photodiode is improved; the integrated circuit module used is made of SOI technology, its parasitic capacitance is small, there is no latch-up effect, and the power consumption of the circuit can be reduced; the integration method of the photoelectric integrated circuit adopted can effectively integrate the photodiode And the performance of the integrated circuit module is optimized.

Example 1:

As shown in Figure 1, this example is an optoelectronic integrated circuit, including two parts: a photodiode and a subsequent CMOS amplifier circuit. The photodiode is a vertical PIN tube, which is made by SOI-compatible CMOS technology. The subsequent CMOS amplifier circuit is composed of several NMOS tubes, PMOS tubes, resistors and capacitors through specific connections, and is made by SOI technology.

Wherein, the photodiode 101 includes the anode 102 of the PIN tube for receiving light, the metal wire 103 is a metal wire connected to the anode, and the anode 102 is covered with an anti-reflection layer 104 for improving the quantum efficiency of the diode, The cathode is made on the back side, which is not shown in Figure 1; the CMOS amplifier circuit in Figure 1 only shows two basic device structures, wherein the NMOS transistor 105 includes a source 108, a gate 109 and a drain 110, and the PMOS transistor 106 includes a source 111, gate 112 and drain 113, all MOS transistors are separated by SiO2107, and are made on one layer of SiO2 insulating layer.

As shown in Figure 2, it is a cross-sectional explanatory diagram of some devices of this example, wherein A-A' section is a cross-sectional view of the photodiode in Figure 1 along A-A', N+ substrate 201 is used as the cathode of the PIN tube, and N -The epitaxial layer 202 is the I layer in the PIN tube, the P+ doped layer 204 is used as the anode of the PIN tube, and the metal electrodes 203 and 206 are respectively connected to the front and the back; BB' section is along the CMOS amplifier circuit B- in Fig. 1 The cross-sectional view of section B', the entire circuit is made on the SiO2 insulating layer 214, each device is isolated by a layer of SiO2 shallow grooves 207, the NMOS transistor includes a gate 209, a source electrode 208 and a drain electrode 207, and a PMOS transistor It includes a gate 212 , a source 211 and a drain 213 .

As shown in Figure 3-Figure 7, it is the manufacturing process of this example:

In this example, the SIMOX process is used for production, and the specific steps are as follows:

1. In the epitaxial layer 302 of the semiconductor substrate 301, use a mask plate 303 to cover the area where the photodiode needs to be fabricated, and perform oxygen ion implantation, as shown in FIG. 3 ;

2. After oxygen ion implantation, an initial oxide layer 304 is formed, as shown in FIG. 4 ;

3. After heat treatment, the required insulating layer 305 is formed, as shown in FIG. 5 ;

4. Remove the mask plate 303, as shown in FIG. 6;

5. Using trench etching, a layer of isolation layer 306 is formed to completely isolate the CMOS circuit part from the photodiode part, and at the same time isolate the devices in the CMOS circuit, as shown in FIG. 7 .

After the local SOI process is completed, conventional vertical photodiode fabrication and CMOS circuit fabrication can be performed. The specific fabrication of vertical photodiodes is mentioned in the Chinese patent with publication number CN101069288A.

Example 2:

As shown in Figure 8-Figure 13, in this example, the direct bonding (SDB) technology is used to fabricate the silicon wafer substrate, and the specific steps are as follows:

1. Bond a silicon wafer 401 with an oxide layer on one side (N+ doped) and a silicon wafer 402 without an oxide layer to form an SOI structure, as shown in Figure 8;

2. Remove the silicon layer and oxide layer in the area where the photodiode needs to be fabricated by wet etching, as shown in Figure 9;

3. growing an epitaxial layer 403, as shown in FIG. 10;

4. Polish the epitaxial layer to the desired thickness, as shown in Figure 11;

5. Use lateral isolation to isolate the photoelectric device area from the integrated circuit area. The methods that can be used include trench isolation (as shown in Figure 12) and V-groove isolation (as shown in Figure 13).

The above manufacturing process and materials should be determined according to the actual process environment.

Claims (2)

1. the manufacture method of an integrated optoelectronic circuit, it is characterised in that comprise the following steps:

A. silicon chip is processed, make a part for silicon chip possess oxide layer; Particularly as follows:

A1. the silicon chip (402) of the silicon chip (401) and non-oxidation layer that have oxide layer through and being bonded to soi structure;

A2. by a part for the soi structure of synthesis in wet etching removal step a1, being specially the silicon chip (402) removing part non-oxidation layer and the silicon chip (401) having oxide layer being connected with this part, the part of the removed silicon chip (401) having oxide layer includes the oxide layer of this part;

A3. the structure growing epitaxial layers (403) obtained in step a2;

A4. glossing is adopted to be worked into required thickness the structure obtained in step a3;

B., silicon chip have the part of oxide layer and the part of non-oxidation layer isolate; It is specially and multiple sealing coat is set in the oxide layer of the silicon chip (401) having oxide layer, the silicon chip in oxide layer is isolated into multiple part;

C. on silicon chip, the part of non-oxidation layer manufactures photoelectric device, manufactures electronic device in oxide layer; Described photoelectric device adopts vertical structure, and for longitudinal P IN photodiode, electronic device adopts SOI technology.

2. the manufacture method of a kind of integrated optoelectronic circuit according to claim 1, it is characterised in that described arrange multiple sealing coat be adopt by etch formed V-groove isolation mode isolate.