CN103617811B - Error correction circuit of SRAM type memory - Google Patents

Abstract

The invention provides an error correction circuit of SRAM memory, which includes: a coding module, a first transmission gate module, a second transmission gate module, an exclusive OR operation module, and an error correction circuit module. Utilize the encoding module to perform decoding operation, add control signals, and time-division multiplex the encoding and decoding operations. The circuit area is small, and at the same time, the reading and writing time of the memory is fast, and the error correction is accurate.

Description

A kind of error correction circuit of SRAM memory

technical field

The invention relates to memory data reliability, in particular to a circuit for ensuring reliability of memory read and write data.

Background technique

It is well known that high-energy particles in the space radiation environment can cause transient errors in multiple units inside the VLSI device. In SRAM memory, the performance of such transient errors in multiple units is multi-bit flipping. Since the particle distribution in the space environment has the characteristics of high energy and low flux, the multi-bit flip of the memory is mainly due to the single high-energy particle hitting the sensitive area of the device, and the charge generated is diffused, causing multiple units of the device to appear instantaneous. mistake.

With the continuous development of the integrated circuit manufacturing process, the process size of the SRAM structure device is continuously reduced, and the core voltage is continuously reduced, so the probability of this error is gradually increasing. Usually, data operations on SRAM memory devices are carried out by basic bytes, so what actually affects the application is a single basic multi-bit flip error (SMU).

At present, the following methods are mainly used to solve the SMU problem of the memory: one is to strengthen the process at the device level, the other is to physically disperse the logic adjacent bits, and the third is to use the BISC+SEC-DED method to implement multi-bit For error correction, the fourth is to detect and correct multiple bit errors through coding methods. The first three methods all require protection design at the device level, which brings complexity in device layout and wiring, increases device power consumption, and at the same time The production cost of the device is increased. Therefore, in the prior art, an encoding method is mostly used for system-level protection of the SRAM type memory.

The Hamming code is a commonly used error correction coding method, which has been widely used because it has fewer redundant check bits. In the traditional Hamming code, the information bit is not equal to the power of 2, so it needs to be shortened and part of the information bit deleted before it can be widely used in the memory. As shown in FIG. 1 , the existing shortened Hamming code encoding circuit is separated from the decoding circuit, which increases the overhead of the circuit area. On the other hand, SRAM cannot read and write at the same time, resulting in the independence of the encoding circuit and decoding circuit cannot improve the read and write speed.

Contents of the invention

The technical problem to be solved by the present invention is to design an error correction circuit for an SRAM type memory with small circuit area, fast read and write time, and accurate error correction

The present invention provides a kind of error correction circuit of SRAM memory, wherein, comprise:

The encoding module is used to generate a check bit by calculating the data signal;

The first transmission gate module generates a check bit accompanying the information bit according to the check bit and the write operation control signal;

The second transmission gate module and the XOR operation module generate a check vector according to the operation of the check bit and the read operation control signal;

The error correction circuit module looks up error bits according to the check vector, and performs error correction decoding.

Preferably, the inside of the coding module is a Hamming code coding rule.

Preferably, the input terminal of the coding module is connected to the data signal input terminal and its inversion signal input terminal, and the output terminal of the coding module outputs the check bit generated by the operation.

Preferably, the two input terminals of the first transmission gate are respectively connected to the output terminal of the encoding module and the write operation control signal terminal, and the output terminal of the first transmission gate outputs a check bit accompanying the information bit.

Preferably, the two input terminals of the second transmission gate module are respectively connected to the output terminal of the encoding module and the read operation control signal terminal, the output terminal of the second transmission gate, the data signal input terminal and its inversion The signal input end is connected to the input end of the XOR operation module, and the output end of the XOR operation module outputs a check vector.

Preferably, the input end of the error correction circuit module is connected to the output end of the XOR operation module, and the output end of the error correction circuit module is connected to the data signal input end and its inversion signal input end.

The coding module is used to perform the decoding operation, and the control signal is added to time-division multiplex the coding and decoding operations. If the memory is a data write operation, use the first transmission gate to generate the check bit output by the encoding module and the write operation control signal with the check bit accompanying the information bit for output, then the encoding module and the first transmission gate and the write operation signal at this time Equivalent to the function of the encoding circuit; if the memory is used for data reading operations, the second transmission gate module and the XOR operation module will calculate the check bit output by the encoding module and the read operation control signal to generate a check bit vector, and cooperate with the error correction circuit module Complete error correction decoding. At this time, the encoding module is reused, so that it is used in the encoding and decoding circuits at the same time, so that the circuit area is small, and the read and write time of the memory is fast, and the error correction is accurate.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment the present invention will be described in further detail:

Fig. 1 is a schematic circuit diagram of a kind of SRAM type memory in the prior art;

FIG. 2 is a schematic circuit diagram of Embodiment 1 of the error correction circuit of the SRAM type memory of the present invention.

detailed description

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the specific implementation modes of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the above-mentioned and other purposes, features and advantages of the present invention will be clearer. Like reference numerals designate like parts throughout the drawings. The drawings have not been drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

As shown in Figure 2, the present invention provides an error correction circuit for SRAM memory, which includes: an encoding module Encoder, a first transmission gate module TG, a second transmission gate module and an exclusive OR operation module TG&XOR, and an error correction circuit module Locating error.

In this embodiment, the input end of the encoding module Encoder is connected to the input end of the data signal O and the input end of the inversion signal OB, and the output end of the encoding module Encoder outputs the verification generated by the operation to the first transmission gate and the second transmission gate; The two input terminals of the first transmission gate TG are respectively connected to the output terminal of the encoding module Encoder and the write operation control signal Write terminal, and the output terminal of the first transmission gate TG outputs the check bit accompanying the information bit; the two terminals of the second transmission gate module TG The two input terminals are respectively connected to the output terminal of the encoding module Encoder and the read operation control signal Read terminal, and the output terminal of the second transmission gate TG, the data signal input terminal O and the input terminal of its inversion signal OB are respectively connected to the exclusive OR operation module XOR. The input terminal, the output terminal of the XOR operation module outputs the check vector to the error correction circuit module Locating error, and the output terminal of the error correction circuit module Locatingerror is connected to the input terminal of the data signal O and the input terminal of the inversion signal OB.

The working principle of this embodiment:

For linear block codes including Hamming codes, a k-dimensional message vector is multiplied by a k×n matrix to generate an n-dimensional codeword (word)

For example, the 32×38-dimensional generator matrix of (38, 32) shortened Hamming code is as follows:

G=[

11000010000000000000000000000000000000;

10100001000000000000000000000000000000;

01100000100000000000000000000000000000;

11100000010000000000000000000000000000;

10010000001000000000000000000000000000;

01010000000100000000000000000000000000;

11010000000010000000000000000000000000;

00110000000001000000000000000000000000;

10110000000000100000000000000000000000;

01110000000000010000000000000000000000;

11110000000000001000000000000000000000;

10001000000000000100000000000000000000;

01001000000000000010000000000000000000;

11001000000000000001000000000000000000;

00101000000000000000100000000000000000;

10101000000000000000010000000000000000;

01101000000000000000001000000000000000;

11101000000000000000000100000000000000;

00011000000000000000000010000000000000;

10011000000000000000000001000000000000;

01011000000000000000000000100000000000;

11011000000000000000000000010000000000;

00111000000000000000000000001000000000;

10111000000000000000000000000100000000;

01111000000000000000000000000010000000;

11111000000000000000000000000001000000;

10000100000000000000000000000000100000;

01000100000000000000000000000000010000;

11000100000000000000000000000000001000;

00100100000000000000000000000000000100;

10100100000000000000000000000000000010;

01100100000000000000000000000000000001

];

(38, 32) The parity check matrix of the shortened Hamming code is as follows:

H=[

10000011011010101101010101010101101010;

01000010110110011011001100110011011001;

00100001110001111000111100001111000111;

00010000001111111000000011111111000000;

00001000000000000111111111111111000000;

00000100000000000000000000000000111111

];

When decoding, the n-dimensional codeword is multiplied by the transposition of the parity check matrix (n×m dimension) to generate an m-dimensional syndrome vector, where m is the number of parity bits.

Syndrome calculation method: s=rH ^T ; where r is the read n-dimensional codeword. The forms of the generation matrix and check matrix satisfy:

G _k×n =[PI _k ],

H _m×n =[I _m P ^T ].

For any code word generated by the generator matrix G, the low bit is the check bit, and the high bit is the information bit. If v is a codeword generated during writing, then:

v=(s ₀ ,s ₁ ,...s _m-1 ,u ₀ ,u ₁ ,...,u _k-1 )

Through the form of codeword v, generator matrix G and check matrix H, it can be found that the new syndrome formed by multiplying the codeword by H is actually equal to the syndrome generated by writing the k-bit information vector into the memory, XOR read Syndromes regenerated from k-bit information bits. Therefore, the original encoding circuit can be used to perform the decoding operation. Add control signals to time multiplex the encoding and decoding operations.

Therefore, in the embodiment, the upper k-bit information bits of the input data signal O and its inverted signal OB are generated by the encoding module Encoder to generate a check bit. If it is a write operation to the memory, the write operation control signal write is at a high level, as an enable signal, controls the first transmission gate TG module, and stores the check digit output by the encoding module as the check digit accompanying the information bit. into the memory, a total of m bits; if it is a read operation, the read operation control signal read is high, and the check digit output by the encoding module Encoder is controlled by a high-effective read enable signal and an exclusive OR operation module, and Originally, the original input data signal O and the lower m bits of the inverted signal OB are XORed to generate a check bit vector for the error correction circuit module Locatingerror. The error correction circuit module finds a certain error bit according to the check vector, and flips a certain information bit in the upper k bits of the input data signal O and its inverted signal OB. Finally, the high k-bit information bits are output.

The coding module is used to perform the decoding operation, and the control signal is added to time-division multiplex the coding and decoding operations. If the memory is a data write operation, use the first transmission gate to generate the check bit output by the encoding module and the write operation control signal with the check bit accompanying the information bit for output, then the encoding module and the first transmission gate and the write operation signal at this time Equivalent to the function of the encoding circuit; if the memory is used for data reading operations, the second transmission gate module and the XOR operation module will calculate the check bit output by the encoding module and the read operation control signal to generate a check bit vector, and cooperate with the error correction circuit module Complete error correction decoding. At this time, the encoding module is reused, so that it is used in the encoding and decoding circuits at the same time, so that the circuit area is small, and the read and write time of the memory is fast, and the error correction is accurate.

In the foregoing description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the above descriptions are only preferred embodiments of the present invention, and the present invention can be implemented in many other ways different from those described here, so the present invention is not limited by the specific implementations disclosed above. At the same time, any person skilled in the art can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. All the content that does not deviate from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still belong to the protection scope of the technical solution of the present invention.

Claims (2)

1. a kind of error correction circuit of SRAM type memory, it is characterised in that including：

Coding module, for data-signal computing to be generated into check bit；

First transmission gate module, the check bit with information bit is generated according to the check bit and the computing of write operation control signal；

Second transmission gate module and xor operation module, according to the check bit and read operation control signal computing generation examine to Amount；

Error correction circuit module, searches error bit, and carry out error-correcting decoding according to inspection vector；

Wherein, if the memory is data write operation, the verification for being exported coding module using the first transmission gate module Position generates with write operation control signal and exported with the check bit of information bit；If memory is data read operation, the The check bit that two transmission gate modules and xor operation module export coding module is generated with read operation control signal computing and examined Vector, and coordinate error correction circuit module to complete error-correcting decoding；The coding module input connection data signal input and Its inversion signal input, the check bit of the output end output computing generation of the coding module；The first transmission gate module Two inputs connect the output end and write operation control signal end of the coding module, the first transmission gate mould respectively The check bit of the adjoint information bit of output end output of block；It is Hamming code coding rule inside the coding module；Described second passes Two inputs of defeated door module connect output end and the read operation control signal end of the coding module, described second respectively Output end, data signal input and its inversion signal input of transmission gate module connect the input of the xor operation module Vector is examined in end, the output end output of the xor operation module.

2. the error correction circuit of SRAM type memory according to claim 1, it is characterised in that the error correction circuit module Input connects the output end of the xor operation module, the output end connection data signal input of the error correction circuit module And its inversion signal input.