CN114548389A - Management method and corresponding processor of computing unit in heterogeneous computing - Google Patents

Abstract

The present disclosure provides a method for managing computing units in heterogeneous computing and a corresponding processor, wherein each computing unit is provided with a corresponding command management register and a command status register, and each bit of the command management register indicates the corresponding computing unit Whether each entry in the command cache is in an idle state, each bit of the command status register indicates the execution status of each command in the corresponding computing unit. The scheme realizes the management of multiple computing units based on the command management register and the command status register, improves the execution efficiency of computing commands by the heterogeneous computing processor, and has good scalability.

Description

Management method of computing unit in heterogeneous computing and corresponding processor

technical field

The present application relates to high-performance computing and heterogeneous computing, and in particular, to a method for managing computing units in heterogeneous computing and a corresponding processor.

Background technique

The statements in this section are only for providing background information related to the technical solutions of the present application to help understanding, and they do not necessarily constitute prior art to the technical solutions of the present application.

In recent years, deep neural network has become very popular, and its computing tasks have the characteristics of large amount of data, large amount of calculation, and many kinds of calculation. The computational tasks of deep neural networks are usually organized in the form of directed acyclic data flow graphs. The execution order of these computing tasks can be serial execution or parallel execution. According to the topological relationship of the graph, these computing tasks are often assigned to multiple command lists. Computational tasks that need to be executed in series are usually assigned to the same command list to allow the hardware to execute sequentially; while computational tasks that can be executed in parallel are usually assigned to multiple different command lists to allow the hardware to execute in parallel to improve performance. Computational efficiency. The existing serial instruction execution mode of the central processing unit (CPU) is very inefficient in executing parallel algorithms, so a heterogeneous computing architecture of "CPU + hardware accelerator" has emerged, in which the hardware accelerator (also known as a coprocessor) specializes in processing a large number of Computational tasks, while other non-computational tasks may be handled by the CPU (which may also be referred to as the main processor).

Among the various hardware accelerators for deep neural networks, heterogeneous computing processors have higher computing efficiency and higher computing efficiency than traditional graphics processing units (GPUs) due to their multiple dedicated hardware computing units for computing task acceleration. lower power consumption. However, due to the diverse types of computing units included in the heterogeneous processor and the different characteristics of executing commands by various computing units, the management of each computing unit faces many challenges.

It should be noted that the above content is only used to help understand the technical solutions of the present application, and is not used as a basis for evaluating the prior art of the present application.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a method for managing computing units in heterogeneous computing and a heterogeneous computing processor, which realizes the management of multiple computing units in a simple and efficient manner and improves the execution efficiency of computing commands.

The above purpose is achieved through the following technical solutions:

According to a first aspect of the embodiments of the present application, a method for managing computing units in heterogeneous computing is provided, wherein each computing unit is provided with a corresponding command management register and a command status register, and each bit of the command management register Indicate whether each entry in the command cache of the corresponding computing unit is in an idle state, and each bit of the command status register indicates the execution state of each command in the corresponding computing unit; the method includes:

According to the type of the command to be executed, determine the command management register corresponding to the computing unit suitable for executing the command of this type; select the command management register with the bits indicating the idle state from the determined command management registers, and indicate one of them. The serial number of the bit of the idle state in the command management register is used as the serial number of the command to be executed and the bit is set to indicate a non-idle state; the command to be executed and its serial number are sent to the command with the selected command. The computing unit corresponding to the management register, and in the command status register corresponding to the computing unit, the bit corresponding to the sequence number is set to indicate an incomplete state; and in response to receiving the command completion signal from the computing unit, in the In the command status register corresponding to the computing unit, the bit corresponding to the serial number of the completed command is set to indicate the completed state, and in the command management register corresponding to the computing unit, the bit corresponding to the serial number of the completed command is set. Set to indicate idle state.

In some embodiments, selecting a command management register with bits indicating an idle state may include: identifying a number of bits in the command management register having bits indicating an idle state by reading the value of the command management register; and selecting a command management register with a maximum number of bits The command management register for the bits indicating the idle state.

In some embodiments, selecting the command management register with the bits indicating the idle state may include selecting the command management register with the bits indicating the idle state in a polling manner.

In some embodiments, the method may further include setting the state of the computing unit to unavailable by setting a value of a corresponding command management register of the computing unit.

In some embodiments, the width of the command management register and the command status register depends on the length of the command buffer of the corresponding computing unit.

In some embodiments, the method may further include: in response to receiving the command completion signal from the computing unit, after a preset period of time has elapsed, in a command management register corresponding to the computing unit, the command management register corresponding to the completed command is updated. The bit corresponding to the serial number is set to indicate the idle state.

In some embodiments, the method may further include: recording the correspondence between the sequence number of the command to be executed and the hardware command queue to which the command to be executed belongs.

In some embodiments, the method may further include: in response to receiving a command completion signal from the computing unit, searching for a hardware command queue corresponding to the command according to the sequence number of the completed command, and feeding back a command indicating that the command is completed. Signal.

In some embodiments, the method may further include: continuously distributing multiple commands to be executed from the same hardware queue to each computing unit for processing.

In some embodiments, the method may further include: in response to receiving the command completion signal from the computing unit, determining whether the completed command still needs to wait for other commands; only when it is determined that the command does not need to wait for other commands, in the In the command management register corresponding to the computing unit, the bit corresponding to the sequence number of the completed command is set to indicate the idle state.

In some embodiments, the method may further include: for commands to be executed from a plurality of hardware command queues, distributing each command to be executed to the computing unit according to a preset priority.

According to a second aspect of the embodiments of the present application, a heterogeneous computing processor is provided, which includes a controller, a plurality of computing units of different types, a command management register and a command status register corresponding to each computing unit, wherein the Each bit of the command management register indicates whether each entry of the command cache of the corresponding computing unit is in an idle state; each bit of the command status register indicates the execution state of each command in the corresponding computing unit, and the controller is is configured to perform the method described in the first aspect above.

The technical solutions of the embodiments of the present application may include the following beneficial effects:

A computing unit management method based on command management register and command status register is proposed, which does not require complicated software programming, and avoids invalid waiting caused by reading external storage. In addition, the non-blocking execution mode of the command queue is realized in a simple way, and the execution efficiency of the computing command by the heterogeneous computing processor is improved. In addition, this register-based computing unit management mechanism also improves the robustness of heterogeneous computing processors and has good scalability.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not limiting of the present application.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application. Obviously, the drawings in the following description are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. In the attached image:

FIG. 1 is a schematic diagram of a structural module of a heterogeneous computing processor according to an embodiment of the present application.

FIG. 2 is a schematic structural module diagram of a front-end control engine in a heterogeneous computing processor according to an embodiment of the present application.

FIG. 3 is a schematic flowchart of a computing unit management method in heterogeneous computing provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings through specific embodiments. It should be understood that the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical solutions of the present application may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the present application.

The block diagrams shown in the figures are merely functional entities and do not necessarily necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices entity.

The flowcharts shown in the figures are only exemplary illustrations and do not necessarily include all contents and operations/steps, nor do they have to be performed in the order described. For example, some operations/steps can be decomposed, and some operations/steps can be combined or partially combined, so the actual execution order may be changed according to the actual situation.

In a heterogeneous computing architecture, the main processor can allocate computing tasks to be executed into multiple command lists, and instruct the corresponding coprocessors to execute these computing tasks. These command lists can be kept in memory for reading, parsing and execution by the coprocessor. In the embodiment of the present application, the command list prepared by the main processor is executed by the heterogeneous computing processor as a co-processor.

FIG. 1 is a schematic diagram of a structural module of a heterogeneous computing processor according to an embodiment of the present application.

In the heterogeneous computing processor, at least two different types of computing units are included; for example, a general-purpose image processing unit, a computing unit dedicated to processing matrix addition and multiplication, a computing unit dedicated to vector operations and derivation operations, etc. . Each computing unit has a command buffer that can receive multiple commands, so as to avoid wasting computing resources due to command transmission gaps. The command cache includes multiple entries, and each received command is stored in a corresponding entry. Since different computing units have different command receiving capabilities, the number of entries in the command buffers of each computing unit (which can be understood as the depth, length or size of the command buffer) is also different.

The heterogeneous computing processor also includes a host interface, a front end control engine, a command network, and a memory interface. The host interface is mainly used for command communication or data communication between the heterogeneous processor and the main processor. A memory interface is used for communication between the heterogeneous computing processor and memory. The front-end control engine is connected to each computing unit through a command network, and distributes a list of commands to be executed to each computing unit for execution. The command network can be implemented in the form of an on-chip data exchange network, which is not limited in this paper.

In heterogeneous computing processors, the management of different kinds of computing units faces many challenges. For example, the ability of different types of computing units to receive commands may be different, and the order of executing commands may also be different, which needs to be scheduled according to the characteristics of the executed commands of each computing unit; the command queue executed in parallel may call the same computing unit at the same time, Competitive relationship between command queues needs to be handled; when multiple computing units need to process computing tasks cooperatively, the waiting relationship between computing units needs to be handled. In the embodiments of the present application, which will be described in detail below, a computing unit management method for heterogeneous computing processors is provided, which can improve the execution efficiency of computing commands of heterogeneous processors, while reducing the management complexity of computing units, and Has good scalability.

FIG. 2 is a schematic structural module diagram of a front-end control engine in a heterogeneous computing processor according to an embodiment of the present application. The front-end control engine can be used to read and parse the command list, and distribute commands according to the parsing result.

As shown in FIG. 2 , the front-end control engine includes a hardware queue scheduling module, a calculation management module and a plurality of hardware command queues that can be executed in parallel. The hardware queue scheduling module can assign the list of commands to be executed to each hardware command queue. Since the number of command lists created by the main processor and stored in the memory according to the corresponding computing tasks may be greater than the number of hardware command queues in the heterogeneous computing processors, the hardware queue scheduling module needs to schedule the hardware command queues, for example, by A certain scheduling strategy sends the command list to the idle hardware command queue. After each hardware command queue parses the received command, it distributes the command to the computing unit via the computing management module. Each hardware command queue can also independently read the command list prepared by the software from the memory, then parse the command and distribute the command to the computing management module. The computing management module can send commands to different computing units for processing according to the type of the command and the command execution status of each computing unit.

In the embodiment of the present application, the computing management module monitors or detects the command execution status of each computing unit by setting two registers for each computing unit. One of the registers is used to record the command buffer status of the computing unit, so it can be called the command management register. The other register is used to record the command execution state of the computing unit, so it can be called a command state register.

In this embodiment, each bit (Bit, may also be referred to as a bit) in the command management register corresponding to each computing unit corresponds to an entry in the command cache of the computing unit, and is used to indicate whether the entry is free. For example, a value of 1 indicates that the entry is unallocated and can receive compute commands; a value of 0 means that the entry is occupied and cannot receive compute commands, and vice versa.

In the following, for each bit of the command management register, a value of 1 indicates idle, and a value of 0 indicates occupied as an example for description.

The number of bits in the command management register (ie the width of the register) depends on the depth of the command buffer of the computing unit. Since different computing units have different command receiving capabilities, the command buffer depths of each computing unit are different, and correspondingly, the widths of the command management registers corresponding to each computing unit may also be different. If the value of each bit of the command management register corresponding to a computing unit is all 1, it means that all entries in the command cache of the computing unit are free, and the command capability it can currently receive is the largest; if the value of each bit of the command management register is 1 The value is all 0, indicating that the computing unit cannot receive new commands. In this way, when the calculation management module sends a certain calculation command to the calculation unit, it can first determine the calculation unit that can be used to process the type of command based on the type of the calculation command; then query the command management register corresponding to the corresponding type of calculation unit, The computing unit that can currently receive commands is selected from which to send computing commands. If all computing units of this type cannot receive new commands, the computing management module can block the computing command, but subsequent computing commands that do not belong to this type can still continue to be sent, so that those computing that still have computing resources The unit can continue to run after receiving new computing commands, and the command network will not be blocked, which can improve the execution efficiency of heterogeneous computing processors.

Continuing to refer to FIG. 2 , the command status register corresponding to each computing unit may have the same width as the above-mentioned command management register. In the command status register, each bit corresponds to the execution status of a computing command of the computing unit, and is used to record the completion of the command. For example, when the value is 1, it means that the calculation command has been completed, and when the value is 0, it means that the calculation command is being executed or not started, and vice versa.

In the following, for each bit of the command status register, a value of 1 indicates that the command has been completed, and a value of 0 indicates that the command has not been completed or not started as an example for description. In one embodiment, the initial value of each bit in the command status register is all 0, and when a calculation command is completed, the corresponding bit is set to 1.

Through the cooperation of the above-mentioned command status register and command management register, non-blocking execution or out-of-order execution of the same hardware command queue can be achieved. That is to say, the hardware command queue does not need to block after sending a command in the queue order, and wait for the command to complete before sending the next command. In the embodiment of the present application, each hardware command queue can continuously distribute several commands to the computing unit according to the state of the command management register of the computing unit without immediately blocking, thereby reducing command waiting time and improving command execution efficiency. The execution of each command will be recorded in the command status register corresponding to the computing unit. When a hardware command queue needs to wait for a command to complete, it only needs to query the corresponding bits in the corresponding command status register to learn the relevant information, without additional storage or tracking. In addition, the order in which commands are completed may vary within a compute unit or between compute units. Since the command status register can track each command that has been issued, it can also allow out-of-order completion of the issued commands, which further improves the execution efficiency of the computing commands by the heterogeneous computing processor.

In this embodiment, a command management register and a command status register corresponding to each computing unit are set in the computing management module. These command management registers and command status registers are visible to all hardware command queues, that is, all computing units of heterogeneous processors share all hardware command queues, and the computing management module can directly allocate them according to the command management registers of each computing unit. . For example, when two hardware command queues are to compete for the same computing unit, the computing management module can ensure that each computing command of the computing unit can be guaranteed by setting the command management register and the command status register of the computing unit for each command distributed to the computing unit. are executed normally, and each command in the command cache of the computing unit is not changed or replaced by commands from other queues. It can be seen that the command status register and command management register here are somewhat similar to the "synchronization lock" in the form of hardware, which simply and conveniently solves the problem of competition between different hardware command queues for the same computing unit. However, if the problem of competition between different hardware command queues for the same computing unit is solved by software programming, each hardware command queue often needs to repeatedly query the memory to obtain the command execution status of the computing unit. Moreover, it is difficult to accurately predict the real-time execution of each command through software programming, which often causes unnecessary synchronization waits and wastes hardware computing resources. In addition, the way of software programming is often not conducive to the use of hardware efficiency, because the synchronization instructions used to perform synchronization between command queues have their own overhead. Most synchronization instructions are implemented by reading and writing semaphore signals in external memory. The memory needs to be read repeatedly, which also introduces a lot of memory access delay or waiting, which affects the execution efficiency of the calculation command.

In some embodiments, the state of the computing unit may also be set by setting the value of the corresponding command management register of the computing unit in response to commands or configuration information from upper-layer software or a host processor. This design not only reduces the management complexity of computing units, but also improves the robustness of heterogeneous computing processors. For example, if some computing units are unavailable due to chip yield problems, the initial value of the command management registers of these computing units will be set to all 0 bits, which means that no command can be assigned to the computing unit. Such a simple design can ensure that the heterogeneous computing processor chip can continue to work even when some computing units are unavailable. In addition, this way of setting registers also provides good scalability for heterogeneous computing processors. When a new type of computing unit needs to be added or the number of computing units needs to be changed, it is only necessary to set or adjust the command management register and the command status register corresponding to the computing management unit. This application does not limit the detection method of the chip yield, and an external hardware detection method or an external software detection method may be used, and the detection of the chip yield should not be construed as a limitation on this application.

The following describes the management process of the computing management module for multiple computing units in more detail with reference to the flowchart shown in FIG. 3 .

In step S1, the computing management module receives commands to be executed from the hardware command queue. Because heterogeneous computing processors usually contain multiple computing units of different types. Therefore, the calculation management module firstly checks the command management registers corresponding to the calculation units suitable for executing commands of this type according to the type of the received commands to be executed, to determine the idle state of the command buffers of these calculation units. As mentioned above, each bit of the command management register indicates whether each entry in the command buffer of the corresponding computing unit is in an idle state. Or take a value of 1 to indicate idle, and a value of 0 to indicate occupied as an example. By reading the value of the command management register, you can easily know which bits are 1 and which bits are 0, and can be counted accordingly. The number of free entries in the command cache of the computing unit, that is, how many commands the computing unit can receive.

Heterogeneous computing processors typically contain multiple hardware command queues. In some embodiments, the computing management module may also be configured to arbitrate requests from multiple hardware command queues to allocate computing units according to a certain algorithm, and select one of the hardware command queues to serve it preferentially according to the arbitration algorithm, Commands in the hardware command queue are dispatched to computing units. In one embodiment, such an arbitration algorithm may be a round-robin algorithm to ensure fairness of command execution for each hardware command queue. In yet another embodiment, such an arbitration algorithm may be a greedy algorithm, which is used to ensure that commands in a certain hardware command queue are executed first. In yet another embodiment, the computing management module may perform scheduling according to the preset weights of each hardware command queue, which not only ensures that scheduling has a certain priority, but also enables all queue commands to be sent to the computing unit, thereby avoiding a certain Queues don't starve by blocking forever.

As mentioned above, the computing management module can determine the idle state of the command buffer of the corresponding computing unit by reading the value of the command management register of the computing unit. In step S2, the calculation management module may select one command management register from a plurality of command management registers with bits indicating idle state, and use the calculation unit corresponding to the command management register as the target calculation unit of the executed command. The serial number of the command management register is the serial number of the target computing unit.

In one embodiment, the computing management module may select the command management register according to the number of free entries in the command cache of the computing unit (ie, the number of bits in the command management register indicating the idle state). For example, a computing unit with more idle entries may be preferentially selected, so as to ensure load balance among the computing units as much as possible.

In yet another embodiment, the calculation management module may also adopt a simple polling allocation method, which avoids the logic and cycle generated by comparing the number of bits indicating the idle state in each command management register.

For the selected command management register, the computing management module assigns one of the bits indicating the idle state to the command to be executed. For example, the serial number of the bit in the command management register is used as the serial number of the command to be executed (also referred to as an identification number of a command, or a command id), and the bit is set to indicate a non-idle state. As mentioned above, in the command management register corresponding to the computing unit, each bit indicates the status of an entry in the command cache of the computing unit, that is, each bit corresponds to the command cache entry of the computing unit one-to-one . Therefore, in this embodiment, the sequence number of the bit in the command management register is used as the sequence number for identifying the command to be executed, which helps to simplify the subsequent setting of the cache and execution state of the command. Since the serial number of this bit is the serial number of the entry that the command to be executed will occupy in the command cache of the target computing unit, it can be directly stored in the corresponding entry of the command cache according to the serial number of the received command to be executed. middle. In addition, setting this bit here to indicate a non-idle state can ensure that the entry will not be occupied by other commands before the command cache is released. If the current command has been executed, and the bit corresponding to the command has been set to indicate the idle state, the sequence number of the bit in the command management register can be assigned to the new command to be executed, that is, By querying or accessing the value of each bit in the command management register, you can know whether the serial number (or identifier) of the corresponding bit in the command management register is currently allowed to be assigned to the next command to be executed. The method is simple and efficient, and additional access query process can be saved.

In some embodiments, the computing management module may also record the correspondence between the sequence number assigned to the command to be executed and the hardware command queue to which the command to be executed belongs, so as to feed back the execution status of the command to the corresponding hardware queue subsequently.

Continuing to refer to FIG. 3, in step S3, the calculation management module sends the command to be executed and its serial number to the calculation unit corresponding to the selected command management register through the command network. The computing unit will save the received command and sequence number in the corresponding entry in its command cache. While sending the command, the calculation management module can directly set the bit corresponding to the sequence number in the command status register corresponding to the calculation unit to indicate an incomplete state based on the sequence number of the command to be executed, so as to prevent the previous operation from being delayed in time. Clearing the state causes the subsequent calculation management module to misjudge the command execution state. The computing unit reads a computing command from its command buffer and executes it. When the execution of the command is completed, the computing unit will return the command completion signal and the sequence number of the completed command to the computing management module through the command network.

In step S4, in response to receiving the command completion signal from the computing unit, the computing management module sets the bit corresponding to the sequence number of the completed command in the command status register corresponding to the computing unit to indicate the completed state, so as to Indicates that the calculation command has been completed.

In one embodiment, the computing management module may also feed back the command completion information to the corresponding hardware command queue. In such an embodiment, when assigning a sequence number to a command to be executed, the computing management module may record which hardware command queue the command sequence number belongs to. In this way, when the command completion signal is received, the relevant information can be returned to the corresponding hardware command queue.

In yet another embodiment, the computing management module may also not feed back the command completion information to the corresponding hardware command queue. When the execution status of a command needs to be queried, for example, the hardware command queue is blocked, or synchronization between commands is required, so that the execution status of a command needs to be queried, the computing management module can actively query the corresponding command status registers, which can save hardware register resources.

After the calculation management module receives the command completion signal from the calculation unit, it can also set the bit corresponding to the serial number of the completed command in the command management register corresponding to the calculation unit to indicate the idle state, thereby releasing the calculation The corresponding entry in the unit's command cache.

As an implementation manner, after receiving the command completion signal, the computing management module can immediately modify the corresponding bit of the command management register to indicate an idle state, so that the command cache entry space of the computing unit can be quickly released, so that subsequent The new command continues to execute.

Considering the possible synchronous operation between commands, after receiving the command completion signal, the computing management module can also modify and update the bits of the command management register in the following manner:

As another implementation manner, after receiving the command completion signal, the computing management module may not modify the corresponding bits of the command management register immediately, but choose to delay for a period of time and then modify it to indicate an idle state (that is, In response to receiving the command completion signal from the computing unit, after a preset period of time, the bit corresponding to the serial number of the completed command is set to indicate an idle state in the command management register corresponding to the computing unit). This is considering the possible synchronous operation between commands. When a command is completed, it needs to wait for other commands. At this time, the sequence number of the completed command needs to be kept in the command management register for a period of time, so that other commands can pass through Query the corresponding command status register to judge the completion of the command. However, if synchronization is not considered, the sequence number of the completed command is directly modified in the corresponding bit of the command management register to indicate the idle state, then the sequence number is likely to be assigned to the subsequent new command, and the corresponding bit in the command status register is corresponding. The bit is also reset, making it impossible to query the execution status of the command.

As a further implementation, the computing management module may, after receiving the command completion signal, determine whether the completed command still needs to wait for other commands; only when it is determined that the command does not need to wait for other commands, the command corresponding to the computing unit The bit corresponding to the sequence number of the completed command is set in the management register to indicate the idle state. Compared with the method of modifying the bit state after waiting for a fixed period of time, this embodiment can adapt to more synchronous operation scenarios and has better flexibility.

In the above-mentioned embodiments, although the hardware queue scheduling module and the calculation management module are introduced in the form of independent modules, it should be understood that the above-mentioned modules or the circuits implementing the above-mentioned modules can be used as control circuits, control logic or control circuits of heterogeneous computing processors. implemented as part of a processor, or the control circuitry, control logic or controller of a heterogeneous computing processor may be configured to perform the functions, steps or methods described above in connection with the hardware queue scheduling module and the computing management module. Based on the same inventive concept, an embodiment of the present application further provides a heterogeneous computing processor. The heterogeneous computing processor includes a controller, a plurality of computing units of different types, and a command management register and a command status register corresponding to each computing unit as described above. The controller is configured to implement the functions described above in conjunction with the hardware queue scheduling module and the computing management module, or to perform the management process of multiple computing units in heterogeneous computing described in conjunction with the above embodiments. For other details of the heterogeneous computing processor, please refer to the relevant description above, which will not be repeated here.

References in this specification to "various embodiments," "some embodiments," "one embodiment," or "an embodiment," etc., refer to specific features, structures, or properties described in connection with the embodiments, including in at least one embodiment. Thus, appearances of the phrases "in various embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout the specification are not necessarily referring to the same implementation example. Furthermore, the particular features, structures, or properties may be combined in any suitable manner in one or more embodiments. Thus, particular features, structures, or properties shown or described in connection with one embodiment may be combined, in whole or in part, with the features, structures, or properties of one or more other embodiments without limitation, provided that the combination is not non-limiting. Logical or not working.

The expressions "comprising" and "having" and terms of similar meaning in this specification are intended to cover non-exclusive inclusion, such as a process, method, system, product or device comprising a series of steps or units not limited to those listed steps or units, but optionally also steps or units not listed, or optionally other steps or units inherent to these processes, methods, products or devices. "A" or "an" also does not exclude the case of more than one. In addition, various elements in the drawings of the present application are for illustrative purposes only and are not drawn to scale.

Although the present application has been described by the above-mentioned embodiments, the present application is not limited to the embodiments described herein, and includes various changes and changes made without departing from the scope of the present application.

Claims (12)

1. a management method of computing unit in heterogeneous computing, wherein each computing unit is provided with its corresponding command management register and command status register, and each bit of the command management register indicates each entry in the command cache of the corresponding computing unit Whether it is in an idle state, each bit of the command status register indicates the execution state of each command in the corresponding computing unit; the method includes: According to the type of the command to be executed, determine the command management register corresponding to the computing unit suitable for executing the command of this type; From the determined command management registers, select a command management register with a bit indicating an idle state, use the sequence number of one of the bits indicating an idle state in the command management register as the sequence number of the command to be executed, and set the sequence number of the command to be executed. This bit is set to indicate a non-idle state; Send the command to be executed and its sequence number to a computing unit corresponding to the selected command management register, and set the bit corresponding to the sequence number in the command status register corresponding to the computing unit to indicate incomplete state; In response to receiving the command completion signal from the computing unit, in the command status register corresponding to the computing unit, the bit corresponding to the serial number of the completed command is set to indicate the completed state, and the command management corresponding to the computing unit The bit in the register corresponding to the sequence number of the completed command is set to indicate the idle state. 2. The method of claim 1, selecting a command management register having a bit indicating an idle state comprising: Identify the number of bits in the command management register that have bits indicating the idle state by reading the value of the command management register; The command management register with the largest number of bits indicating idle state is selected. 3. The method of claim 1, selecting a command management register having a bit indicating an idle state comprising: The command management register with the bits indicating the idle state is selected in a round-robin fashion. 4. The method of claim 1, further comprising setting the state of a computing unit to unavailable by setting a value of a corresponding command management register of the computing unit. 5. The method of claim 1, wherein the width of the command management register and the command status register depends on the length of the command buffer of their corresponding computing unit. 6. The method of claim 1, further comprising: The correspondence between the sequence number of the command to be executed and the hardware command queue to which the command to be executed belongs is recorded. 7. The method of claim 6, further comprising: In response to receiving the command completion signal from the computing unit, the hardware command queue corresponding to the command is searched according to the sequence number of the completed command, and a signal indicating that the command is completed is fed back to it. 8. The method of claim 6, further comprising: Continuously distribute multiple commands to be executed from the same hardware command queue to each computing unit for processing. 9. The method of any one of claims 1-8, further comprising: In response to receiving the command completion signal from the computing unit, determining whether the completed command still needs to wait for other commands; Only when it is determined that the command does not need to wait for other commands, the bit corresponding to the sequence number of the completed command is set to indicate an idle state in the command management register corresponding to the computing unit. 10. The method of any one of claims 1-8, further comprising: In response to receiving the command completion signal from the computing unit, after a preset period of time, the bit corresponding to the serial number of the completed command is set to indicate the idle state in the command management register corresponding to the computing unit. 11. The method according to any one of claims 1-8, further comprising, for commands to be executed from a plurality of hardware command queues, distributing each command to be executed to the computing unit according to a preset priority. 12. A heterogeneous computing processor, comprising a controller, a plurality of computing units of different types, a command management register and a command status register corresponding to each computing unit, wherein each bit of the command management register indicates corresponding Whether each entry of the command cache of the computing unit is in an idle state; each bit of the command status register indicates the execution state of each command in the corresponding computing unit, and the controller is configured to execute any one of claims 1-11. one of the methods described.

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