CN115207087A - A kind of TVS device and its making method - Google Patents

Abstract

The invention discloses a TVS device and a manufacturing method thereof. The TVS device includes: an N-type substrate; an N-type buried layer disposed on one side of the N-type substrate; an N-epitaxial layer disposed on a side of the N-type buried layer away from the N-type substrate; the The N-epitaxial layer is provided with a P well and at least one N-type deep well, the N-type deep well penetrates the N-epitaxial layer, and the P-well is far away from the surface of the N-type substrate and the N-epitaxy The surface of the layer away from the N-type substrate is flush, and the depth of the P-well is less than the thickness of the N-epitaxial layer; the N-type deep well and the P-well are both provided with N+ regions, and the The N+ region is flush with the surface of the N-type deep well and the P-well remote from the N-type substrate, and the depth of the N+ region is less than the depth of the P-well. The embodiment of the present invention realizes that the TVS diode and the PIN tube are fabricated in the same device, without occupying the wiring space of the circuit, and can reduce the capacitance of the TVS device and improve the clamping characteristic.

Description

A kind of TVS device and its making method

technical field

The present invention relates to the technical field of semiconductors, in particular to a TVS device and a manufacturing method thereof.

Background technique

According to Moore's Law, the number of transistors on an integrated circuit doubles approximately every eighteen months. The constant shrinking of transistor size allows ICs to have more complex functions under the same layout. As the CMOS process shrinks with the manufacturing precision, the gate dielectric layer (SiO2) needs to be thinner and thinner, which makes the antistatic ability of the IC weaker and weaker. In this case, if proper protection is not done, the IC will suffer will be susceptible to fatal damage. Therefore, protection devices represented by TVS (Transient Voltage Suppressor, transient voltage suppressor) are widely used in various I/O interfaces. Under normal conditions, the TVS diode is in an open-circuit state and will not interfere with the normal operation of the back-end IC. However, when static electricity or surge occurs in the peripheral circuit, the TVS diode will break down at a speed of picoseconds, instantly releasing the current. And clamp the voltage of the back-end IC within a safe voltage range.

In the actual application process, the capacitance characteristics and clamping characteristics of TVS diodes are two key indicators to investigate the device performance. Taking HDMI (High-Definition Multimedia Interface) as an example, the transmission rate of high-speed interfaces is getting faster and faster, even as high as 3GHz, which requires that the capacitance of TVS diodes must be less than 0.3pf, only this ultra-low Capacitance can protect the signal on each signal line of the interface from being lost. In addition, the clamping characteristics of the TVS diode will directly affect the voltage on the corresponding port of the back-end IC when subjected to external interference. If the clamping characteristics of the TVS diode are poor, the TVS diode will not be damaged after encountering external interference. The back-end IC is still broken.

The traditional low-capacitance TVS diode implementation method is to connect an ultra-low-capacitance TVS diode in parallel at each signal end. If the TVS diode has a capacitance as low as 0.3pF, it is often necessary to connect the TVS diode in series with an ultra-low-capacitance PIN. Therefore, the cost of this protection scheme is high, and it takes up a lot of circuit wiring space. The clamping characteristics of TVS diodes are mainly affected by the body resistance of TVS diodes. Traditional TVS diodes are mostly implemented by manufacturing a positive and negative electrode on the front and back of the wafer. Although this method is simple, the process is simple. However, it is greatly affected by the thickness of the wafer, and the clamping voltage is usually relatively high.

SUMMARY OF THE INVENTION

The invention provides a TVS device and a manufacturing method thereof, so as to realize the manufacture of the TVS diode and the PIN tube in the same device without occupying the wiring space of the circuit, and can reduce the capacitance of the TVS device and improve the clamping characteristic.

According to an aspect of the present invention, a TVS device is provided, comprising:

N-type substrate;

an N-type buried layer disposed on one side of the N-type substrate;

An N-epitaxial layer disposed on the side of the N-type buried layer away from the N-type substrate; the N-epitaxial layer is provided with a P well and at least one N-type deep well, and the N-type deep well penetrates through the N-type deep well. In the N- epitaxial layer, the surface of the P well away from the N-type substrate is flush with the surface of the N- epitaxial layer away from the N-type substrate, and the depth of the P well is smaller than the N- The thickness of the epitaxial layer;

Both the N-type deep well and the P-well are provided with an N+ region, the N+ region is flush with the surfaces of the N-type deep well and the P-well away from the N-type substrate, and the N+ The depth of the region is less than the depth of the P-well.

Optionally, the TVS device further includes:

an oxide layer and a metal layer, the oxide layer is arranged on the side of the N- epitaxial layer away from the N-type substrate; the oxide layer covers the N- epitaxial layer, the N-type deep well, the N-type deep well, the The P well and the N+ region, and the oxide layer is provided with a first through hole and a second through hole, and at least part of the N+ region in the N-type deep well is exposed at the first through hole, so The second through hole exposes at least part of the N+ region in the P well;

The metal layer is disposed on the side of the oxide layer away from the N-type substrate, the metal layer includes a first metal block and a second metal block, and the first metal block and the second metal block are mutually insulation;

The first metal block is in contact with the N+ region in the N-type deep well through the first through hole, and the second metal block is in contact with the N+ region in the P well through the second through hole.

Optionally, the N-epitaxial layer is provided with one P well and two N-type deep wells, and the two N-type deep wells are located on both sides of the P well.

Optionally, the N-epitaxial layer is provided with a first deep groove and a second deep groove;

The first deep trench is disposed between the P well and the N-type deep well, and the first deep trench is disposed around the P well, and the second deep trench surrounds the P well and the N-type deep well At least one N-type deep well setup;

Both the first deep trench and the second deep trench penetrate through the N-epitaxial layer, the N-type buried layer and part of the N-type substrate;

The first deep groove and the second deep groove are filled with silicon dioxide.

Optionally, the depths of the first deep groove and the second deep groove are greater than or equal to 15um.

Optionally, the thickness of the N-type substrate is 100-200um; the depth of the N+ region is 2-3um;

The thickness of the N-epitaxial layer is 5-10um, and the resistivity is 1000-3000 Ohm·cm;

The thickness of the oxide layer is 0.8-1.5um, and the thickness of the metal layer is 2-6um.

Optionally, the doping material of the N-type buried layer includes As, the doping material of the P well includes B, the doping material of the N-type deep well includes P, and the doping material of the N+ region includes P;

The material of the metal layer includes AlSicu.

According to another aspect of the present invention, a method for fabricating a TVS device is provided, comprising:

Provide N-type substrate;

Perform general injection of an N-type buried layer on one side of the N-type substrate to form an N-type buried layer;

forming an N-epitaxial layer on the side of the N-type buried layer away from the N-type substrate;

A P well and at least one N-type deep well are formed in the N-epitaxial layer, the N-type deep well penetrates the N-epitaxial layer, and the P-well is far from the surface of the N-type substrate and the N-type deep well. - the surface of the epitaxial layer away from the N-type substrate is flush, and the depth of the P-well is less than the thickness of the N- epitaxial layer;

An N+ region is provided in the N-type deep well and the P-well, the N+ region is flush with the surfaces of the N-type deep well and the P-well away from the N-type substrate, and the N+ region The depth is less than the depth of the P-well.

Optionally, after the N+ regions are arranged in the N-type deep well and the P well, the method further includes:

A first deep trench and a second deep trench are formed in the N-epitaxial layer; wherein the first deep trench is disposed between the P well and the N-type deep well, and the first deep trench surrounds The P well is arranged, and the second deep trench is arranged around the P well and the at least one N-type deep well; the first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate;

Silicon dioxide is filled in the first deep groove and the second deep groove.

Optionally, after the silicon dioxide is filled in the first deep groove and the second deep groove, the method further includes:

An oxide layer is formed on the side of the N- epitaxial layer away from the N-type substrate; the oxide layer covers the N- epitaxial layer, the N-type deep well, the P-well and the N+ region, And the oxide layer is provided with a first through hole and a second through hole, the first through hole exposes at least a part of the N+ region in the N-type deep well, and the second through hole exposes the entire area. at least a partial area of the N+ region in the P well;

A metal layer is formed on a side of the oxide layer away from the N-type substrate, the metal layer includes a first metal block and a second metal block, and the first metal block and the second metal block are insulated from each other, And the first metal block is in contact with the N+ region in the N-type deep well through the first through hole, and the second metal block is in contact with the N+ region in the P well through the second through hole ;

Thin the N-type substrate.

In the embodiment of the present invention, the structures of the TVS diode and the PIN switch tube are designed in a single die, so as to reduce the capacitance of the entire device, the PIN switch tube is set without occupying the wiring space of the circuit, and the combination of the buried layer and the deep well process is adopted. , so that the positive and negative electrodes of the device are arranged on the front of the chip, overcoming the disadvantage that the negative electrodes must be drawn from the back of the chip, reducing the bulk resistance of the device, thereby reducing the clamping voltage of the device and improving the clamping characteristics.

It should be understood that the content described in this section is not intended to identify key or critical features of the embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the present invention will become readily understood from the following description.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is a schematic diagram of a TVS device provided by an embodiment of the present invention;

2 is a flowchart of a method for manufacturing a TVS device provided by an embodiment of the present invention;

FIG. 3 is a flowchart of a method for fabricating a TVS device provided by an embodiment of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

An embodiment of the present invention provides a TVS device. FIG. 1 is a schematic diagram of a TVS device provided by an embodiment of the present invention. Referring to FIG. 1 , the TVS device includes:

N-type substrate 10;

an N-type buried layer 20 disposed on one side of the N-type substrate 10;

The N- epitaxial layer 30 is arranged on the side of the N-type buried layer 20 away from the N-type substrate 10; the N- epitaxial layer 30 is provided with a P well 40 and at least one N-type deep well 50, and the N-type deep well 50 penetrates through the N- The surface of the epitaxial layer 30 and the P well 40 away from the N-type substrate 10 is flush with the surface of the N-epitaxial layer 30 away from the N-type substrate 10, and the depth of the P well is less than the thickness of the N-epitaxial layer;

An N+ region 60 is provided in both the N-type deep well 50 and the P-well 40 , the N+ region 60 is flush with the surfaces of the N-type deep well 50 and the P-well 40 away from the N-type substrate 10 , and the depth of the N+ region 60 is smaller than that of the P-well 40 depth.

Specifically, the N-type substrate 10 can be a <100> crystal-oriented N-type substrate sheet, and the resistivity can be 10-30 Ohm·cm. The N-type buried layer can be injected on the N-type substrate 10. The implanted element is As, the concentration is about 1E15-5E15 per square centimeter, and the energy is 70KeV to form the N-type buried layer 20. The N-type buried layer is abbreviated as BN. The N- epitaxial layer 30 may be an ultra-high resistance epitaxial N-. The N-type deep well 50 can be formed by the diffusion of the N-type deep well in the designated area of the N-epitaxial layer 30, and the N-type deep well 50 should be expanded through the thickness of the N-epitaxial layer 30 and connected to the N-type buried layer 20, so that the N-type deep well 50 is to be expanded. The deep well 50 and the N-type buried layer 20 together form an N-type current channel, and the N-type deep well 50 is referred to as DN for short. The P well can be implanted in the designated area of the N-epitaxial layer 30. The implanted element is B, the concentration is about 1E15-5E15 per square centimeter, and the energy is 70KeV to form the P well 40. The P well 40 is referred to as PW for short. N+ ion implantation is performed in the P well 40 and the N-type deep well 50. The implanted element is P, the concentration is about 1E15-5E15 per square centimeter, and the energy is 70KeV to form an N+ region 60, and the N+ region 60 is referred to as SN. Furnace tube advancement is possible to advance SN and PW to specified depths.

The PN junction of the SN (N+ region 60 ) and the PW (P well 40 ) is the PN junction of the TVS diode, which determines the breakdown voltage of the TVS diode. PW (P well 40 ), N-epitaxial layer 30 and BN (N-type buried layer 20 ) form a structure of a PIN switch. The capacitance of this switch is about 0.3pF, which reduces the capacitance in the entire device structure. The N+ region 60 in the N-type deep well 50 is used for connecting the first electrode of the device, and the N+ region 60 in the P-well 40 is used for connecting the second electrode of the device.

In the embodiment of the present invention, the structures of the TVS diode and the PIN switch tube are designed in a single die, so as to reduce the capacitance of the entire device, the PIN switch tube is set without occupying the wiring space of the circuit, and the combination of the buried layer and the deep well process is adopted. , so that the positive and negative electrodes of the device are arranged on the front of the chip, overcoming the disadvantage that the negative electrodes must be drawn from the back of the chip, reducing the bulk resistance of the device, thereby reducing the clamping voltage of the device and improving the clamping characteristics. In addition, the use of N-epitaxial layers and the use of ultra-high-resistance epitaxy can further reduce the device capacitance.

Optionally, referring to Figure 1, the TVS device further includes:

The oxide layer 70 and the metal layer 80, the oxide layer 70 is arranged on the side of the N- epitaxial layer 30 away from the N-type substrate 10; the oxide layer 40 covers the N- epitaxial layer 30, the N-type deep well 50, the P well 40 and the N+ region 60, and the oxide layer 70 is provided with a first through hole 71 and a second through hole 72, at least part of the N+ region 60 in the N-type deep well 50 is exposed at the first through hole 71, and the second through hole 72 is exposed at least a portion of the N+ region 60 in the P-well 40;

The metal layer 80 is disposed on the side of the oxide layer 70 away from the N-type substrate 10, the metal layer 80 includes a first metal block 81 and a second metal block 82, and the first metal block 81 and the second metal block 82 are insulated from each other;

The first metal block 81 is in contact with the N+ region 60 in the N-type deep well 50 through the first through hole 71 , and the second metal block 82 is in contact with the N+ region 60 in the P well 40 through the second through hole 72 .

Specifically, the oxide layer 70 plays an insulating and protective role, and the first metal block 81 and the second metal block 82 are the first electrode and the second electrode of the device, respectively. In this embodiment, an N-type buried layer 20 and an N-type deep well are provided. 50 allows both the negative electrode and the positive electrode of the device to be drawn out from the same side of the device, thereby reducing the bulk resistance of the device, thereby reducing the clamping voltage of the device and improving the clamping characteristic.

In addition, SN is Shallow N+ region, SN (N+ region 60) generally has a shallow junction depth of 2-3um, and the doping concentration is relatively dense, SN (N+ region 60) in DN (N-type deep well 50) plays the role of The function of the DN (N-type deep well 50 ) and the first metal block 81 being drawn out in series reduces the contact resistance of the metal directly in contact with the DN (N-type deep well 50 ).

Optionally, referring to FIG. 1 , the N-epitaxial layer 30 is provided with one P well 40 and two N-type deep wells 50 , and the two N-type deep wells 50 are located on both sides of the P well 40 .

Specifically, the two N-type deep wells 50 can realize the protection of two high-speed ports by a single TVS device, thereby improving the integration of the device.

Optionally, the N-epitaxial layer 30 is provided with a first deep groove 91 and a second deep groove 92;

The first deep trench 91 is arranged between the P well 40 and the N-type deep well 50, and the first deep trench 91 is arranged around the P well 40, and the second deep trench 92 is arranged around the P well 40 and at least one N-type deep well 50; The first deep trenches 91 and the second deep trenches 92 penetrate through the N- epitaxial layer 30 , the N-type buried layer 20 and part of the N-type substrate 10 ; the first deep trenches 91 and the second deep trenches 92 are filled with silicon dioxide.

Specifically, the first deep trench 91 and the second deep trench 92 serve to isolate devices and reduce leakage. The first deep groove 91 and the second deep groove 92 may be formed by dry etching.

Optionally, the depths of the first deep groove 91 and the second deep groove 92 are greater than or equal to 15um.

In this way, the first deep trench 91 and the second deep trench 92 can penetrate through the N- epitaxial layer 30 , the N-type buried layer 20 and a part of the N-type substrate 10 , so as to better isolate the device.

Optionally, the thickness of the N-type substrate 10 is 100-200um; the thickness of the N-epitaxial layer 30 is 5-10um, the resistivity of the N-epitaxial layer 30 is 1000-3000Ohm·cm; the thickness of the oxide layer 70 is 0.8 -1.5um, the thickness of the metal layer 80 is 2-6um.

Specifically, the thickness of the N-type substrate 10 is 100-200um, which can adapt to most package thicknesses. Exemplarily, the thickness of the N-type substrate 10 may be 150um. The thickness of the N-epitaxial layer 30 is 5-10 um, and the resistivity is 1000-3000 Ohm·cm, so that the device has a smaller capacitance. The thickness of the oxide layer 70 is 0.8-1.5um. On the one hand, the difficulty of the process is reduced, and on the other hand, the insulating protection can be better played. An exemplary thickness of the oxide layer 70 can be 1.2um. The thickness of the metal layer 80 is 2-6um. On the one hand, it reduces the difficulty of the process, and on the other hand, it can better transmit signals and reduce the resistance. An exemplary thickness of the metal layer can be 4um.

Optionally, the doping material of the N-type buried layer 20 includes As, the doping material of the P well 40 includes B, the doping material of the N-type deep well 50 includes P, and the doping material of the N+ region 60 includes P; the metal layer 80 The materials include AlSicu.

An embodiment of the present invention also provides a method for fabricating a TVS device. FIG. 2 is a flowchart of a method for fabricating a TVS device provided by an embodiment of the present invention. Referring to FIG. 2 , the method includes:

S110, providing an N-type substrate.

S120, performing general injection of an N-type buried layer on one side of the N-type substrate to form an N-type buried layer.

S130, an N- epitaxial layer is formed on the side of the N-type buried layer that is far away from the N-type substrate.

S140, forming a P well and at least one N-type deep well in the N-epitaxial layer, the N-type deep well penetrates the N-epitaxial layer, the P well is far away from the surface of the N-type substrate, and the N-epitaxial layer is far away from the surface of the N-type substrate level, and the depth of the P-well is less than the thickness of the N-epitaxial layer.

Specifically, the N-type deep well is mainly formed by the diffusion of Pocl ₃ phosphorus, and Pocl ₃ is decomposed into PCl ₅ and P ₂ O ₅ at high temperature, and P ₂ O ₅ reacts with silicon at high temperature to generate silicon dioxide and P atoms, P Atoms form N-type deep wells during high-temperature propelling.

S150 , setting an N+ region in the N-type deep well and the P-well, the N+ region is flush with the surfaces of the N-type deep well and the P-well far from the N-type substrate, and the depth of the N+ region is less than that of the P-well.

In the embodiment of the present invention, the structures of the TVS diode and the PIN switch tube are designed in a single die, so as to reduce the capacitance of the entire device, the PIN switch tube is set without occupying the wiring space of the circuit, and the combination of the buried layer and the deep well process is adopted. , so that the positive and negative electrodes of the device are arranged on the front of the chip, overcoming the disadvantage that the negative electrodes must be drawn from the back of the chip, reducing the bulk resistance of the device, thereby reducing the clamping voltage of the device and improving the clamping characteristics. In addition, the use of N-epitaxial layers and the use of ultra-high-resistance epitaxy can further reduce the device capacitance.

Optionally, after the N+ regions are arranged in the N-type deep well and the P well, the method further includes:

A first deep trench and a second deep trench are formed in the N-epitaxial layer; wherein the first deep trench is arranged between the P well and the N-type deep well, the first deep trench is arranged around the P well, and the second deep trench is arranged around the P well A well and at least one N-type deep well are arranged; the first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate;

Silicon dioxide is filled in the first deep trench and the second deep trench.

3 is an optional flowchart of a method for fabricating a TVS device provided by an embodiment of the present invention, and the method includes:

S110, providing an N-type substrate.

S120, performing general injection of an N-type buried layer on one side of the N-type substrate to form an N-type buried layer.

S130, an N- epitaxial layer is formed on the side of the N-type buried layer that is far away from the N-type substrate.

S140, forming a P well and at least one N-type deep well in the N-epitaxial layer, the N-type deep well penetrates the N-epitaxial layer, the P well is far away from the surface of the N-type substrate, and the N-epitaxial layer is far away from the surface of the N-type substrate level, and the depth of the P-well is less than the thickness of the N-epitaxial layer.

S150 , setting an N+ region in the N-type deep well and the P-well, the N+ region is flush with the surfaces of the N-type deep well and the P-well far from the N-type substrate, and the depth of the N+ region is less than that of the P-well.

S160, forming a first deep trench and a second deep trench in the N-epitaxial layer; wherein the first deep trench is arranged between the P well and the N-type deep well, and the first deep trench is arranged around the P well, and the second deep trench is Surrounding the P well and the at least one N-type deep well; the first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate.

S170, filling silicon dioxide in the first deep groove and the second deep groove.

S180, forming an oxide layer on the side of the N- epitaxial layer away from the N-type substrate; the oxide layer covers the N- epitaxial layer, the N-type deep well, the P well and the N+ region, and the oxide layer is provided with a first through hole and a second Through holes, the first through holes expose at least part of the N+ region in the N-type deep well, and the second through hole exposes at least part of the N+ region in the P well.

S190, forming a metal layer on the side of the oxide layer away from the N-type substrate, where the metal layer includes a first metal block and a second metal block, the first metal block and the second metal block are insulated from each other, and the first metal block passes through the first metal block The through hole is in contact with the N+ region in the N-type deep well, and the second metal block is in contact with the N+ region in the P well through the second through hole.

S200, thinning the N-type substrate.

The manufacturing method of the TVS device in the embodiment of the present invention belongs to the same inventive concept as the TVS device, and has corresponding beneficial effects. For detailed technical details not in this embodiment, please refer to the TVS device provided in any embodiment of the present invention.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, the steps described in the present invention can be performed in parallel, sequentially or in different orders, and as long as the desired results of the technical solutions of the present invention can be achieved, no limitation is imposed herein.

The above-mentioned specific embodiments do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. a TVS device, is characterized in that, comprises: N-type substrate; an N-type buried layer disposed on one side of the N-type substrate; An N-epitaxial layer disposed on the side of the N-type buried layer away from the N-type substrate; the N-epitaxial layer is provided with a P well and at least one N-type deep well, and the N-type deep well penetrates through the N-type deep well. In the N- epitaxial layer, the surface of the P well away from the N-type substrate is flush with the surface of the N- epitaxial layer away from the N-type substrate, and the depth of the P well is smaller than the N- The thickness of the epitaxial layer; Both the N-type deep well and the P-well are provided with an N+ region, the N+ region is flush with the surfaces of the N-type deep well and the P-well away from the N-type substrate, and the N+ The depth of the region is less than the depth of the P-well. 2. TVS device according to claim 1, is characterized in that, also comprises: an oxide layer and a metal layer, the oxide layer is arranged on the side of the N- epitaxial layer away from the N-type substrate; the oxide layer covers the N- epitaxial layer, the N-type deep well, the N-type deep well, the The P well and the N+ region, and the oxide layer is provided with a first through hole and a second through hole, and at least part of the N+ region in the N-type deep well is exposed at the first through hole, so The second through hole exposes at least part of the N+ region in the P well; The metal layer is disposed on the side of the oxide layer away from the N-type substrate, the metal layer includes a first metal block and a second metal block, and the first metal block and the second metal block are mutually insulation; The first metal block is in contact with the N+ region in the N-type deep well through the first through hole, and the second metal block is in contact with the N+ region in the P well through the second through hole. 3. TVS device according to claim 1, is characterized in that: A P well and two N-type deep wells are arranged in the N-epitaxial layer, and the two N-type deep wells are located on both sides of the P well. 4. TVS device according to claim 1, is characterized in that: The N-epitaxial layer is provided with a first deep groove and a second deep groove; The first deep trench is disposed between the P well and the N-type deep well, and the first deep trench is disposed around the P well, and the second deep trench surrounds the P well and the N-type deep well At least one N-type deep well setup; Both the first deep trench and the second deep trench penetrate through the N-epitaxial layer, the N-type buried layer and part of the N-type substrate; The first deep groove and the second deep groove are filled with silicon dioxide. 5. TVS device according to claim 4, is characterized in that: The depths of the first deep groove and the second deep groove are greater than or equal to 15um. 6. TVS device according to claim 2, is characterized in that: The thickness of the N-type substrate is 100-200um; the depth of the N+ region is 2-3um; The thickness of the N-epitaxial layer is 5-10um, and the resistivity is 1000-3000 Ohm·cm; The thickness of the oxide layer is 0.8-1.5um, and the thickness of the metal layer is 2-6um. 7. TVS device according to claim 2, is characterized in that: The doping material of the N-type buried layer includes As, the doping material of the P well includes B, the doping material of the N-type deep well includes P, and the doping material of the N+ region includes P; The material of the metal layer includes AlSicu. 8. a preparation method of TVS device, is characterized in that, comprises: Provide N-type substrate; Perform general injection of an N-type buried layer on one side of the N-type substrate to form an N-type buried layer; forming an N-epitaxial layer on the side of the N-type buried layer away from the N-type substrate; A P well and at least one N-type deep well are formed in the N-epitaxial layer, the N-type deep well penetrates the N-epitaxial layer, and the P-well is far from the surface of the N-type substrate and the N-type deep well. - the surface of the epitaxial layer away from the N-type substrate is flush, and the depth of the P-well is less than the thickness of the N- epitaxial layer; An N+ region is provided in the N-type deep well and the P-well, the N+ region is flush with the surfaces of the N-type deep well and the P-well away from the N-type substrate, and the N+ region The depth is less than the depth of the P-well. 9. The method according to claim 8, characterized in that after setting N+ regions in the N-type deep well and the P well, the method further comprises: A first deep trench and a second deep trench are formed in the N-epitaxial layer; wherein the first deep trench is disposed between the P well and the N-type deep well, and the first deep trench surrounds The P well is arranged, and the second deep trench is arranged around the P well and the at least one N-type deep well; the first deep trench and the second deep trench both penetrate the N-epitaxial layer, the N-type buried layer and part of the N-type substrate; Silicon dioxide is filled in the first deep groove and the second deep groove. 10. The method according to claim 9, wherein after the silicon dioxide is filled in the first deep groove and the second deep groove, the method further comprises: An oxide layer is formed on the side of the N- epitaxial layer away from the N-type substrate; the oxide layer covers the N- epitaxial layer, the N-type deep well, the P-well and the N+ region, And the oxide layer is provided with a first through hole and a second through hole, the first through hole exposes at least a part of the N+ region in the N-type deep well, and the second through hole exposes the entire area. at least a partial area of the N+ region in the P well; A metal layer is formed on a side of the oxide layer away from the N-type substrate, the metal layer includes a first metal block and a second metal block, and the first metal block and the second metal block are insulated from each other, And the first metal block is in contact with the N+ region in the N-type deep well through the first through hole, and the second metal block is in contact with the N+ region in the P well through the second through hole ; Thin the N-type substrate.

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