CN115276661B - An ultra-high-resolution analog-to-digital converter - Google Patents
An ultra-high-resolution analog-to-digital converter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
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Abstract
本申请提供一种超高分辨率的模数转换器，包括二阶Delta‑Sigma调制解调单元和数字滤波单元；二阶Delta‑Sigma调制解调单元包括信号整理电路、第一级积分器电路、第二级积分器电路、模数转换单元、第一数模转换单元、第二数模转换单元和处理单元；采用多位数模转换单元和模数转换单元实现多比特量化和多比特反馈，有效降低量化噪声和电路噪声，提高信噪比；二阶Delta‑Sigma调制解调单元输出的数字信号经数字滤波单元进行抽取滤波后，输出高分辨率的数字信号，能够实现高分辨率、大动态范围的数据采集。
The present application provides an ultra-high-resolution analog-to-digital converter, comprising a second-order Delta-Sigma modulation and demodulation unit and a digital filtering unit; the second-order Delta-Sigma modulation and demodulation unit comprises a signal sorting circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit; a multi-bit digital-to-analog conversion unit and an analog-to-digital conversion unit are used to realize multi-bit quantization and multi-bit feedback, effectively reduce quantization noise and circuit noise, and improve the signal-to-noise ratio; a digital signal output by the second-order Delta-Sigma modulation and demodulation unit is extracted and filtered by a digital filtering unit, and a high-resolution digital signal is output, which can realize high-resolution and large dynamic range data acquisition.
Description
Technical Field
One or more embodiments of the present disclosure relate to the field of high resolution instruments and meters, and more particularly, to an ultra-high resolution analog-to-digital converter.
Background
With the development of electronic technology, the resolution and dynamic response range of the analog-to-digital converter are improved, and the effective bit of the analog-to-digital converter produced by some companies at present reaches 23.5 bits at most, and the dynamic range is smaller than 144dB. However, in some high-precision instrument measurement fields, a larger dynamic range is often required, for example, a seismic data collector for collecting seismic observation data, and the dynamic range of an output signal of a seismic observation instrument to be measured is more than 150dB, so that the existing analog-to-digital converter still has difficulty in meeting the requirement.
Disclosure of Invention
In view of this, it is an object of one or more embodiments of the present disclosure to provide an ultra-high resolution analog-to-digital converter capable of obtaining an ultra-high resolution, large dynamic range output signal.
In view of the above, one or more embodiments of the present disclosure provide an ultra-high resolution analog-to-digital converter including a second order Delta Sigma modem unit and a digital filtering unit;
The second-order Delta-Sigma modulation and demodulation unit comprises a signal arrangement circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit;
The differential analog signal is input into the signal arrangement circuit, the differential output end of the signal arrangement circuit is connected with the differential reverse input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected with the differential reverse input end of the second-stage integrator circuit, the differential output end of the second-stage integrator circuit is connected with the differential input end of the analog-to-digital conversion unit, the output end of the analog-to-digital conversion unit is connected with the signal input end of the processing unit, one path of signal output end of the processing unit is connected with the input end of the first digital-to-analog conversion unit through an inverter, the differential output end of the first digital-to-analog conversion unit is connected with the differential reverse input end of the first-stage integrator, the other path of signal output end of the processing unit is connected with the input end of the second digital-to-analog conversion unit, the digital signal output end of the processing unit is connected with the input end of the digital filtering unit, and the digital signal is subjected to digital filtering and then output.
Optionally, the processing unit performs primary filtering processing on the received digital signal, and transmits the digital signal after the primary filtering processing to the digital filtering unit.
Optionally, the signal conditioning circuit includes two operational amplifiers, the differential analog signal is connected with the forward input ends of the two operational amplifiers through resistors R1, the reverse input ends of the two operational amplifiers are grounded through resistors 4R, the reverse input ends of the two operational amplifiers are connected with the output ends of the operational amplifiers through resistors 2R, and the two output ends of the two operational amplifiers form a differential output end and are connected with the differential input end of the first-stage integrator circuit.
Optionally, a TVS protection circuit is disposed at the differential input end of the signal conditioning circuit.
Optionally, the first-stage integrator circuit includes two operational amplifiers U3 and U4, differential output ends of the signal sorting circuit are connected to inverting input ends of the two operational amplifiers U3 and U4 through resistors 3R, forward input ends of the two operational amplifiers U3 and U4 are grounded through resistors R2, differential signal output ends of the first digital-to-analog converter are connected to inverting input ends of the two operational amplifiers U3 and U4 through resistors 2R, and output ends of the two operational amplifiers U3 and U4 are connected to inverting input ends of the two operational amplifiers U3 and U4 through capacitors, respectively;
The second-stage integrator circuit comprises two operational amplifiers U5 and U6, the output ends of the two operational amplifiers U3 and U4 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through resistors 2R, the positive input ends of the two operational amplifiers U5 and U6 are respectively grounded through resistors R3, the differential signal output ends of the second digital-analog converter are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through resistors 2R, the output ends of the two operational amplifiers U5 and U6 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through capacitors, and the output ends of the two operational amplifiers U5 and U6 form differential output ends which are connected with the input ends of the analog-digital conversion unit.
Optionally, the analog-to-digital conversion unit adopts 16-bit ADC chips, the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are respectively formed by connecting two 16-bit DAC chips in parallel, and the four 16-bit DAC chips have the same model.
Optionally, output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are calibrated by using preset calibration parameters, and the calibrated signals are respectively input into the first-stage integrator circuit and the second-stage integrator circuit.
Optionally, the method for determining the calibration parameter includes dividing an output voltage range of the DAC chip into a plurality of voltage intervals according to a predetermined voltage interval, for each voltage interval, inputting different digital signals, measuring corresponding output analog voltage signals, and performing fitting processing according to a relationship between the input digital signals and the output analog voltage signals to obtain a calibration coefficient and a calibration offset corresponding to the voltage interval;
The relationship between the input digital signal D and the output analog voltage signal Vout is:
Vout=k×D×VR/2N+b (1)
Wherein VR is the reference voltage input to the DAC chip, N is the number of bits of the DAC chip, k is the calibration coefficient, and b is the calibration offset.
Optionally, the digital filter unit is configured with a multi-stage filter, and the multi-stage filter is used for outputting the digital signal with the variable sampling rate.
Optionally, the multi-stage filter includes a first-stage filter and a second-stage filter, the first-stage filter is a first-stage linear phase filter, the second-stage filter includes a second-stage linear phase filter and a second-stage minimum phase filter, and the digital signal output by the processing unit is filtered by the first-stage linear phase filter, and then is filtered by the second-stage linear phase filter and the second-stage minimum phase filter, so as to obtain a linear phase digital signal and a minimum phase digital signal.
From the above, it can be seen that, in the ultra-high resolution analog-to-digital converter provided in one or more embodiments of the present disclosure, the second-order Delta-Sigma modulation and demodulation unit is built by the second-stage integrator circuit, the multi-bit digital-to-analog conversion unit and the analog-to-digital conversion unit, the multi-bit quantization and multi-bit feedback are implemented by the multi-bit digital-to-analog conversion unit and the analog-to-digital conversion unit, the quantization noise and the circuit noise are effectively reduced, the signal-to-noise ratio is improved, the feedback loop adopts the multi-bit DAC chip with the parallel structure, the noise effect caused by nonlinearity can be reduced, and the digital signal output by the second-order Delta-Sigma modulation and demodulation unit can output the ultra-high resolution and large dynamic range digital signal after being extracted and filtered by the digital filtering unit.
Drawings
For a clearer description of one or more embodiments of the present description or of the solutions of the prior art, the drawings that are necessary for the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only one or more embodiments of the present description, from which other drawings can be obtained, without inventive effort, for a person skilled in the art.
FIG. 1 is a block diagram of an analog-to-digital converter in accordance with one or more embodiments of the present disclosure;
FIG. 2 is a block diagram of a second order Delta-Sigma modem unit in accordance with one or more embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a signal conditioning circuit according to one or more embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a two-stage integrator circuit in accordance with one or more embodiments of the present disclosure;
fig. 5 is a schematic diagram of a digital filtering unit according to one or more embodiments of the present disclosure.
Detailed Description
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
It is noted that unless otherwise defined, technical or scientific terms used in one or more embodiments of the present disclosure should be taken in a general sense as understood by one of ordinary skill in the art to which the present disclosure pertains. The use of the terms "first," "second," and the like in one or more embodiments of the present description does not denote any order, quantity, or importance, but rather the terms "first," "second," and the like are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
As shown in fig. 1 and 2, one or more embodiments of the present disclosure provide an ultra-high resolution analog-to-digital converter, including a second order Delta Sigma modem unit and a digital filtering unit;
The second-order Delta-Sigma modulation and demodulation unit comprises a signal arrangement circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit;
The differential analog signal input signal arrangement circuit, the differential output end of the signal arrangement circuit is connected with the differential reverse input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected with the differential reverse input end of the second-stage integrator circuit, the differential output end of the second-stage integrator circuit is connected with the differential input end of the analog-to-digital conversion unit, the output end of the analog-to-digital conversion unit is connected with the signal input end of the processing unit, one path of signal output end of the processing unit is connected with the input end of the first digital-to-analog conversion unit through the inverter, the differential output end of the first digital-to-analog conversion unit is connected with the differential reverse input end of the first-stage integrator, the other path of signal output end of the processing unit is connected with the input end of the second digital-to-analog conversion unit, the digital signal output end of the processing unit is connected with the input end of the digital filtering unit, and the digital filtering unit carries out filtering processing on the input digital signal and then outputs the converted digital signal.
The differential analog signals are input into the signal arrangement circuit through a differential input end, the signal arrangement circuit amplifies the input differential analog signals, the amplified differential analog signals and the differential analog signals output by the first digital-to-analog conversion unit are input into the first-stage integrator circuit, the first-stage integrator circuit integrates the input signals, the output differential analog signals and the differential analog signals output by the second digital-to-analog conversion unit are input into the second-stage integrator circuit, the second-stage integrator circuit integrates the input signals, the output differential analog signals are input into the analog-to-digital conversion unit, and the analog-to-digital conversion unit converts the input differential analog signals into digital signals and then inputs the digital signals into the processing unit.
The processing unit receives digital signals of the analog-to-digital conversion unit, on one hand, the received digital signals are directly output through one path of signal output end, the path of digital signals are input into the first digital-to-analog conversion unit after being inverted by the inverter, the inverted digital signals are converted into analog signals by the first digital-to-analog conversion unit, the analog signals are input into the first-stage integrator circuit, on the other hand, the received digital signals are directly output through the other path of signal output end, the path of digital signals are input into the second digital-to-analog conversion unit, the second digital-to-analog conversion unit converts the path of digital signals into analog signals, the analog signals are input into the second-stage integrator circuit, on the other hand, the processing unit performs primary filtering processing on the received digital signals, the primary filtered digital signals are transmitted to the digital filtering unit, the digital filtering unit performs further filtering extraction processing on the input digital signals, and finally the required digital signals are output.
The ultra-high resolution analog-to-digital converter provided by the embodiment is characterized in that the second-order Delta-Sigma modulation and demodulation unit is composed of a secondary integrator circuit, a multi-bit digital-to-analog conversion unit and an analog-to-digital conversion unit, and the secondary integrator circuit is constructed based on a low-noise operational amplifier, and multi-bit quantization and multi-bit feedback are realized by adopting the multi-bit digital-to-analog conversion unit and the analog-to-digital conversion unit, so that quantization noise and circuit noise are effectively reduced, and the signal-to-noise ratio is improved. The digital signal output by the second-order Delta-Sigma modem unit is subjected to extraction and filtration by the digital filtering unit, and then a high-resolution digital signal is output, so that data acquisition with ultrahigh resolution and large dynamic range can be realized.
As shown in fig. 3, the signal conditioning circuit is in the form of a fully symmetrical circuit. The signal arrangement circuit comprises two operational amplifiers U1 and U2, differential analog signals are respectively connected with forward input ends of the two operational amplifiers U1 and U2 through resistors R1 (the resistance values are 1 Kohm), reverse input ends of the two operational amplifiers U1 and U2 are respectively grounded through resistors 4R, reverse input ends of the two operational amplifiers U1 and U2 are respectively connected with output ends of the operational amplifiers U1 and U2 through resistors 2R, and differential output ends are formed by two output ends of the two operational amplifiers U1 and U2 and are connected with differential input ends of a first-stage integrator circuit. Each resistor in the circuit forms a matching resistor, so that the circuit stability can be ensured, and the input differential analog signal is amplified by a specific amplification factor.
IN some modes, the output signal of the earthquake observation instrument is a differential analog signal, the amplitude range of the differential analog signal is-20V-20V, the differential analog signal is input into a differential signal input end IN+ and IN-of the signal arrangement circuit, the differential analog signal is amplified by 1.5 times by a matching resistor, and the amplitude range of the differential signal output by a differential output end vin+ and Vin-of the signal arrangement circuit is-30V-30V. Optionally, the differential input terminal of the signal conditioning circuit may further be provided with a TVS protection circuit for suppressing transient interference that may occur.
As shown in fig. 4, the first-stage integrator circuit and the second-stage integrator circuit are cascaded to form a second-stage integrator circuit, which is in the form of a completely symmetrical circuit. Specifically, the first-stage integrator circuit comprises two operational amplifiers U3 and U4, differential output ends vin+ and Vin-of the signal arrangement circuit are respectively connected with reverse input ends of the two operational amplifiers U3 and U4 through resistors 3R, forward input ends of the two operational amplifiers U3 and U4 are respectively grounded through resistors R2 (the resistance value is 1 Kohm), and output ends of the two operational amplifiers U3 and U4 are respectively connected with the reverse input ends of the operational amplifiers U3 and U4 through capacitors;
The second-stage integrator circuit comprises two operational amplifiers U5 and U6, the output ends of the two operational amplifiers U3 and U4 of the first-stage integrator circuit are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 of the second-stage integrator circuit through resistors 2R, the forward input ends of the two operational amplifiers U5 and U6 are respectively grounded through resistors R3 (the resistance value is 1 Kohm), and the output ends of the two operational amplifiers U5 and U6 are respectively connected with the reverse input ends of the operational amplifiers U5 and U6 through capacitors.
The output ends of the two operational amplifiers U5 and U6 form a differential output end ADC_ P, ADC _N which is connected with the input end of the analog-to-digital conversion unit, and the analog-to-digital conversion unit converts an input analog signal into a digital signal and transmits the digital signal to the processing unit.
In some modes, the analog-to-digital conversion unit uses 16-bit ADC chips, the selected ADC chips should meet the requirements that the dynamic range is larger than 90dB, INL (Integral Nonlinearity ) is smaller than 0.5LSB, the power consumption is about 10mW, the bandwidth should be adapted to the bandwidth of the analog-to-digital converter, and the reference source of the ADC chips should be filtered so as to ensure low voltage noise and stable and reliable amplitude. Optionally, the ADC chip meeting the above requirements may be, for example, an AD7688, an AD1273, an AD7693, or the like, and the AD7693 is exemplified as a 16-bit successive comparison type analog-digital converter, the dynamic range is 96.5dB, thd (Total Harmonic Distortion ) can reach-120 dB at 1KHz, the power consumption is about 4mW at a sampling rate of 100KHz, and the maximum conversion rate is 500K. Alternatively, the sampling rate of the ADC chip is set to 64KHz.
In some modes, the first digital-to-analog conversion unit and the second digital-to-analog conversion unit use four 16-bit DAC chips with the same model, wherein the two 16-bit DAC chips are connected in parallel to form the first digital-to-analog conversion unit, and the other two 16-bit DAC chips are connected in parallel to form the second digital-to-analog conversion unit. The digital-to-analog conversion units with parallel structures are adopted in the feedback loop, so that random noise generated by the DAC can be counteracted, the problems of noise and harmonic distortion caused by the nonlinearity of the DAC are reduced, and the performance of the modem is ensured. Alternatively, the 16-bit DAC chip may select a chip with a larger output range, for example, the AD5781 chip has an output range of-10V-10V.
In some embodiments, output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are calibrated by using preset calibration parameters, the calibrated signals are respectively input into the first-stage integrator circuit and the second-stage integrator circuit, and noise and distortion influence caused by DAC nonlinearity can be reduced by the calibrated signals.
The method for determining the calibration parameter is that the digital signal input into the DAC chip is D, the output analog voltage signal of the DAC chip is Vout, the reference voltage input into the DAC chip is VR, the number of bits of the DAC chip is N, and the relationship between the input digital signal and the output analog voltage signal is:
Vout=k×D×VR/2N+b (1)
where k is the calibration coefficient and b is the calibration offset.
The output voltage range of the DAC chip is divided into a plurality of voltage intervals according to preset voltage intervals, for each voltage interval, different digital signals are input, corresponding output analog voltage signals are measured, fitting processing of the input signals and the output signals is carried out according to a formula (1), and the calibration coefficient and the calibration offset of the voltage interval are obtained. According to the method, the calibration coefficient and the calibration offset of each voltage interval are obtained, the first digital-to-analog conversion unit and the second digital-to-analog conversion unit determine the corresponding voltage interval and the calibration coefficient and the calibration offset according to the input digital signals, and according to the calibration coefficient, the calibration offset and the input digital signals, the analog voltage signals output after calibration are obtained according to the formula (1).
For example, the output voltage range of the DAC chip is-10V-10V, the output voltage range is divided into a plurality of voltage intervals according to the voltage interval of 100mV, different digital signals are input to the DAC chip for each voltage interval, the voltage measuring instrument is used for measuring the actual output voltage value corresponding to every 10mV, and the calibration coefficient and the calibration offset corresponding to the voltage interval are obtained through fitting based on the different digital signals and the measured actual output voltage value. Alternatively, the fitting method may be a linear fitting or a polynomial fitting, and the specific manner is not limited.
The processing unit receives the digital signal output by the analog-to-digital conversion unit through the SPI interface, on one hand, the received digital signal is output to the inverter through the SPI interface, the inverter inverts the digital signal and then inputs the digital signal into the first digital-to-analog conversion unit, and the output end DAC1_ N, DAC1_P of the first digital-to-analog conversion unit is connected with the inverting input ends of the operational amplifiers U3 and U4 through the resistor 2R. In the second aspect, the received digital signal is output to the second digital-to-analog conversion unit through the SPI interface, and the output end DAC2_ P, DAC2_n of the second digital-to-analog conversion unit is connected to the inverting input ends of the operational amplifiers U5, U6 through the resistor R2. In a third aspect, a received digital signal is subjected to primary filtering, and the primary filtered signal is input to the digital filter via an SPI interface.
In some embodiments, the processing unit performs half-band filtering on the received digital signal to implement primary filtering of the digital signal. As half of the half-band filtering coefficients are 0, the operation amount of the processing unit can be greatly reduced, and the data processing rate is improved. Optionally, the analog-to-digital conversion unit outputs a 64KHz digital signal, and the processing unit extracts a 2KHz signal from the 64KHz digital signal to implement primary filtering. The sampling rate of the analog-to-digital conversion unit can also be increased according to the specific application requirement, for example, the analog-to-digital conversion unit outputs a digital signal of 512KHz, and the processing unit extracts a digital signal of 16KHz from the digital signal of 512 KHz.
Referring to fig. 4, the inputs and outputs of the operational amplifiers U3 and U4 of the first-stage integrator circuit are in the form of fully symmetrical differential circuits, the non-inverting input ends of the operational amplifiers U3 and U4 are grounded through resistors with the same resistance, the differential signal output ends vin+ and vin+ of the signal arrangement circuit are connected with the inverting input ends of the operational amplifiers U3 and U4 through resistors 3R, the differential signal output ends DAC1_ N, DAC1_p of the first digital-to-analog converter are connected with the inverting input ends of the operational amplifiers U3 and U4 through resistors 2R, the resistance relation of the matching resistors is 3:2, and the amplitude of the input differential analog signals is adjusted to the input range of the operational amplifiers.
The input and output of the operational amplifiers U5 and U6 of the second-stage integrator circuit are in a completely symmetrical differential circuit mode, the normal phase input ends of the operational amplifiers U5 and U6 are grounded through resistors with the same resistance value, the differential signal output ends of the first-stage integrator circuit are connected with the reverse phase input ends of the operational amplifiers U5 and U6 through resistors 2R, the differential signal output end DAC 2-P, DAC-N of the second-stage integrator circuit is connected with the reverse phase input ends of the operational amplifiers U5 and U6 through resistors 2R, and after the second-stage integrator circuit adjusts input signals, the output differential analog signal range is a signal amplitude range 0V-5V which is suitable for being processed by an analog-digital conversion unit.
In some embodiments, to implement the filtering calculation, the digital filtering unit may be implemented by a processor with a 32-bit floating point operation. The digital filter unit may configure the multi-stage filters and filter coefficients of the respective filters so as to output the digital signal of the variable sampling rate using the multi-stage filters. In some modes, the multi-stage filter comprises a first-stage filter and a second-stage filter, the first-stage filter is a first-stage linear phase filter, the second-stage filter comprises a second-stage linear phase filter and a second-stage minimum phase filter, and after the digital signals output by the processing unit are subjected to filtering processing through the first-stage linear phase filter, the digital signals are respectively subjected to filtering processing through the second-stage linear phase filter and the second-stage minimum phase filter, so that linear phase digital signals and minimum phase digital signals are obtained.
In some embodiments, as shown in FIG. 5, the digital filtering unit includes a primary filter FIR-L0 and two secondary filters FIR-L1, FIR-M. Taking 2000-point sampling data output by the processing unit as an example, the 2000-point sampling data is filtered by a first-stage filter FIR-L0, the decimation ratio is 5, 400-point sampling data is obtained, the first-stage filter FIR-L0 is a linear phase filter, the output bandwidth of the first-stage filter FIR-L0 is far higher than that of an analog-to-digital converter, and therefore a filter with fewer filter coefficients can be adopted to reduce the calculated amount, such as 60dB of stop band attenuation and 1% of pass band flatness. The 400-point sampling data output by the first-stage filter FIR-L0 is filtered by the second-stage filter FIR-L1, the second-stage filter FIR-L1 is a linear phase filter, the extraction ratio is 2, 200-point sampling data are obtained, the second-stage filter FIR-L1 is filtered again, 100-point sampling data are obtained, the 400-point sampling data output by the first-stage filter FIR-L0 are filtered by the second-stage filter FIR-M, the second-stage filter FIR-M is a minimum phase filter, the extraction ratio is 2, 200-point sampling data are obtained, and the second-stage filter FIR-M is filtered again, so that 100-point sampling data are obtained. Thus, through the filtering processing of the digital filtering unit, two types of data, namely 100-point minimum phase data and 100-point linear phase data, can be obtained and output as observation data, and a user can select the required type of observation data according to the needs.
With reference to fig. 1, the clock signal end of the analog-to-digital converter is used for inputting a clock signal, and the clock signal can adopt a non-return-to-zero clock signal, so that the influence of clock jitter on the converter can be eliminated. The reset signal end of the analog-to-digital converter is used for inputting a reset synchronous signal, so that synchronous reset of a plurality of analog-to-digital converters can be realized. The reference voltage range input by the reference voltage end of the analog-to-digital converter is plus or minus 10V, and the gain of the converter can be controlled to be about 1:1.
The ultra-high resolution analog-to-digital converter provided by the embodiment of the application is characterized in that a second-order Delta-Sigma modulation-demodulation unit is built by electronic elements such as a secondary integrator circuit, a multi-bit analog-to-digital converter, a digital-to-analog converter and the like, quantization noise and circuit noise are effectively reduced through multi-bit quantization and multi-bit feedback, and the signal-to-noise ratio is improved. The digital-to-analog conversion units with parallel structures are used in the feedback loop, and output signals of the digital-to-analog conversion units are calibrated to reduce white noise and harmonic distortion caused by nonlinearity. The circuit structures such as the signal arrangement circuit and the two-stage integrator circuit adopt the circuit structures of differential input and output and complete symmetry, the circuit is ensured to stably reach the expected performance, the common mode rejection ratio is improved by matching symmetrical resistors and capacitors in the differential circuit, the anti-interference capability is enhanced, and the matching coefficient of the matched symmetrical resistors can reach 0.03%.
In the earthquake observation scene, the sampling rate required by earthquake observation is lower and is usually less than 500Hz, the analog-to-digital converter can adopt lower oversampling rate, such as 64KHz, and the clock frequency can be greatly reduced, so that the circuit structure is simplified, the circuit difficulty is reduced, the radiation influence of a high-speed clock on the circuit is reduced, and the noise is reduced. According to the circuit structure provided by the application, the analog-to-digital converter meeting the seismic observation requirement can output the ultra-high resolution digital signal, and the seismic data acquisition with the dynamic range exceeding 160dB is realized.
It will be appreciated by persons skilled in the art that the foregoing discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure, including the claims, is limited to these examples, that technical features in the above embodiments or in different embodiments may be combined, that steps may be implemented in any order, and that many other variations of the different aspects of one or more embodiments of the present description as described above exist, which are not provided in detail for clarity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure one or more embodiments of the present description. Furthermore, the apparatus may be shown in block diagram form in order to avoid obscuring the one or more embodiments of the present description, and also in view of the fact that specifics with respect to implementation of such block diagram apparatus are highly dependent upon the platform within which the one or more embodiments of the present description are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that one or more embodiments of the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Any omissions, modifications, equivalents, improvements, and the like, which are within the spirit and principles of the one or more embodiments of the disclosure, are therefore intended to be included within the scope of the disclosure.
Claims (8)
1. The ultra-high resolution analog-to-digital converter is characterized by comprising a second-order Delta-Sigma modulation-demodulation unit and a digital filtering unit;
The second-order Delta-Sigma modulation and demodulation unit comprises a signal arrangement circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit;
The differential analog signal is input into the signal sorting circuit, the differential output end of the signal sorting circuit is connected with the differential reverse input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected with the differential reverse input end of the second-stage integrator circuit, the differential output end of the second-stage integrator circuit is connected with the differential input end of the analog-to-digital conversion unit, the output end of the analog-to-digital conversion unit is connected with the signal input end of the processing unit, one path of signal output end of the processing unit is connected with the input end of the first digital-to-analog conversion unit through an inverter, the differential output end of the first digital-to-analog conversion unit is connected with the differential reverse input end of the first-stage integrator, the other path of signal output end of the processing unit is connected with the input end of the second digital-to-analog conversion unit, the digital signal output end of the processing unit is connected with the input end of the digital filtering unit, and the digital signal is subjected to digital filtering and then output;
calibrating output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit by using preset calibration parameters, and respectively inputting the calibrated signals into the first-stage integrator circuit and the second-stage integrator circuit;
Dividing the output voltage range of the DAC chip into a plurality of voltage intervals according to preset voltage intervals, inputting different digital signals for each voltage interval, measuring corresponding output analog voltage signals, and carrying out fitting processing according to the relation between the input digital signals and the output analog voltage signals to obtain a calibration coefficient and a calibration offset corresponding to the voltage interval;
The relationship between the input digital signal D and the output analog voltage signal Vout is:
Vout = k×D×VR/2N + b (1)
Wherein VR is the reference voltage input to the DAC chip, N is the number of bits of the DAC chip, k is the calibration coefficient, and b is the calibration offset.
2. The analog-to-digital converter according to claim 1, wherein the processing unit performs primary filtering processing on the received digital signal, and transmits the primary-filtered digital signal to the digital filtering unit.
3. The analog-to-digital converter according to claim 1, wherein the signal conditioning circuit comprises two operational amplifiers, the differential analog signals are respectively connected with the positive input ends of the two operational amplifiers through resistors R1, the negative input ends of the two operational amplifiers are respectively grounded through resistors 4R, the negative input ends of the two operational amplifiers are respectively connected with the output ends of the operational amplifiers through resistors 2R, and the two output ends of the two operational amplifiers form differential output ends which are connected with the differential input ends of the first-stage integrator circuit.
4. An analog-to-digital converter according to claim 3, wherein the differential inputs of the signal conditioning circuit are provided with TVS protection circuits.
5. The analog-to-digital converter according to claim 1, wherein the first-stage integrator circuit comprises two operational amplifiers U3 and U4, differential output ends of the signal sorting circuit are respectively connected with inverting input ends of the two operational amplifiers U3 and U4 through resistors 3R, forward input ends of the two operational amplifiers U3 and U4 are respectively grounded through resistors R2, differential signal output ends of the first digital-to-analog converter are respectively connected with inverting input ends of the two operational amplifiers U3 and U4 through resistors 2R, and output ends of the two operational amplifiers U3 and U4 are respectively connected with inverting input ends of the two operational amplifiers U3 and U4 through capacitors;
The second-stage integrator circuit comprises two operational amplifiers U5 and U6, the output ends of the two operational amplifiers U3 and U4 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through resistors 2R, the positive input ends of the two operational amplifiers U5 and U6 are respectively grounded through resistors R3, the differential signal output ends of the second digital-analog converter are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through resistors 2R, the output ends of the two operational amplifiers U5 and U6 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through capacitors, and the output ends of the two operational amplifiers U5 and U6 form differential output ends which are connected with the input ends of the analog-digital conversion unit.
6. The analog-to-digital converter of claim 1, wherein the analog-to-digital conversion unit adopts 16-bit ADC chips, the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are respectively formed by connecting two 16-bit DAC chips in parallel, and four 16-bit DAC chips have the same model.
7. The analog-to-digital converter of claim 1, wherein the digital filtering unit is configured with a multi-stage filter for outputting a digital signal of a variable sampling rate.
8. The analog-to-digital converter of claim 7, wherein the multi-stage filter comprises a primary filter and a secondary filter, the primary filter is a primary linear phase filter, the secondary filter comprises a secondary linear phase filter and a secondary minimum phase filter, and the digital signal output by the processing unit is filtered by the primary linear phase filter and then is filtered by the secondary linear phase filter and the secondary minimum phase filter respectively to obtain the linear phase digital signal and the minimum phase digital signal.
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