CN218041371U - Ultrahigh resolution analog-to-digital converter - Google Patents
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Abstract
The application provides an analog-to-digital converter with ultrahigh resolution, which comprises a second-order Delta-Sigma modulation-demodulation unit and a digital filtering unit; the second-order Delta-Sigma modulation-demodulation unit comprises a signal arrangement circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit; multi-bit quantization and multi-bit feedback are realized by adopting a multi-bit digital-to-analog conversion unit and an analog-to-digital conversion unit, so that quantization noise and circuit noise are effectively reduced, and the signal-to-noise ratio is improved; the digital signal output by the second-order Delta-Sigma modulation and demodulation unit is extracted and filtered by the digital filtering unit, and then the digital signal with high resolution is output, so that the data acquisition with high resolution and large dynamic range can be realized.
Description
Technical Field
One or more embodiments of the present disclosure relate to the field of high resolution instrumentation, and more particularly, to an ultra-high resolution analog-to-digital converter.
Background
With the development of electronic technology, the resolution and dynamic response range of analog-to-digital converters are improved, and currently, some companies produce analog-to-digital converters with the effective bit reaching 23.5 bits at most and the dynamic range being less than 144dB. However, in some high-precision instrument measurement fields, a larger dynamic range is often required, for example, a seismic data collector for collecting seismic observation data needs to measure the dynamic range of an output signal of the seismic observation instrument above 150dB, and the existing analog-to-digital converter has difficulty in meeting such a requirement.
SUMMERY OF THE UTILITY MODEL
In view of the above, an object of one or more embodiments of the present disclosure is to provide an ultra-high resolution analog-to-digital converter, which can obtain an ultra-high resolution output signal with a large dynamic range.
In view of the above, one or more embodiments of the present disclosure provide an ultra-high resolution analog-to-digital converter, including a second-order Delta Sigma modem unit and a digital filter unit;
the second-order Delta-Sigma modulation-demodulation unit comprises a signal arrangement circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit;
the differential analog signal is input into the signal sorting circuit, the differential output end of the signal sorting circuit is connected with the differential reverse input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected with the differential reverse input end of the second-stage integrator circuit, the differential output end of the second-stage integrator circuit is connected with the differential input end of the analog-to-digital conversion unit, the output end of the analog-to-digital conversion unit is connected with the signal input end of the processing unit, one path of signal output end of the processing unit is connected with the input end of the first digital-to-analog conversion unit through a phase inverter, the differential output end of the first digital-to-analog conversion unit is connected with the differential reverse input end of the first-stage integrator, the other path of signal output end of the processing unit is connected with the input end of the second digital-to-analog conversion unit, the differential output end of the processing unit is connected with the differential reverse input end of the second-stage integrator, and the digital filtering unit processes the input digital signal and outputs the converted digital signal.
Optionally, the processing unit performs primary filtering processing on the received digital signal, and transmits the digital signal after the primary filtering processing to the digital filtering unit.
Optionally, the signal sorting circuit includes two operational amplifiers, the differential analog signal is connected to the forward input ends of the two operational amplifiers through resistors R1, the reverse input ends of the two operational amplifiers are grounded through resistors 4R, the reverse input ends of the two operational amplifiers are connected to the output ends of the operational amplifiers through resistors 2R, and the two output ends of the two operational amplifiers form a differential output end connected to the differential input end of the first-stage integrator circuit.
Optionally, a TVS protection circuit is disposed at a differential input terminal of the signal sorting circuit.
Optionally, the first-stage integrator circuit includes two operational amplifiers U3 and U4, a differential output end of the signal conditioning circuit is connected to the inverting input ends of the two operational amplifiers U3 and U4 through a resistor 3R, forward input ends of the two operational amplifiers U3 and U4 are grounded through a resistor R2, a differential signal output end of the first digital-to-analog conversion unit is connected to the inverting input ends of the two operational amplifiers U3 and U4 through a resistor 2R, and output ends of the two operational amplifiers U3 and U4 are connected to the inverting input ends of the two operational amplifiers U3 and U4 through capacitors;
the second-stage integrator circuit comprises two operational amplifiers U5 and U6, the output ends of the two operational amplifiers U3 and U4 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through a resistor 2R, the positive input ends of the two operational amplifiers U5 and U6 are respectively grounded through a resistor R3, the differential signal output end of the second digital-to-analog conversion unit is respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through a resistor 2R, and the output ends of the two operational amplifiers U5 and U6 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through capacitors; the output ends of the two operational amplifiers U5 and U6 form a differential output end which is connected with the input end of the analog-to-digital conversion unit.
Optionally, the analog-to-digital conversion unit adopts a 16-bit ADC chip; the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are respectively formed by connecting two 16-bit DAC chips in parallel, and the models of the four 16-bit DAC chips are the same.
Optionally, output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are calibrated by using preset calibration parameters, and the calibrated signals are respectively input to the first-stage integrator circuit and the second-stage integrator circuit.
Optionally, the method for determining the calibration parameter includes dividing an output voltage range of the DAC chip into a plurality of voltage intervals according to a predetermined voltage interval, and for each voltage interval, performing fitting processing by inputting different digital signals and measuring an analog voltage signal that is output correspondingly, and according to a relationship between the input digital signal and the analog voltage signal that is output, obtaining a calibration coefficient and a calibration offset corresponding to the voltage interval;
the relationship between the input digital signal D and the output analog voltage signal Vout is:
Vout＝k×D×VR/2N+b (1)
VR is a reference voltage input to the DAC chip, N is the digit of the DAC chip, k is a calibration coefficient, and b is a calibration offset.
Optionally, the digital filtering unit is configured with a multistage filter, and the multistage filter is configured to output a digital signal with a variable sampling rate.
Optionally, the multistage filter includes a first-stage filter and a second-stage filter, the first-stage filter is a first-stage linear phase filter, the second-stage filter includes a second-stage linear phase filter and a second-stage minimum phase filter, and the digital signal output by the processing unit is filtered by the first-stage linear phase filter and then is filtered by the second-stage linear phase filter and the second-stage minimum phase filter, so as to obtain a linear phase digital signal and a minimum phase digital signal.
As can be seen from the foregoing, in the analog-to-digital converter with ultrahigh resolution provided in one or more embodiments of the present disclosure, a second-order Delta-Sigma modulation-demodulation unit is built by discrete electronic elements such as a second-order integrator circuit, a multi-bit digital-to-analog conversion unit, and an analog-to-digital conversion unit, and multi-bit quantization and multi-bit feedback are implemented by using the multi-bit digital-to-analog conversion unit and the analog-to-digital conversion unit, so that quantization noise and circuit noise are effectively reduced, and a signal-to-noise ratio is improved.
Drawings
In order to more clearly illustrate one or more embodiments or prior art solutions of the present specification, the drawings that are needed in the description of the embodiments or prior art will be briefly described below, and it is obvious that the drawings in the following description are only one or more embodiments of the present specification, and that other drawings may be obtained by those skilled in the art without inventive effort from these drawings.
Fig. 1 is a block diagram of an analog-to-digital converter according to one or more embodiments of the present disclosure;
FIG. 2 is a block diagram of a second order Delta-Sigma modem unit according to one or more embodiments of the present disclosure;
FIG. 3 is a schematic diagram of a signal conditioning circuit according to one or more embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a two-stage integrator circuit according to one or more embodiments of the present disclosure;
fig. 5 is a schematic structural diagram of a digital filtering unit according to one or more embodiments of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be described in further detail below with reference to specific embodiments and the accompanying drawings.
It is to be noted that unless otherwise defined, technical or scientific terms used in one or more embodiments of the present specification should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in one or more embodiments of the specification is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
As shown in fig. 1 and 2, one or more embodiments of the present disclosure provide an ultra-high resolution analog-to-digital converter, which includes a second-order Delta-Sigma modem unit and a digital filter unit;
the second-order Delta-Sigma modulation-demodulation unit comprises a signal arrangement circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit;
the differential analog signal input signal arrangement circuit comprises a differential analog signal input signal arrangement circuit, wherein a differential output end of the signal arrangement circuit is connected with a differential reverse input end of a first-stage integrator circuit, an output end of the first-stage integrator circuit is connected with a differential reverse input end of a second-stage integrator circuit, a differential output end of the second-stage integrator circuit is connected with a differential input end of an analog-to-digital conversion unit, an output end of the analog-to-digital conversion unit is connected with a signal input end of a processing unit, one signal output end of the processing unit is connected with an input end of a first digital-to-analog conversion unit through a phase inverter, a differential output end of the first digital-to-analog conversion unit is connected with a differential reverse input end of the first-stage integrator, the other signal output end of the processing unit is connected with an input end of a second digital-to-analog conversion unit, a differential output end of the second digital-to-analog conversion unit is connected with a differential reverse input end of the second-stage integrator, a digital signal output end of the processing unit is connected with an input end of a digital filtering unit, and the digital filtering unit carries out a digital signal after the input digital signal is filtered.
The differential analog signal is input into the signal arrangement circuit through the differential input end, the signal arrangement circuit amplifies the input differential analog signal, the amplified differential analog signal and the differential analog signal output by the first digital-to-analog conversion unit are input into the first-stage integrator circuit, the first-stage integrator circuit integrates the input signal, the output differential analog signal and the differential analog signal output by the second digital-to-analog conversion unit are input into the second-stage integrator circuit, the second-stage integrator circuit integrates the input signal, the output differential analog signal is input into the analog-to-digital conversion unit, and the analog-to-digital conversion unit converts the input differential analog signal into a digital signal and then inputs the digital signal into the processing unit.
The processing unit receives the digital signal of the analog-digital conversion unit, on one hand, the received digital signal is directly output through one path of signal output end, the path of digital signal is input into the first digital-analog conversion unit after being inverted by the phase inverter, the inverted digital signal is converted into an analog signal by the first digital-analog conversion unit, and the analog signal is input into the first-stage integrator circuit; in the second aspect, the received digital signal is directly output through the other path of signal output end, the path of digital signal is input into a second digital-to-analog conversion unit, the path of digital signal is converted into an analog signal by the second digital-to-analog conversion unit, and the analog signal is input into a second-stage integrator circuit; in the third aspect, the processing unit performs primary filtering processing on the received digital signal, transmits the digital signal after the primary filtering processing to the digital filtering unit, and performs further filtering and decimation processing on the input digital signal by the digital filtering unit to finally output the required digital signal.
In the ultrahigh-resolution analog-to-digital converter provided by the embodiment, the second-order Delta-Sigma modulation and demodulation unit is composed of discrete electronic elements such as a second-stage integrator circuit, a multi-bit digital-to-analog conversion unit and an analog-to-digital conversion unit, the second-stage integrator circuit is constructed based on a low-noise operational amplifier, and multi-bit quantization and multi-bit feedback are realized by adopting the multi-bit digital-to-analog conversion unit and the analog-to-digital conversion unit, so that quantization noise and circuit noise are effectively reduced, and the signal-to-noise ratio is improved. The digital signal output by the second-order Delta-Sigma modulation and demodulation unit is extracted and filtered by the digital filtering unit, and then the high-resolution digital signal is output, so that the data acquisition with ultrahigh resolution and large dynamic range can be realized.
As shown in fig. 3, the signal conditioning circuit is in the form of a completely symmetrical circuit. The signal arrangement circuit comprises two operational amplifiers U1 and U2, differential analog signals are respectively connected with forward input ends of the two operational amplifiers U1 and U2 through resistors R1 (the resistance values are 1K ohm), reverse input ends of the two operational amplifiers U1 and U2 are respectively grounded through resistors 4R, the reverse input ends of the two operational amplifiers U1 and U2 are respectively connected with output ends of the operational amplifiers U1 and U2 through resistors 2R, and two output ends of the two operational amplifiers U1 and U2 form differential output ends which are connected with a differential input end of a first-stage integrator circuit. The resistors in the circuit form matching resistors, so that the stability of the circuit can be ensured, and the input differential analog signals are amplified by a specific amplification factor.
IN some modes, the output signal of the seismic observation instrument is a differential analog signal, the amplitude range of the differential analog signal is-20V-20V, the differential analog signal is input into the differential signal input ends IN + and IN-of the signal sorting circuit and is amplified by 1.5 times through the matching resistors, and the amplitude range of the differential signal output by the differential output ends Vin + and Vin-of the signal sorting circuit is-30V-30V. Optionally, the differential input terminal of the signal sorting circuit may further be provided with a TVS protection circuit for suppressing transient interference that may occur.
As shown in fig. 4, the first-stage integrator circuit and the second-stage integrator circuit are cascaded to form a two-stage integrator circuit, and the two-stage integrator circuit is in a completely symmetrical circuit form. Specifically, the first-stage integrator circuit comprises two operational amplifiers U3 and U4, the differential output ends Vin + and Vin-of the signal conditioning circuit are respectively connected with the reverse input ends of the two operational amplifiers U3 and U4 through a resistor 3R, the forward input ends of the two operational amplifiers U3 and U4 are respectively grounded through a resistor R2 (with the resistance value of 1K ohm), and the output ends of the two operational amplifiers U3 and U4 are respectively connected with the reverse input ends of the operational amplifiers U3 and U4 through capacitors;
the second-stage integrator circuit comprises two operational amplifiers U5 and U6, the output ends of two operational amplifiers U3 and U4 of the first-stage integrator circuit are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 of the second-stage integrator circuit through a resistor 2R, the forward input ends of the two operational amplifiers U5 and U6 are respectively grounded through a resistor R3 (the resistance value is 1K ohm), and the output ends of the two operational amplifiers U5 and U6 are respectively connected with the reverse input ends of the operational amplifiers U5 and U6 through capacitors.
The output ends of the two operational amplifiers U5 and U6 form differential output ends ADC _ P and ADC _ N which are connected with the input end of the analog-to-digital conversion unit, the analog-to-digital conversion unit converts the input analog signal into a digital signal, and the digital signal is transmitted to the processing unit.
In some embodiments, the ADC unit uses a 16-bit ADC chip, the selected ADC chip should satisfy a dynamic range greater than 90db, inl (Integral Nonlinearity) less than 0.5LSB, power consumption of about 10mW, bandwidth suitable for the bandwidth of the ADC, and a reference source of the ADC chip should be filtered to ensure low voltage noise and stable and reliable amplitude. Optionally, the ADC chip meeting the above requirements may be, for example, AD7688, AD1273, AD7693, etc., and taking AD7693 as an example, the ADC chip is a 16-bit successive comparison analog-to-digital converter, the dynamic range is 96.5db, the thd (Total Harmonic Distortion) may reach-120 dB at 1KHz, the power consumption is about 4mW at a sampling rate of 100KHz, and the maximum conversion rate is 500K. Optionally, the sampling rate of the ADC chip is set to 64KHz.
In some embodiments, the first and second digital-to-analog conversion units use four 16-bit DAC chips with the same model, wherein two 16-bit DAC chips are connected in parallel to form the first digital-to-analog conversion unit, and the other 16-bit DAC chips are connected in parallel to form the second digital-to-analog conversion unit. The digital-to-analog conversion unit with a parallel structure is adopted in the feedback loop, so that random noise generated by the DAC can be counteracted, the problems of noise and harmonic distortion caused by nonlinearity of the DAC are reduced, and the performance of the modem is ensured. Optionally, the 16-bit DAC chip may select a chip with a large output range, for example, the output range of the AD5781 chip is-10V.
In some embodiments, the output signals of the first and second digital-to-analog conversion units are calibrated by using preset calibration parameters, and the calibrated signals are input into the first and second integrator circuits respectively, so that the calibrated signals can reduce the influence of noise and distortion introduced by the DAC nonlinearity.
The method for determining the calibration parameters comprises the following steps of setting a digital signal input into a DAC chip as D, an analog voltage signal output by the DAC chip as Vout, a reference voltage input into the DAC chip as VR, and a bit number of the DAC chip as N, wherein the relation between the input digital signal and the output analog voltage signal is as follows:
Vout＝k×D×VR/2N+b (1)
where k is the calibration coefficient and b is the calibration offset.
Dividing the output voltage range of the DAC chip into a plurality of voltage intervals according to a preset voltage interval, inputting different digital signals into each voltage interval, measuring an analog voltage signal which is correspondingly output, and performing fitting processing on the input signal and the output signal according to a formula (1) to obtain a calibration coefficient and a calibration offset of the voltage interval. And obtaining a calibration coefficient and a calibration offset of each voltage interval according to the method, determining the corresponding voltage interval, the calibration coefficient and the calibration offset by the first digital-to-analog conversion unit and the second digital-to-analog conversion unit according to the input digital signal, and obtaining an analog voltage signal output after calibration according to a formula (1) according to the calibration coefficient, the calibration offset and the input digital signal.
For example, the output voltage range of the DAC chip is-10V to 10V, the output voltage range is divided into a plurality of voltage intervals according to a voltage interval of 100mV, for each voltage interval, different digital signals are input to the DAC chip, actual output voltage values corresponding to every 10mV are measured by a voltage measuring instrument, and based on the different digital signals and the measured actual output voltage values, a calibration coefficient and a calibration offset corresponding to the voltage interval are obtained by fitting. Optionally, the fitting method may be linear fitting or polynomial fitting, and the specific manner is not limited.
The processing unit receives the digital signals output by the analog-digital conversion unit through the SPI interface, on one hand, the received digital signals are output to the phase inverter through the SPI interface, the phase inverter inverts the digital signals and then inputs the digital signals into the first digital-analog conversion unit, and the output ends DAC1_ N and DAC1_ P of the first digital-analog conversion unit are connected with the inverting input ends of the operational amplifiers U3 and U4 through the resistor 2R. In the second aspect, the received digital signal is output to the second digital-to-analog conversion unit through the SPI interface, and output terminals DAC2_ P and DAC2_ N of the second digital-to-analog conversion unit are connected to inverting input terminals of operational amplifiers U5 and U6 through a resistor R2. In the third aspect, the received digital signal is primarily filtered, and the primarily filtered signal is input to the digital filtering unit through the SPI interface.
In some modes, the processing unit performs half-band filtering processing on the received digital signal to realize primary filtering of the digital signal. Because half of the filter coefficients of the half-band filtering are 0, the operation amount of the processing unit can be greatly reduced, and the data processing rate is improved. Optionally, the analog-to-digital conversion unit outputs a 64KHz digital signal, and the processing unit extracts a 2KHz signal from the 64KHz digital signal to implement primary filtering. The sampling rate of the analog-to-digital conversion unit can also be increased according to the specific application requirements, for example, the analog-to-digital conversion unit outputs a 512KHz digital signal, and the processing unit extracts a 16KHz digital signal from the 512KHz digital signal.
With reference to fig. 4, the inputs and outputs of the operational amplifiers U3 and U4 of the first-stage integrator circuit are in the form of fully symmetric differential circuits, the non-inverting input terminals of the operational amplifiers U3 and U4 are grounded through resistors with the same resistance, the differential signal output terminals Vin +, vin + of the signal sorting circuit are connected to the inverting input terminals of the operational amplifiers U3 and U4 through resistors 3R, the differential signal output terminals DAC1_ N and DAC1_ P of the first digital-to-analog conversion unit are connected to the inverting input terminals of the operational amplifiers U3 and U4 through resistors 2R, the resistance relationship of the matching resistors is 3: 2, and the amplitude of the input differential analog signal is adjusted to the input range of the operational amplifiers.
The input and output of operational amplifiers U5 and U6 of the second-stage integrator circuit are in a fully symmetrical differential circuit form, the positive phase input ends of the operational amplifiers U5 and U6 are respectively grounded through resistors with the same resistance value, the differential signal output end of the first-stage integrator circuit is respectively connected with the reverse phase input ends of the operational amplifiers U5 and U6 through a resistor 2R, the differential signal output ends DAC2_ P and DAC2_ N of the second digital-to-analog conversion unit are respectively connected with the reverse phase input ends of the operational amplifiers U5 and U6 through a resistor 2R, and after the second-stage integrator circuit adjusts the input signals, the output differential analog signal range is a signal amplitude range of 0V-5V suitable for processing by the analog-to-digital conversion unit.
In some embodiments, the digital filtering unit may be implemented by a 32-bit processor with floating point operations to implement the filtering calculation. The digital filtering unit may configure the multistage filters and filter coefficients of the respective filters so as to output a digital signal of a variable sampling rate using the multistage filters. In some embodiments, the multistage filter includes a first-stage filter and a second-stage filter, the first-stage filter is a first-stage linear phase filter, the second-stage filter includes a second-stage linear phase filter and a second-stage minimum phase filter, and the digital signal output by the processing unit is filtered by the first-stage linear phase filter and then filtered by the second-stage linear phase filter and the second-stage minimum phase filter, respectively, to obtain the linear phase digital signal and the minimum phase digital signal.
As shown in FIG. 5, in some embodiments, the digital filtering unit includes a first order filter FIR-L0 and two second order filters FIR-L1, FIR-M. The digital signal output by the processing unit is input into the data filtering unit to perform two-stage FIR filtering processing, specifically: taking 2000-point sampling data output by the processing unit as an example, the 2000-point sampling data is filtered by a first-stage filter FIR-L0, the decimation ratio is 5, and 400-point sampling data is obtained, the first-stage filter FIR-L0 is a linear phase filter, and the output bandwidth is far higher than the output bandwidth of the analog-to-digital converter, so that a filter with less filter coefficients can be adopted to reduce the calculation amount, for example, the stop band attenuation is 60dB, and the pass band flatness is 1%. Filtering 400-point sampling data output by a first-stage filter FIR-L0 through a second-stage filter FIR-L1, wherein the second-stage filter FIR-L1 is a linear phase filter, the extraction ratio is 2, 200-point sampling data are obtained, and then filtering is performed by the second-stage filter FIR-L1 once again, and 100-point sampling data are obtained; the 400-point sampling data output by the first-stage filter FIR-L0 is filtered by a second-stage filter FIR-M, the second-stage filter FIR-M is a minimum phase filter, the decimation ratio is 2, 200-point sampling data is obtained, and the second-stage filter FIR-M filtering is performed again to obtain 100-point sampling data. Therefore, through the filtering processing of the digital filtering unit, two types of data of 100-point minimum phase data and 100-point linear phase data can be obtained and output as observation data, and a user can select the required type of observation data according to the requirement.
Referring to fig. 1, a clock signal end of the analog-to-digital converter is used for inputting a clock signal, and the clock signal may be a non-return-to-zero clock signal, which can eliminate the influence of clock jitter on the converter. The reset signal end of the analog-to-digital converter is used for inputting a reset synchronous signal, and synchronous reset of a plurality of analog-to-digital converters can be realized. The reference voltage range input by the reference voltage end of the analog-to-digital converter is plus or minus 10V, and the gain of the converter can be controlled to be about 1: 1.
According to the ultrahigh-resolution analog-to-digital converter, a second-order Delta-Sigma modulation-demodulation unit is built by electronic elements such as a second-order integrator circuit, a multi-bit analog-to-digital converter and a digital-to-analog converter, quantization noise and circuit noise are effectively reduced through multi-bit quantization and multi-bit feedback, and the signal-to-noise ratio is improved. A digital-to-analog conversion unit with a parallel structure is used in a feedback loop, and an output signal of the digital-to-analog conversion unit is calibrated to reduce white noise and harmonic distortion caused by nonlinearity. The circuit structures of the signal arrangement circuit, the secondary integrator circuit and the like all adopt a fully symmetrical circuit structure with differential input and output, the circuit is ensured to stably reach the expected performance, the common mode rejection ratio is improved and the anti-interference capability is enhanced by matching symmetrical resistors and capacitors in the differential circuit, and the matching coefficient of the matched symmetrical resistors can reach 0.03%.
In an earthquake observation scene, the sampling rate required by earthquake observation is lower, usually less than 500Hz, the analog-to-digital converter can adopt a lower over-sampling rate, such as 64KHz, and the clock frequency can also be greatly reduced, so that the circuit structure is simplified, the circuit difficulty is reduced, the radiation influence of a high-speed clock on the circuit is reduced, and the noise is reduced. The analog-to-digital converter meeting the earthquake observation requirement is designed according to the circuit structure provided by the application, a digital signal with ultrahigh resolution can be output, and the earthquake data acquisition with the dynamic range exceeding 160dB is realized.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; features from the above embodiments, or from different embodiments, may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of one or more embodiments of the present description, as described above, which are not provided in detail for the sake of brevity.
In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures, for simplicity of illustration and discussion, and so as not to obscure one or more embodiments of the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the understanding of one or more embodiments of the present description, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the one or more embodiments of the present description will be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that one or more embodiments of the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.
While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.
It is intended that the one or more embodiments of the present specification embrace all such alternatives, modifications and variations as fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit or scope of the disclosure are intended to be included within the scope of the disclosure.
Claims (9)
1. An analog-to-digital converter with ultrahigh resolution is characterized by comprising a second-order Delta-Sigma modulation-demodulation unit and a digital filtering unit;
the second-order Delta-Sigma modulation and demodulation unit comprises a signal sorting circuit, a first-stage integrator circuit, a second-stage integrator circuit, an analog-to-digital conversion unit, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit and a processing unit;
the differential analog signal is input into the signal arrangement circuit, the differential output end of the signal arrangement circuit is connected with the differential reverse input end of the first-stage integrator circuit, the output end of the first-stage integrator circuit is connected with the differential reverse input end of the second-stage integrator circuit, the differential output end of the second-stage integrator circuit is connected with the differential input end of the analog-to-digital conversion unit, the output end of the analog-to-digital conversion unit is connected with the signal input end of the processing unit, one signal output end of the processing unit is connected with the input end of the first digital-to-analog conversion unit through a phase inverter, the differential output end of the first digital-to-analog conversion unit is connected with the differential reverse input end of the first-stage integrator, the other signal output end of the processing unit is connected with the input end of the second digital-to-analog conversion unit, the differential output end of the second digital-to-analog conversion unit is connected with the differential reverse input end of the second-stage integrator, the digital signal output end of the processing unit is connected with the input end of the digital filtering unit, and the digital filtering unit filters the input digital signal and outputs the converted digital signal.
2. The analog-to-digital converter according to claim 1, wherein the processing unit performs a primary filtering process on the received digital signal, and transmits the primary filtered digital signal to the digital filtering unit.
3. The analog-to-digital converter according to claim 1, wherein the signal conditioning circuit comprises two operational amplifiers, the differential analog signal is connected to the positive input terminals of the two operational amplifiers through resistors R1, the negative input terminals of the two operational amplifiers are grounded through resistors 4R, the negative input terminals of the two operational amplifiers are connected to the output terminals of the operational amplifiers through resistors 2R, and the two output terminals of the two operational amplifiers form a differential output terminal connected to the differential input terminal of the first stage integrator circuit.
4. The analog-to-digital converter according to claim 3, characterized in that the differential input of the signal conditioning circuit is provided with a TVS protection circuit.
5. The analog-to-digital converter according to claim 1, wherein the first stage integrator circuit comprises two operational amplifiers U3, U4, the differential output terminal of the signal conditioning circuit is connected to the inverting input terminals of the two operational amplifiers U3, U4 through resistors 3R, respectively, the forward input terminals of the two operational amplifiers U3, U4 are grounded through resistors R2, the differential signal output terminal of the first digital-to-analog conversion unit is connected to the inverting input terminals of the two operational amplifiers U3, U4 through resistors 2R, respectively, and the output terminals of the two operational amplifiers U3, U4 are connected to the inverting input terminals of the two operational amplifiers U3, U4 through capacitors, respectively;
the second-stage integrator circuit comprises two operational amplifiers U5 and U6, the output ends of the two operational amplifiers U3 and U4 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through a resistor 2R, the forward input ends of the two operational amplifiers U5 and U6 are respectively grounded through a resistor R3, the differential signal output end of the second digital-to-analog conversion unit is respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through a resistor 2R, and the output ends of the two operational amplifiers U5 and U6 are respectively connected with the reverse input ends of the two operational amplifiers U5 and U6 through capacitors; the output ends of the two operational amplifiers U5 and U6 form a differential output end which is connected with the input end of the analog-to-digital conversion unit.
6. The analog-to-digital converter according to claim 1, wherein the analog-to-digital conversion unit adopts a 16-bit ADC chip; the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are respectively formed by connecting two 16-bit DAC chips in parallel, and the models of the four 16-bit DAC chips are the same.
7. The analog-to-digital converter according to claim 1 or 6, wherein the output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are calibrated by using a preset calibration parameter, and the calibrated signals are respectively input into the first stage integrator circuit and the second stage integrator circuit.
8. The analog-to-digital converter according to claim 1, characterized in that the digital filtering unit is configured with a multistage filter for outputting a digital signal of variable sampling rate.
9. The analog-to-digital converter according to claim 8, wherein the multistage filter comprises a first stage filter and a second stage filter, the first stage filter is a first stage linear phase filter, the second stage filter comprises a second stage linear phase filter and a second stage minimum phase filter, and the digital signal output by the processing unit is filtered by the first stage linear phase filter and then filtered by the second stage linear phase filter and the second stage minimum phase filter, respectively, to obtain a linear phase digital signal and a minimum phase digital signal.
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| CN115276661A (en) * | 2022-07-13 | 2022-11-01 | 中国地震局地震预测研究所 | An ultra-high resolution analog-to-digital converter |
| CN115276661B (en) * | 2022-07-13 | 2025-07-11 | 中国地震局地震预测研究所 | An ultra-high-resolution analog-to-digital converter |
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