CN115459769A - Successive approximation analog-to-digital converter with segmented reference voltage - Google Patents
Successive approximation analog-to-digital converter with segmented reference voltage Download PDFInfo
- Publication number
- CN115459769A CN115459769A CN202211128164.3A CN202211128164A CN115459769A CN 115459769 A CN115459769 A CN 115459769A CN 202211128164 A CN202211128164 A CN 202211128164A CN 115459769 A CN115459769 A CN 115459769A
- Authority
- CN
- China
- Prior art keywords
- comparison
- voltage
- reference voltage
- voltage value
- selection switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013139 quantization Methods 0.000 claims abstract description 25
- 238000009966 trimming Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 59
- 238000005070 sampling Methods 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000013459 approach Methods 0.000 claims description 6
- 230000002457 bidirectional effect Effects 0.000 claims description 4
- 238000013461 design Methods 0.000 claims description 4
- 239000000284 extract Substances 0.000 claims description 3
- 230000009471 action Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a successive approximation analog-to-digital converter with a segmented reference voltage, which comprises a voltage input end, a comparison module and a capacitance trimming control circuit, wherein the voltage input end is connected with the voltage input end; the voltage input end inputs a comparison voltage value and a reference voltage value into the comparison module, the comparison module outputs an obtained comparison result to the capacitance trimming control circuit, and the capacitance trimming control circuit adjusts the comparison voltage value and inputs the comparison voltage value into the comparison module again through the voltage input end; repeating the above operation to make the comparison voltage value successively approximate to the reference voltage value; to ensure the stability of the input voltage during the quantization phase. The invention provides a successive approximation analog-to-digital converter with a segmented reference voltage, which adjusts an input voltage through a set comparison module, and further solves the problems of error in a quantization process and deviation of quantized residual voltage; and the occupied area of the DAC layout can be reduced, and the power consumption is reduced.
Description
Technical Field
The invention relates to a successive approximation analog-to-digital converter with a segmented reference voltage.
Background
A DAC structure in the traditional analog-to-digital converter needs to occupy larger layout area; when the ADC quantizes the non-differential signals, the problems that errors occur in the ADC quantizing process and the quantized residual voltage deviates due to the fact that common-mode voltages are different are solved, the dynamic performance of a middle comparator or a middle-stage amplifier is affected, and the quantized residual voltage and the quantizing precision of the ADC are further affected; in addition, several conventional methods for extracting threshold voltages widely used in long-channel and short-channel transistors are complicated and consume much power, and the accuracy of the voltage level and the high and low potentials determined by the threshold voltage is also poor.
Disclosure of Invention
The invention aims to: in order to overcome the defects in the prior art, the invention provides a successive approximation analog-to-digital converter with a segmented reference voltage, which adjusts the input voltage through a set comparison module, and further solves the problems of error in the quantization process and deviation of quantized residual voltage; and the occupied area of the DAC layout can be reduced, and the power consumption is reduced.
The technical scheme is as follows: in order to achieve the purpose, the technical scheme of the invention is as follows:
a successive approximation analog-to-digital converter with a segmented reference voltage comprises a voltage input end, a comparison module and a capacitance trimming control circuit; the voltage input end inputs the comparison voltage value and the reference voltage value into the comparison module, the comparison module outputs the obtained comparison result to the capacitance trimming control circuit, and the capacitance trimming control circuit adjusts the comparison voltage value and re-inputs the comparison voltage value into the comparison module through the voltage input end; repeating the above operations to make the comparison voltage value gradually approximate to the reference voltage value; to ensure the stability of the input voltage during the quantization phase; the transistors in the circuit of the comparison module adopt a bidirectional component structure design, and can simultaneously generate corresponding resistance values and the action of an inverter so as to accurately judge the voltage level and the potential.
Further, the comparison module comprises a capacitor array with a minimum weight of a segmented reference voltage; the relation between the analog voltage of the capacitor array with the minimum weight of the segmented reference voltage and the output digital code word is as follows:
furthermore, the ADC quantization precision of the capacitor array with the segmented reference voltage and the minimum weight is N +2, and the minimum analog voltage can be distinguished to be 1/2 N+2 *V R (ii) a The generated current has a power consumption of V R /R all 。
Further, the comparison module comprises a sampling module; the sampling module comprises a first selection switch, a second selection switch, a third selection switch, a capacitor CAP and a comparison unit; the first selection switch is connected with the reverse input end of the comparison unit, the positive electrode of the capacitor CAP is connected with a connection node between the first selection switch and the reverse input end of the comparison unit, the negative electrode of the capacitor CAP is grounded, and the second selection switch and the third selection switch are both connected with the non-inverting input end of the comparison unit.
Further, the switch operating state of the third selection switch is opposite to the switch operating states of the first selection switch and the second selection switch.
Further, the comparison step of the sampling module is as follows:
the first step is as follows: the first selection switch and the capacitor CAP sample-hold a reference voltage value VIN of a gating input, and the second selection switch is used for balancing an input voltage of the comparison unit, namely the reference voltage value VIN;
the second step: the comparison unit compares the reference voltage value VIN with the comparison voltage value DAC _ OUT output by the input module, and transmits a comparison result and a middle digital signal CMP _ OUT to the capacitance trimming control circuit;
the third step: the capacitance trimming control circuit adopts SAR logic to enable the generated comparison voltage value DAC _ OUT to approach a reference voltage value VIN according to a comparison result and a middle digital signal CMP _ OUT;
the fourth step: after one analog-to-digital conversion, the result of the analog-to-digital conversion is updated, i.e., DAC _ OUT is updated.
Further, the comparison module comprises a capacitor array adjustable common-mode voltage circuit; a lower capacitor plate of the capacitor array adjustable common-mode voltage circuit samples and compares a voltage value, and an upper capacitor plate samples a reference voltage value of a reference voltage; the lower polar plate of the single-side capacitor is connected with a high reference voltage VREF, and the other capacitor is connected with a low reference voltage GND; according to the charge conservation theorem, the input voltages at two ends of the comparator are VREF-VINP and VREF-VINN respectively; and the capacitor trimming control circuit extracts the comparative voltage value of the upper electrode plate of the capacitor, adjusts the comparative voltage value and gradually approaches the VCM voltage according to the current comparative voltage value.
Further, the implementation steps of the capacitor array adjustable common mode voltage circuit are as follows:
the first step is as follows: the reference voltage VREF is 1V, the GND is 0V, and the comparison voltage values are 0.7V and 0.5V respectively; the input voltages VP and VN at two ends of the comparator are respectively 0.3V and 0.5V;
the second step is that: entering a common mode voltage adjusting stage, wherein the current comparison voltage value is 0.4V and needs to be increased; keeping the potential of the lower C5C pole plate at VREF, raising the potential of the lower C4C pole plate to VREF, and changing the common mode of the upper pole plate to 0.48V and 0.4V +4u/50u + 1V;
the third step: repeating the above processes until the last C0C lower polar plate potential setting is finished; based on the above logic, the C5C to C0C setting should be 11011,1 represents the bottom plate connected to VREF,0 represents the bottom plate connected to GND, and the final comparison voltage value becomes 0.52V, which is closer to the reference voltage value VCM than the voltage of 0.4V.
Further, the input voltage adjustment phase may be performed at any stage in the quantization process.
Has the advantages that: according to the scheme, the input voltage is input to the quantization stage, and the input voltage can be adjusted in two modes of the sampling module and the capacitor array adjustable common-mode voltage circuit, so that the comparison voltage value is enabled to gradually approach the reference voltage value; the input voltage is ensured to be kept relatively constant, the influence on the dynamic performance of the intermediate comparator or the intermediate-stage amplifier is reduced, and the influence on the quantized residual voltage and the quantization precision of the ADC is reduced; and the analog-digital converter with the segmented reference voltage minimum weight capacitor array can greatly reduce the area and the conversion power consumption of the high-precision analog-digital converter.
Drawings
FIG. 1 is a circuit layout diagram of a successive approximation analog-to-digital converter with segmented reference voltages;
FIG. 2 is a circuit layout of a minimum weight capacitor array with segmented reference voltages;
FIG. 3 is a circuit layout diagram of a sampling module;
FIG. 4 is a diagram of the relative positions of the input voltage regulation stages;
FIG. 5 is a circuit layout diagram of a comparison unit or comparator;
fig. 6 is a transistor circuit layout diagram of the amplifier.
Detailed Description
The present invention will be further described with reference to the accompanying drawings.
As shown in figures 1-6: a successive approximation analog-to-digital converter with a segmented reference voltage comprises a voltage input end 3, a comparison module 31 and a capacitance trimming control circuit 32; the voltage input end 3 inputs the comparison voltage value and the reference voltage value into the comparison module 31, the comparison module 31 outputs the obtained comparison result to the capacitance trimming control circuit 32, and the capacitance trimming control circuit 32 adjusts the comparison voltage value and inputs the comparison voltage value into the comparison module 31 again through the voltage input end 3; repeating the above operations to make the comparison voltage value gradually approximate to the reference voltage value; to ensure the stability of the input voltage during the quantization phase; the transistors in the circuit of the comparison module 31 are designed as bidirectional components, and can generate corresponding resistance values and the function of the inverter at the same time, so as to accurately judge the voltage level and the potential. The change of the input voltage value can affect the dynamic performance of the middle comparator or the middle-stage amplifier, and further affect the quantization residual voltage and the quantization precision of the ADC; the capacitance trimming control circuit 32 adjusts the input voltage value to achieve the effect that the input voltage is relatively constant in the quantization process, so as to reduce the influence on the quantization residual voltage and the quantization precision of the ADC.
The comparison module 31 comprises a capacitor array 4 with a minimum weight of a segmented reference voltage; when N is designed as quantization precision, the structure at least needs 2N-1 capacitors; the relation between the analog voltage of the capacitor array 4 with the minimum weight of the segmented reference voltage and the output digital code word is as follows:
the analog-to-digital converter with segmented reference voltage minimum weight capacitor array 4 is schematically shown in fig. 2, and the biggest difference is that the least significant bit capacitor can not only act, but also receive a plurality of proportional reference voltages. The ADC quantization precision of the capacitor array 4 with the minimum weight of the segmented reference voltage is N +2, and the minimum analog voltage can be distinguished to be 1/2N +2 VR; the power consumption of the generated current is VR/Rall. The generation of the multiple reference voltages is in the form of resistive voltage division, as shown on the right side of fig. 2. The generated current power consumption is VR/Rall, and when the resistance reaches the level of 100k omega, the quiescent current power consumption is controlled to be about 10 microamperes. When designing an ADC with 16 d precision, the total number of unit capacitors will be reduced from 32768 to 8192. Compared with the reduced area, the additionally increased resistance area is negligible. The power consumption is several orders of magnitude smaller than that of the nearly 1 ma interstage amplifier. The area and conversion power consumption of the high-precision analog-to-digital converter are greatly reduced.
The comparison module 31 comprises a sampling module 1; the sampling module 1 comprises a first selection switch 11, a second selection switch 12, a third selection switch 13, a capacitor CAP and a comparison unit 14; the first selection switch 11 is connected to the inverting input terminal of the comparing unit 14, the positive electrode of the capacitor CAP is connected to the connection node between the first selection switch 11 and the inverting input terminal of the comparing unit 14, the negative electrode of the capacitor CAP is grounded, and the second selection switch 12 and the third selection switch 13 are both connected to the non-inverting input terminal of the comparing unit 14; wherein, through the third selection switch 13, the output end of the voltage input end 3 is connected to the non-inverting input end of the comparing unit 14, so that the comparison voltage value DAC _ OUT can be input to the non-inverting input end of the comparing unit 12.
The switch working state of the third selection switch 13 is opposite to the switch working state of the first selection switch 11 and the second selection switch 12; specifically, it needs to be ensured that the switch control signals for controlling the second selection switch 12 and the third selection switch 13 are not enabled at the same time, that is, the second selection switch 12 and the third selection switch 13 are not closed at the same time (the switch operating states of the two are opposite), so as to prevent the reference voltage value VIN and the comparison voltage value DAC _ OUT from being short-circuited; in operation, the first selection switch 11 and the second selection switch 12 are simultaneously closed, so that the non-inverting input terminal and the inverting input terminal of the comparison unit 14 receive the reference voltage VIN to balance the input voltage of the comparison unit 14.
As shown in fig. 1, the comparison steps of the sampling module 1 are:
the first step is as follows: the first selection switch 11 and the capacitor CAP sample-hold gate input reference voltage value VIN, the second selection switch 12 is used for balancing the input voltage of the comparison unit 14, i.e. the reference voltage value VIN;
the second step is that: the comparing unit 14 compares the reference voltage value VIN with the comparison voltage value DAC _ OUT output by the input module, and transmits a comparison result, i.e., an intermediate digital signal CMP _ OUT, to the capacitance trimming control circuit 32;
the third step: the capacitance trimming control circuit 32 adopts SAR logic to enable the generated comparison voltage value DAC _ OUT to approach the reference voltage value VIN according to the comparison result and the intermediate digital signal CMP _ OUT;
the fourth step: after the first analog-to-digital conversion, updating the result of the analog-to-digital conversion, namely updating DAC _ OUT; the capacitance trimming control circuit 32 adjusts the comparison voltage value DAC _ OUT to approach the reference voltage value VIN, so as to ensure that the input voltage at the final input quantization stage is relatively constant, and reduce the influence on the quantization residual voltage and the quantization precision of the ADC.
The comparison module 31 comprises a capacitor array adjustable common-mode voltage circuit; comparing voltage values of all capacitor lower electrode plates in the capacitor array adjustable common-mode voltage circuit, and sampling a reference voltage value VCM of reference voltage by a capacitor upper electrode plate; after sampling is finished, the upper polar plate sampling switch is firstly switched off, the lower polar plate switch is then switched off, the C5 and C5C lower polar plates of the single-side capacitor are connected with a high VREF reference voltage, and the other capacitors are connected with a low GND reference voltage; according to the charge conservation theorem, the input voltages VP and VN at the two ends of the comparator 2 are VREF-VINP and VREF-VINN respectively; the capacitance trimming control circuit 32 extracts a comparison voltage value of the upper electrode plate of the capacitor, and gradually approximates the current comparison voltage value to the VCM voltage by adjusting the common mode adjustment capacitors at both sides. Any capacitor array is composed of a common-mode adjusting capacitor and a quantization capacitor, VINP and VINN are a pair of input signals, VREF is high reference voltage, GND is low reference voltage, VCM is common-mode voltage of the reference voltage, VP and VN are input voltages of the positive end and the negative end of a comparator respectively, and u represents the size of the capacitor.
As shown in fig. 3, the implementation steps of the capacitor array adjustable common mode voltage circuit are as follows:
the first step is as follows: the reference voltage VREF is 1V, the GND is 0V, and the comparison voltage values are 0.7V and 0.5V respectively; the input voltages VP and VN at two ends of the comparator 2 are 0.3V and 0.5V respectively;
the second step is that: entering a common mode voltage adjusting stage, wherein the current comparison voltage value is 0.4V and needs to be increased; keeping the potential of the lower C5C pole plate at VREF, raising the potential of the lower C4C pole plate to VREF, and changing the common mode of the upper pole plate to 0.48V and 0.4V +4u/50u + 1V;
the third step: repeating the above processes until the last C0C lower polar plate potential setting is finished; based on the above logic, the setting of C5C to C0C should be 11011,1 represents that the bottom plate is connected to VREF,0 represents that the bottom plate is connected to GND, and the final comparison voltage value becomes 0.52V, which is closer to the reference voltage value VCM than the voltage of 0.4V. FIG. 4 is a diagram of relative positions of input voltage debug stages as follows; the input voltage adjustment phase may be performed at any stage in the quantization process. The analog-to-digital converter can adjust the common-mode voltage of a non-differential signal, namely the input voltage, and solves the problem of non-linear errors caused by common-mode voltage deviation in the design process of a high-precision ADC. The input voltage can be adjusted through two modes of the sampling module and the capacitor array adjustable common-mode voltage circuit, so that the input voltage is ensured to be kept relatively constant, the influence on the dynamic performance of a middle comparator or a middle-stage amplifier is reduced, and the influence on the quantized residual voltage and the quantization precision of the ADC is reduced.
As shown in fig. 5, the comparison unit or comparator is composed of a current adder 21, an amplifier 22 and a dynamic latch 23 connected in sequence; the threshold voltage extraction method applied to the long-channel transistor and the short-channel transistor in the amplifier circuit is complex and consumes power, and the accuracy of the voltage level and the high potential and low potential judged by the threshold voltage is poor; therefore, the arrangement design structure of the transistor shown in fig. 6 is utilized, and the design of the bidirectional component is utilized to simultaneously generate the corresponding resistance value and the function of the inverter, so as to achieve the purpose of accurately judging the voltage level and the potential.
The above is only a preferred embodiment of the present invention, and is not intended to limit the technical solutions of the present invention, and it will be apparent to those skilled in the art that a number of modifications and changes can be made without departing from the above-mentioned principle of the present invention, and these modifications and changes are also considered to be within the scope of the present invention.
Claims (9)
1. A successive approximation analog-to-digital converter with a segmented reference voltage comprises a voltage input end (3), a comparison module (31) and a capacitance trimming control circuit (32); the method is characterized in that: the voltage input end (3) inputs a comparison voltage value and a reference voltage value into the comparison module (31), the comparison module (31) outputs an obtained comparison result to the capacitance trimming control circuit (32), and the capacitance trimming control circuit (32) adjusts the comparison voltage value and re-inputs the comparison voltage value into the comparison module (31) through the voltage input end (3); repeating the above operations to make the comparison voltage value gradually approximate to the reference voltage value; to ensure the stability of the input voltage during the quantization phase; the transistors in the circuit of the comparison module (31) adopt a bidirectional component structure design, and can generate corresponding resistance values and the action of an inverter at the same time so as to accurately judge the voltage level and the potential.
2. The successive approximation analog-to-digital converter with a segmented reference voltage according to claim 1, characterized in that: the comparison module (31) comprises a capacitor array (4) with a minimum weight of a segmented reference voltage; the relation between the analog voltage of the capacitor array (4) with the minimum weight of the segmented reference voltage and the output digital code word is as follows:
3. the successive approximation analog-to-digital converter with segmented reference voltage of claim 2Characterized in that: the ADC quantization precision of the capacitor array (4) with the minimum weight of the segmented reference voltage is N +2, and the minimum analog voltage can be distinguished to be 1/2 N+2 *V R (ii) a The generated current has a power consumption of V R /R all 。
4. A successive approximation analog-to-digital converter with a segmented reference voltage according to claim 3, characterized in that: the comparison module (31) comprises a sampling module (1); the sampling module (1) comprises a first selection switch (11), a second selection switch (12), a third selection switch (13), a capacitor CAP and a comparison unit (14); the first selection switch (11) is connected with the inverting input end of the comparison unit (14), the positive pole of the capacitor CAP is connected with a connection node between the first selection switch (11) and the inverting input end of the comparison unit (14), the negative pole of the capacitor CAP is grounded, and the second selection switch (12) and the third selection switch (13) are both connected with the non-inverting input end of the comparison unit (14).
5. The successive approximation analog-to-digital converter with segmented reference voltages of claim 4, wherein: the switch working state of the third selection switch (13) is opposite to the switch working states of the first selection switch (11) and the second selection switch (12).
6. The successive approximation analog-to-digital converter with a segmented reference voltage according to claim 5, characterized in that: the comparison step of the sampling module (1) is as follows:
the first step is as follows: the first selection switch (11) and the capacitor CAP sample-and-hold a gated input reference voltage value VIN, the second selection switch (12) is used for balancing an input voltage of the comparison unit (14), namely the reference voltage value VIN;
the second step is that: the comparison unit (14) compares the reference voltage value VIN with the comparison voltage value DAC _ OUT output by the input module, and transmits a comparison result and an intermediate digital signal CMP _ OUT to the capacitance trimming control circuit (32);
the third step: the capacitance trimming control circuit (32) adopts SAR logic according to the comparison result and the intermediate digital signal CMP _ OUT to enable the generated comparison voltage value DAC _ OUT to approach the reference voltage value VIN;
the fourth step: after one analog-to-digital conversion, the result of the analog-to-digital conversion is updated, i.e. DAC _ OUT is updated.
7. The successive approximation analog-to-digital converter with segmented reference voltages of claim 3, wherein: the comparison module (31) comprises a capacitor array adjustable common-mode voltage circuit; a lower capacitor plate of the capacitor array adjustable common-mode voltage circuit samples and compares a voltage value, and an upper capacitor plate samples a reference voltage value of a reference voltage; the lower polar plate of the single-side capacitor is connected with a high reference voltage VREF, and the other capacitor is connected with a low reference voltage GND; according to the charge conservation theorem, the input voltages at two ends of the comparator (2) are VREF-VINP and VREF-VINN respectively; the capacitance trimming control circuit (32) extracts the comparison voltage value of the upper electrode plate of the capacitor, adjusts the comparison voltage value and successively approximates the current comparison voltage value to the VCM voltage.
8. The successive approximation analog-to-digital converter with segmented reference voltages of claim 7, wherein: the implementation steps of the capacitor array adjustable common-mode voltage circuit are as follows:
the first step is as follows: the reference voltage VREF is 1V, the GND is 0V, and the comparison voltage values are 0.7V and 0.5V respectively; the input voltages VP and VN at two ends of the comparator (2) are respectively 0.3V and 0.5V;
the second step is that: entering a common mode voltage adjusting stage, wherein the current comparison voltage value is 0.4V and needs to be increased; keeping the potential of the lower C5C pole plate at VREF, raising the potential of the lower C4C pole plate to VREF, and changing the common mode of the upper pole plate to 0.48V and 0.4V +4u/50u + 1V;
the third step: repeating the process until the potential setting of the last C0C lower polar plate is finished; based on the above logic, the setting of C5C to C0C should be 11011,1 represents that the bottom plate is connected to VREF,0 represents that the bottom plate is connected to GND, and the final comparison voltage value becomes 0.52V, which is closer to the reference voltage value VCM than the voltage of 0.4V.
9. The successive approximation analog-to-digital converter with a segmented reference voltage according to claim 1, characterized in that: the input voltage adjustment phase may be performed at any stage in the quantization process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211128164.3A CN115459769A (en) | 2022-09-16 | 2022-09-16 | Successive approximation analog-to-digital converter with segmented reference voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211128164.3A CN115459769A (en) | 2022-09-16 | 2022-09-16 | Successive approximation analog-to-digital converter with segmented reference voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115459769A true CN115459769A (en) | 2022-12-09 |
Family
ID=84304679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211128164.3A Pending CN115459769A (en) | 2022-09-16 | 2022-09-16 | Successive approximation analog-to-digital converter with segmented reference voltage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115459769A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115967402A (en) * | 2022-12-21 | 2023-04-14 | 安徽大学 | A switch connection method of ADC sampling circuit and its circuit and chip |
| CN116614135A (en) * | 2023-05-18 | 2023-08-18 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
| CN119397158A (en) * | 2024-10-24 | 2025-02-07 | 中国计量科学研究院 | A Josephson array driving method and system based on bidirectional successive approximation algorithm |
-
2022
- 2022-09-16 CN CN202211128164.3A patent/CN115459769A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115967402A (en) * | 2022-12-21 | 2023-04-14 | 安徽大学 | A switch connection method of ADC sampling circuit and its circuit and chip |
| CN116614135A (en) * | 2023-05-18 | 2023-08-18 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
| CN116614135B (en) * | 2023-05-18 | 2024-04-09 | 金华高等研究院(金华理工学院筹建工作领导小组办公室) | Dynamic comparator suitable for synchronous sequential SAR ADC and control method |
| CN119397158A (en) * | 2024-10-24 | 2025-02-07 | 中国计量科学研究院 | A Josephson array driving method and system based on bidirectional successive approximation algorithm |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10135457B2 (en) | Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter | |
| CN104242935B (en) | A kind of bearing calibration of SAR ADC sectional capacitance mismatches | |
| CN115459769A (en) | Successive approximation analog-to-digital converter with segmented reference voltage | |
| CN109039332B (en) | Successive approximation type analog-to-digital converter and low-power-consumption switching algorithm thereof | |
| CN113839673B (en) | A Novel Self-calibrating Successive Approximation Analog-to-Digital Converter in the Digital Domain | |
| CN113794475B (en) | Calibration method of capacitor array type successive approximation analog-digital converter | |
| CN109379082B (en) | Successive approximation analog-to-digital converter | |
| CN111431529B (en) | Successive approximation type analog-to-digital converter with capacitance mismatch correction function | |
| CN109120268A (en) | A kind of dynamic comparer offset voltage calibration method | |
| CN108306644B (en) | Front-end circuit based on 10-bit ultra-low power consumption successive approximation type analog-to-digital converter | |
| CN110198169B (en) | An Adaptive Predictive Low Power Switching Method for SAR ADC | |
| CN108832928B (en) | Common-mode voltage correction circuit of SAR ADC capacitor array and correction method thereof | |
| CN113014263B (en) | A capacitor array and switching logic circuit of a successive approximation ADC | |
| CN112039528B (en) | Capacitor array logic control method in successive approximation analog-to-digital converter | |
| CN111565042A (en) | A Calibration Method for Two-Step ADC | |
| CN113676183B (en) | High-precision low-power-consumption SAR ADC based on two steps | |
| TW201924227A (en) | Method and apparatus for enabling wide input common-mode range in SAR ADCs with no additional active circuitry | |
| CN105811984B (en) | Input sampling and converting circuit | |
| CN108111171B (en) | Monotonic switching method suitable for differential structure successive approximation type analog-to-digital converter | |
| TWI788951B (en) | Comparison control circuit, and analog-to-digital converter and low dropout regulator having the same | |
| CN115441868B (en) | Analog-to-digital converter, detection device, conversion method and adjustment method | |
| CN115473531B (en) | High-precision high-linearity analog-to-digital converter with low power consumption and small layout | |
| CN109039338B (en) | Differential capacitor array and switching method thereof | |
| KR101986699B1 (en) | Successive approximation register analog digital converter and operating method thereof | |
| CN113131940B (en) | A Capacitor Sequencing Circuit for Capacitive Successive Approximation Analog-to-Digital Converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |