CN115831875A - Integrated circuit comprising standard cells and at least one capacitive fill structure - Google Patents

Abstract

Embodiments of the present disclosure relate to integrated circuits including standard cells and at least one capacitive fill structure. An integrated circuit includes a logic portion comprising standard cells in parallel rows along a first direction and with an alternating arrangement of complementary semiconductor wells. In a standard cell at least one capacitive filling structure belongs to two adjacent rows and comprises a capacitive interface between a conductive armature and a first well, said second well extending in said first direction within said capacitive The capacitive fill structure is interrupted over the length of the capacitive fill structure such that the first well occupies the width of two adjacent rows of the capacitive fill structure in the second direction. The conductive structure electrically connects the second well on either side of the capacitive fill structure.

Description

Integrated circuit comprising standard cells and at least one capacitive fill structure

priority claim

This application claims priority from French Patent Application No. 2109789 filed September 17, 2021, the entire content of which is hereby incorporated by reference to the fullest extent permitted by law.

technical field

Embodiments and embodiments relate to integrated circuits, and more particularly to logic portions of integrated circuits including standard cells and capacitive fill structures.

Background technique

Typically, standard cells are the "building blocks" of the logic portion of an integrated circuit. Standard cells are predesigned and characterized with basic logic functions, such as logic functions "NOT", "AND", "OR", "XOR", etc., which can be combined with each other in a fully compatible manner in order to design complex logic mechanisms.

Physically, combinations of standard cells are usually arranged in rows of logical sections with a fixed width corresponding to the width imposed on each standard cell. The rows of the logic section may each contain a plurality of standard cells in length, and the length of each standard cell may vary according to the basic logic function of the cell.

Basic logic functions are usually implemented using "complementary metal-oxide-semiconductor" (CMOS) technology, including the per se known "NMOS" using n-channel MOS transistors in p-type semiconductor wells, and p-channel MOS transistors in n-type semiconductor wells "PMOS" for MOS transistors.

In addition, logic components can advantageously include capacitive structures called "fillers" because they are formed in spaces that can accommodate standard cells, but leave gaps in rows of logic components due to the nature of the design of complex logic mechanisms . Thus, the capacitive fill structure allows occupying available space in the logic portion of the integrated circuit and thus reduces the surface footprint of capacitive elements, typically resistive-capacitive (RC) filter capacitive elements that reduce supply voltage variations.

In order to further limit the surface footprint of the capacitive element, it is advantageous to increase the capacitance value per unit surface area of the capacitive filling structure. In this regard, the realization of a capacitive element of a capacitive structural architecture of the "Metal Oxide Semiconductor" (MOS) type has been proposed, in which the conductive armature comprises a trench filled with a conductive material, the trench in terms of depth in a complementary well Extending vertically and longitudinally in the direction of the surface of the logic component.

That is, the capacitance value of this type of capacitive structure is limited by the composition of the complementary well of a standard cell of CMOS type.

In fact, on the one hand, in order to operate in depletion mode, the well containing the capacitive structure (usually N-type) is polarized to a non-zero voltage, usually the supply voltage. Therefore, well taps are provided and occupy surfaces that contribute only slightly to capacitive effects.

Furthermore, when this type of MOS capacitive structure is adapted to operate in NOT mode, typically in a p-type well, the longitudinal ends of the trench must be separated from an adjacent well of the opposite type (usually an adjacent N-type well). Open a non-negligible distance to avoid current flow through the pass-transistor effect. Here again, the separation distance occupies the surface that does not contribute to the capacitive effect.

Contents of the invention

The embodiments and examples defined below propose to introduce a discontinuity in the arrangement of the complementary wells of the logic part at the capacitive filling structure, allowing to eliminate the above-mentioned problems while increasing the capacitance value per unit surface area. Furthermore, the embodiments and embodiments do not introduce constraints on the combinatorial possibilities and compatibility of standard cells, and are especially compatible with non-well-tapped technologies.

According to one aspect, in this respect, an integrated circuit is proposed comprising a logic part comprising standard cells arranged in parallel rows along a first direction, and the logic part has a fixed width perpendicular to the first The second direction of the direction covers half the width of the first semiconductor well doped with a first type (for example, P-type) and the second semiconductor well with a second type of doping (for example, N-type) opposite to the first type. Half width, each well is shared by two adjacent rows. In a standard cell at least one capacitive filling structure belongs to two adjacent rows and comprises a capacitive interface between a conductive armature and a first well, said second well extending in said first direction within said capacitive The capacitive filling structure is interrupted over the length of the capacitive filling structure, so that the first well occupies the width of two rows of the capacitive filling structure in the second direction, and the capacitive filling structure also includes a conductive structure, and the conductive structure is suitable for The second well on either side of the capacitive fill structure is electrically connected in the first direction.

Thus, the capacitive interface formed by the conductive armature and the first well can be considerably enlarged, since the first well occupies the entire width of the capacitively filled structure via the absence of the second well. The effect of enlarging the capacitive interface is also obtained in case the conductive armature does not comprise a trench filled with conductive material, the trench extending vertically in terms of depth in the first well.

This further allows eliminating the condition of separation distance between the capacitive structure and the second well and the need for well taps.

Furthermore, the electrical continuity of the second well is ensured by the conductive structure, although its extent is interrupted, ie there is no second well above the length of the capacitive filling structure.

According to one embodiment, the conductive structure comprises at least one metal track located in the metal level and extending in a first direction opposite the length of the capacitively filled structure, the capacitive interface in a second direction in the capacitively filled structure. Constructed to extend across the entire width of the two rows.

This advantageously allows dedicating the entire extent of the width of the two rows of capacitive filling structures, and in addition ensures electrical continuity of the second well with the conductive structure, which may allow reducing the number of well taps (usually regularly arranged within the confines of the well ), the conductive structure has a resistance lower than that of the second well.

According to one embodiment, the conductive structure comprises a surface semiconductor strip with a strong doping of the second type, which is located in the first well and extends in the first direction over the length of the capacitive filling structure, said The capacitive interface extends in the second direction over the entire width of the two rows of capacitive filling structures except for the width of the surface semiconductor strips.

Thus, a quasi-population of the width range of two rows, for example greater than 60% or even greater than 80%, is dedicated to the capacitive filling structure, and here the conductive structure may have a lower resistance than the resistance of the second well, thereby allowing a reduction to be provided The number of well taps.

For example, the surface semiconductor strips include metal suicides.

For example, the conductive structure comprises shallow insulating trenches on either side of the surface semiconductor strip in the second direction.

For example, said surface semiconductor strips comprise dopant species of the first type implanted in the first well at a density between 1×10 ¹⁵ atoms per cubic centimeter and 1×10 ¹⁶ atoms per cubic centimeter.

According to one embodiment, said conductive armature of the capacitive filling structure comprises at least one vertical gate structure extending in depth in the first well.

According to one embodiment, the at least one vertical gate structure includes a region implanted with second type doping at the vertical end of the vertical gate located at the first well depth, and the vertical gate structure located at the surface of the first well The vertical end of the region is implanted with a second type of doping.

A doped region implanted at the vertical end of the vertical gate structure can be applied by the fabrication of the vertical gate, but advantageously allows operation in NOT mode, generally more stable with respect to voltage variation in capacitance value.

And, in particular, this embodiment does not suffer from the problem of current flow via the turn-on transistor effect (forming a conducting channel) between said doped regions and adjacent wells polarized to different voltages.

According to an embodiment, the conductive armature of the capacitive filling structure further includes at least one horizontal gate structure, and the at least one vertical gate structure is located on the side of the first well facing the at least one vertical gate structure. on the surface of the structure.

According to one implementation, the integrated circuit further includes a non-volatile memory, the non-volatile memory includes a memory cell, the memory cell is provided with a vertical gate buried access transistor and a floating gate state transistor, and the conductive The vertical gate structure of the armature is composed of the same material and has the same depth as the vertical gate of the buried access transistor of the memory cell.

Such an implementation of the integrated circuit advantageously allows the manufacture of shared non-volatile memory cells and capacitive filling structures, in particular, that is to say, in practice, manufacturing the capacitive filling mechanism without additional costs.

According to another aspect, there is also proposed a method for manufacturing an integrated circuit, comprising manufacturing a logic component comprising forming a first semiconductor well with doping of a first type and having a second semiconductor well opposite to the first type alternating portions of second type doped semiconductor wells, the first semiconductor wells extending parallel in a first direction, and fabricating the logic component includes forming standard cells arranged in parallel rows in the first direction, and The integrated circuit has a fixed width covering half the width of one of the first wells and half the width of one of the second wells in a second direction perpendicular to the first direction, each well consisting of Shared by two adjacent rows. The method also includes forming at least one capacitive fill structure belonging to two adjacent rows in the middle of the standard cell, and includes forming a capacitive interface between the conductive armature and the first well, the second well being formed such that it The extension in one direction is interrupted over the length of the capacitive fill structure, the first well is formed to occupy the width of two rows of the capacitive fill structure in the second direction, the capacitive fill structure The forming of also includes the formation of a conductive structure configured to be in place.

According to one embodiment, the formation of the conductive structure comprises the formation of at least one metal track located in the metal layer and extending in a first direction opposite to the length of the capacitive filling structure, and the capacitive interface is formed in the second Both directions extend over the entire width of the two rows of capacitive filling structures.

According to one embodiment, the forming of the conductive structure comprises forming a surface semiconductor strip with a strong doping of the second type in the first well, and the surface semiconductor strip extends in the first direction over the length of the capacitive filling structure, and The capacitive interface is formed to extend in the second direction over the entire width of the two rows of capacitive filling structures except for the width of the surface semiconductor strips.

For example, the formation of the surface semiconductor strips includes a silicide step of forming a metal silicide in the surface semiconductor strips.

For example, the formation of the conductive structure comprises forming shallow insulating trenches on either side of the surface semiconductor strip in the second direction.

For example, the formation of the surface semiconductor strips includes implanting the dopant species of the first type at a density between 1×10 ¹⁵ atoms per cubic centimeter and 1×10 ¹⁶ atoms per cubic centimeter in the first well.

According to one embodiment, the formation of the conductive armature comprises the formation of at least one vertical gate structure, the vertical gate extending in depth in the first well.

For example, the formation of the vertical gate structure includes forming a trench etched in the first well and covering the dielectric cladding layer on the bottom and sides, implanting a second-type doped electrode into the first well at the bottom of the trench. region, filling the trench with a conductive material, implanting a region with doping of the second type in the trench, and implanting a region with doping of the second type adjacent to the trench on the surface of the first well.

For example, the forming of the conductive armature of the capacitive filling structure further includes forming at least one horizontal gate structure, the at least one vertical gate structure is located on the first well surface of the at least two vertical gate structures. on the surface of the polar structure.

According to one embodiment, the method further includes fabricating a non-volatile memory comprising a memory cell provided with a vertical gate buried access transistor and a floating gate state transistor, and the conductive The formation of the vertical gate structure of the armature occurs simultaneously with the formation of the vertical gate of the buried access transistor of the memory cell.

Description of drawings

Other advantages and features will emerge after examining the detailed description (not limiting in any way) of the embodiments and examples and the accompanying drawings, in which:

Figure 1 shows an integrated circuit including logic and other peripheral parts;

Figures 2A-2C illustrate the implementation of conductive structures;

3A-3C illustrate another embodiment of a conductive structure;

4A-4I illustrate steps in a method of fabricating an integrated circuit, as described above with respect to FIG. 1 .

Detailed ways

Fig. 1 shows an example of an integrated circuit CI comprising a logic part LG and other peripheral parts such as a non-volatile memory part NVM and a high voltage part HV. It should be noted that the proportions shown in Figure 1 are not necessarily to scale.

The logic part LG includes standard cells CPC, each cell configured to implement basic logic functions such as AND, OR logic gates, latches, etc. using CMOS technology. Therefore, each standard cell CPC is formed on the first semiconductor well PW having a doping of a first type, ie, for example, P-type, and formed on a doping of a second type opposite to the first type (ie, for example, , N-type) on the second semiconductor well NW.

Furthermore, the organization of the standard cells CPC in the logic part LG is realized by arranging the standard cells CPC in parallel rows RG along the first direction X, which defines the length of the row RG and is perpendicular to the A direction X and a second direction Y have a fixed width W_RG, and the fixed width W_RG is applied to each standard cell CPD. The length of the standard cell CPC is free and can vary according to the size of the logic circuit constituting it.

The first wells PW and the second wells NW of the logic part LG are alternately arranged in parallel along the first direction X such that each well PW, NW is shared by two adjacent rows RG. Thus, the row covers a width W_RG in the second direction Y, ie half the width of the first semiconductor well PW and half the width of the second semiconductor well NW.

Furthermore, in the standard cell CPC, the logic part LG comprises at least one capacitive filling structure SCR, located in the row RG in a position not occupied by the standard cell CPC. Each capacitive fill structure SCR includes a capacitive interface between the conductive armature and the first well PW.

Each capacitive filling structure SCR belongs to two adjacent rows, and the extent of the second well NW in the first direction X is interrupted, that is, the second well NW is not formed between the length of the capacitive filling structure L_SCR position on the For the first well PW, it occupies the width of two rows RG of the capacitive filling structure W_SCR in the second direction Y.

Therefore, as will be described below with reference to FIGS. 2A-2C and FIGS. 3A-3C , the capacitive interface may be formed to extend in the second direction Y over the entire or nearly entire width of the two rows of capacitive filling structures W_SCR.

Furthermore in order to ensure electrical continuity in the second semiconductor well NW, each capacitive filling structure SCR comprises a conductive structure COND (schematically shown in FIG. 1 by a horizontal line (according to the X direction) connecting two points), which The second well NW on either side of the capacitive filling structure SCR is electrically connected in the first direction X.

In this regard, in particular two implementations of the conductive structures CONDa, CONDb are described with reference to FIGS. 2A-2C and FIGS. 3A-3C .

2A shows a top view of a first example of a capacitive filling structure SCRa in a plane (X-Y), FIG. 2B shows a cross-sectional view of a capacitive filling structure CRA in a plane BB (X-Z) of FIG. 2A , FIG. 2C A cross-sectional view of the capacitive filler structure SCRa on plane CC(Y-Z) of FIG. 2A is shown. The directions X, Y, Z correspond to the orthogonal reference frame shared by Figures 2A, 2B and 2C.

In this example, the conductive structure CONDa is electrically connected to the second well NW on either side of the capacitive filling structure SCRa via a metal track M1 extending in the first direction X over the length of the capacitive filling structure L_SCR. The metal track M1 is located in a metal layer, eg a first metal layer, of an interconnection part commonly referred to as back end of line (BEOL) formed above the front side FA of the semiconductor part, commonly referred to as back end of line (FEOL). The front side FA generally means the surface of the semiconductor substrate and the surfaces of the semiconductor wells PW, NW on which semiconductor devices such as MOS type transistors and capacitive elements are formed.

Thus, the conductive structure CONDa does not particularly occupy space in the first well PW and leaves the entire width W_SCR of the first well PW completely free to form a capacitive interface therein.

The conductive armature ARM forming a MOS-type capacitive interface with the first well PW advantageously comprises at least one vertical gate structure SGV extending vertically (in direction Z) in terms of depth in the first well PW . The vertical gate structure SGV includes a conductive material, such as polysilicon, filling the trench etched in the first well PW. A dielectric cladding is provided on the sides and bottom of the trench to electrically insulate the conductive material from the first well PW.

Furthermore, the vertical gate structures SGV extend in length in the second direction Y and are parallel to each other along the second direction Y. The width of the vertical gate structures SGV in the first direction X is minimized in order to multiply the number of parallel vertical gate structures SGV contained in the length L_SCR (first direction X) of the capacitive filling structure SCRa.

Furthermore, in this example the conductive armature ARM of the capacitive filling structure SCR also comprises a horizontal gate structure SGH on the surface of the first well PW facing the at least one vertical gate structure SGV. The horizontal gate structure SGH is electrically connected to the vertical gate structure SGV.

The capacitive interface is defined by the surfaces of the conductive armature ARM and the first well PW facing each other. Thus, the capacitive interface is formed in particular by the outer surface of the trench which is in contact with the first well PW.

Thus, in the manner visible in FIG. 2A , the entirety of the available space is occupied by capacitive interfaces within frames RGDS each corresponding to the outline of a standard cell CPC with length L_SCR in the respective row RG. In this case, the standard cell is absent and replaced by a capacitive filling structure SCRa.

In fact, the vertical gate structure SGV and thus the capacitive interface advantageously extend in the second direction Y over the entire length of the two rows RG of the capacitive filling structure W_SCR.

In the first direction X, negligible space is used to form a contact with the second well NW on either side of the length L_SCR of the capacitive fill structure SCRa, in order to electrically connect there the metal track M1 of the conductive structure CONDa, thereby The electrical continuity of the second well NW is ensured. This space also allows compatibility with the rules of longitudinal adjacency in the first direction X between adjacent standard cells and capacitive filling structures SCRa.

Furthermore, the vertical gate structure SGV may include a region NS with a second type (N-type) doping implanted in the first well PW at the bottom of the trench before the first well PW is filled with a conductive material. The vertical gate structure SGV may also comprise a further region of doping of the second type (N-type) implanted on the surface of the first well PW (at the front side FA).

These implanted regions of the second type NS that exist due to the method of fabricating the vertical gate structure SGV are advantageously combined with the method of fabricating the non-volatile memory cells (see below in relation to FIGS. 4A-4I ). That is, the injection regions NS, AS provide a source of minority carriers allowing the formation of an inversion channel along the capacitive interface, which allows the capacitive filling structure SCR to operate in NOT mode.

Reference is now made to Figures 3A, 3B and 3C.

3A shows a top view of a second example of a capacitive filling structure SCRb in a plane (X-Y), FIG. 3B shows a cross-sectional view of a capacitive filling structure SCRb in a plane BB (X-Z) of FIG. 3A , and FIG. 3C A cross-sectional view of the capacitive filler structure SCRb on plane CC(Y-Z) of FIG. 3A is shown. The directions X, Y, Z correspond to the orthogonal reference frame shared by Figures 3A, 3B and 3C.

In this example, the conductive structure CONDb is electrically connected to the second well NW on either side of the capacitive filling structure SCRb via a surface semiconductor strip BDN+ of the second type (type N, N+ ) and extends in the first direction X over the length of the capacitive filling structure L_SCR.

Compared with the implantation depth of the transistor conduction region, "surface" means that the implantation depth of the semiconductor strip BDN+ is located on the surface of the first well PW, rather than the depth of wells such as the first well PW or the second well NW.

For example, a surface semiconductor band BDN+ with strong N-type doping can be obtained by implanting an N-type dopant (boron usually used in the substrate) and a first well PW made of silicon with a density of about 5 per cubic centimeter *10 ¹⁵ atoms and 10 ¹⁶ atoms per cubic centimeter.

Advantageously, the surface semiconducting strips BDN+ comprise a metal silicide, allowing the resistivity of the semiconducting strips BDN+ to be reduced.

Furthermore, shallow insulating trenches STI (typically Shallow Trench Insulation) are provided on either side of the surface semiconductor strip BDN+ in the second direction Y to avoid a short circuit to another adjacent region comprising a metal silicide, e.g. The contact CNTSGV of the vertical gate structure SGV.

The conductive armature ARMh, ARMb of this example of the capacitive filling structure SCRb has the same advantageous design as the conductive armature ARM described above in relation to FIGS. 2A-2C . The same elements support the same reference numerals and are not fully described in detail.

That is to say, when the conductive structure CONDb exists in the first well PW, along the first direction X, the conductive armatures ARMh and ARMb of the capacitive filling structure SCRb are divided into two parts, that is, the conductive structure CONDb is in the second The "upper" part ARMh and the "lower" part ARMb on either side of the direction Y.

Thus, each of the parts ARMh, ARMb of the conductive armature may in particular comprise: a vertical gate structure SGV, an implantation region NS, AS, a horizontal gate structure SG.

The conductive structure CONDb passes through the capacitive filling structure SCRb advantageously in the middle of the width of the capacitive filling structure SCRb. Thus, the two parts ARMh, ARMb of the conducting armature may be identical or symmetrical with respect to said intermediate or central point.

In other words, apart from the width of the surface semiconductor strips BDN+, STI, the capacitive interface extends in the second direction Y over the entire width of the two rows of capacitive filling structures W_SCR. The width of the surface semiconductor strip BDN+, STI in the second direction Y is less than 10% of the width W_SCR of the two rows RG of the capacitive filling structure SCRb.

Thus, a quasi-population (eg greater than 60% or even greater than 80%) of the extent of the width W_SCR of the two rows RG of the capacitive filling structure SCRb is dedicated to the capacitive interface.

Reference is now made to FIGS. 4A to 4I which illustrate the results of method steps for manufacturing an integrated circuit CI in the first example SCRa described in FIGS. 2A-2C and in the second example SCRb shown in FIGS. 3A-3C .

The manufacturing method also includes manufacturing non-volatile memory cells NVM comprising vertical gate access transistors and floating gate state transistors, high voltage Transistors, and low-voltage transistors belonging to the low-voltage part LV, such as the logic part LG (Fig. 1).

Therefore, as shown below, all the steps of manufacturing the capacitive filling structures SCRa, SCRb can also be used for manufacturing other components of the integrated circuit CI. In other words, the method for producing the capacitive filling structures SCRa, SCRb can be integrated with existing production methods and can thus be implemented freely.

The individual parts NVM, HV, LV, SCRa, SCRb of the integrated circuit CI are formed from the same semiconductor substrate PSUB, typically silicon with p-type doping.

The capacitive filling structure SCRb corresponding to the example of FIGS. 3A-3C is shown in a pair of YZ planes (similar to FIG. 3C), while the capacitive filling structure SCA corresponding to the example of FIGS. 2A-2C is shown in a In-plane to XZ (similar to Figure 2B). Of course, the manufacturing methods of the two examples mentioned above are shown simultaneously, but in practice only one of the two examples can be performed.

FIG. 4A shows the result of the steps of defining the well PWNVM of the non-volatile memory cell NVM and forming the shallow insulation trench STI.

The formation of shallow isolation trenches STI generally involves etching openings (referred to as trenches) in the substrate PSUB and forming a dielectric material that fills the trenches. Shallow insulation trenches (STIs) are generally present in all parts of integrated circuits and allow to define the contours of the "active area" and ensure lateral electrical isolation between adjacent devices.

The formation of the well of the memory cell PWNVM takes place in particular due to a specific doping with respect to the write voltage involved and due to the implantation of the buried semiconductor layer NISO at a depth in the substrate PSUB that insulates the well PWNVM and forms the memory The source line (or source plane) of the NVM.

Figure 4B shows the result of the step of defining the high-voltage well PW, with a doping of the first type, that is to say a p-type doping implanted at a concentration suitable for the voltages involved in the high-voltage part during operation of the integrated circuit CI agent.

Fig. 4C shows the result of the step of etching trench TR for accommodating vertical gate structures SGV belonging to memory cells NVM (Vertical Gate Buried Access Transistors) and capacitive filling structures SCRa, SCRb. By etching the pattern of the mask, trenches TR are opened in the respective wells PW and PWNVM by dry directional etching of plasma etching type. The depth of trench TR is the same in various parts of integrated circuit CI and the bottom of the trench is at a depth substantially at source plane NISO, slightly above the source plane.

A cladding layer of the gate dielectric is deposited on the sides and bottom of the trench TR, for example by thermal growth of a silicon oxide layer.

Furthermore, a region NS with a second type (N-type) doping is implanted at the bottom of the trench TR. Region NS forms the source region of the vertical gate-buried access transistor of the memory cell, in contact with source plane NISO.

FIG. 4D shows the result of the step of forming the vertical gate structure SGV, including overfilling the trench TR with a conductive material (eg, polysilicon P0). Excess conductive material overflowing from trench TR is removed, for example, by chemical mechanical polishing.

Furthermore, a high voltage oxide layer HVOX is deposited on the entire front side FA of the substrate PSUB and then thinned to a thickness called tunnel thickness TNOX in the non-volatile memory NVM portion.

Figure 4E shows the result of the step of forming the first gate conductive layer P1 (usually made of polysilicon) on the high voltage HVOX and tunnel TNOX oxide layers, and the etching step GR1 (usually dry etching in a mask pattern) As a result, the etching step is usually dry etching in a masked pattern allowing to define the gate area of the high voltage transistor HV and to remove the first gate conductive layer P1 in the areas SCRa, SCRb and LV of the integrated circuit CI.

Figure 4F shows the result of the step of forming a dielectric layer ONO comprising a stack of eg oxide, nitride and silicon oxide layers in the non-volatile memory NVM components and capacitive fill structures SCRa, SCRb.

Then, wells NW with second type (ie N-type) doping are implanted in the part of the integrated circuit containing N-type wells, in particular the second well NW of the logic part LG (FIG. 1) LV. Thus, capacitive filling structures SCRa, SCRb are defined in this step.

A second gate conductive layer P2 generally made of polysilicon is formed on the entire surface of the integrated circuit CI. In the first etching GR2HV, the second gate conductive layer P2 is removed in the high voltage portion HV.

Figure 4G shows the result of the second etching GR2NVM, in the non-volatile memory NVM area, the floating gate is defined by the second gate conductive layer P2, the dielectric stack ONO and the first gate conductive film P1 The floating gate GF and control gate GC regions of the state transistor.

Fig. 4H shows the result of the third etch GR2LV of the second gate conductive layer P2, which defines the gate region of the low voltage transistor LV and the horizontal gate structure SGH of the capacitive filling structures SCRa, SCRb.

FIG. 4I shows the result of the step of implanting strongly doped conductive regions N+, P+ on either side of the gate regions of the above-mentioned high-voltage HV, low-voltage LV transistors and floating gate state transistors.

Furthermore, this implantation step allows forming an n+ contact with the second well NW in the capacitively filled structure SCRa, to electrically connect there via the metal contact pillar CNT the metal track M1 belonging to the conductive structure CONDa, and in the capacitively filled structure SCRb, The strongly doped surface semiconductor strip BDN+ with the second type N+ belongs to the conductive structure CONDb.

Before the formation of the metal contact pillars CNT and the first metal layer, the silicidation method is performed in all parts of the integrated circuit CI, allowing the formation of compounds of metal silicides on the surface of all exposed parts made of silicon, especially the surface semiconductor strips BDN+, also includes transistor conduction regions, well taps, and/or other regions, and gates of transistors made of polysilicon. Metal silicides allow to improve the electrical conductivity of the regions made of silicon, in particular to form ohmic contacts there.

Claims (20)

1. An integrated circuit comprising: a logic section comprising standard cells arranged in parallel rows along a first direction and having a fixed width covering a first semiconductor having a doping of a first type in a second direction perpendicular to the first direction half the width of the well and half the width of a second semiconductor well having a doping of a second type opposite to said first type; wherein each of the first semiconductor well and the second semiconductor well is shared by two adjacent rows; and a capacitive filling structure located between said standard cells and belonging to two adjacent rows, and said capacitive filling structure comprising a capacitive interface between a conductive armature and said first semiconductor well; wherein the extent of the second semiconductor well in the first direction is interrupted over the length of the capacitive fill structure such that the first semiconductor well occupies the capacitive fill structure in the second direction The width of the two adjacent rows of ; and Wherein the capacitive filling structure further includes a conductive structure configured to electrically connect the second semiconductor well on an opposite side of the capacitive filling structure in the first direction. 2. The integrated circuit of claim 1 , wherein said conductive structure comprises at least one metal track located in a level of metal interconnect and at said length relative to said capacitive fill structure. The capacitive interface extends in the first direction and the capacitive interface extends in the second direction over the entire width of the two adjacent rows of the capacitive filling structures. 3. The integrated circuit of claim 1 , wherein the conductive structure comprises a surface semiconductor strip located in the first semiconductor well and over the length of the capacitive fill structure at extending in said first direction, said surface semiconducting strips having a strong doping of said second type, said capacitive interface extending in said second direction in said capacitive filling structure except said surface semiconducting strips The width extends over the entire width of the two adjacent rows. 4. The integrated circuit of claim 3, wherein the surface semiconductor strips comprise metal suicides. 5. The integrated circuit of claim 3, wherein the conductive structure comprises shallow insulating trenches on either side of the surface semiconductor strip extending in the second direction. 6. The integrated circuit of claim 3 , wherein said surface semiconductor strips include said first type of dopant implanted into said first semiconductor well, said first type of dopant having The density is between 10 ¹⁵ atoms/cm3 and 10 ¹⁶ atoms/cm3. 7. The integrated circuit of claim 1, wherein the conductive armature of the capacitive fill structure comprises at least one vertical gate structure extending in depth in the first semiconductor well. 8. The integrated circuit of claim 7, wherein the at least one vertical gate structure comprises: implanting the the region doped with the second type, and implanting the region doped with the second type at the second vertical end of the vertical gate structure located on the surface of the first semiconductor well. 9. The integrated circuit of claim 7, wherein said conductive armature of said capacitive fill structure further comprises at least one horizontal gate structure located in said first semiconductor well on a surface facing the at least one vertical gate structure. 10. The integrated circuit of claim 7, further comprising a non-volatile memory comprising a memory cell provided with a vertical gate buried access transistor and a floating gate state transistor, wherein the The vertical gate structure of the conductive armature is composed of the same material and has the same depth as the vertical gate of the vertical gate buried access transistor. 11. A method for manufacturing an integrated circuit comprising: Manufacture logic components, including: forming alternating portions of first semiconductor wells having doping of a first type and second semiconductor wells having doping of a second type opposite to said first type, said alternating portions extending parallel in length in a first direction ; forming standard cells arranged in parallel rows along the first direction, the standard cells having a fixed width covering the first semiconductor well in a second direction perpendicular to the first direction half the width of a first semiconductor well and half the width of a second one of said second semiconductor wells; wherein each of the first semiconductor well and the second semiconductor well is shared by two adjacent rows; In the middle of said standard cells, capacitive filling structures belonging to two adjacent rows are formed by the following steps: Interrupting the extent of the second semiconductor well in the first direction over the length of the capacitive fill structure, such that the first semiconductor well occupies a portion of the capacitive fill structure in the second direction the width of said two adjacent rows; forming a capacitive interface between the conductive armature and the first semiconductor well; and A conductive structure is formed configured to electrically connect the second semiconductor well on an opposite side of the capacitive fill structure in the first direction. 12. The method of claim 11 , wherein forming the conductive structure comprises forming at least one metal track in a level of metal interconnect and facing the length of the capacitive fill structure at the extending in the first direction, and wherein the capacitive interface extends in the second direction over the entire width of the two adjacent rows of the capacitive fill structures. 13. The method of claim 11, wherein forming the conductive structure comprises forming a surface semiconductor strip in the first semiconductor well, the surface semiconductor strip having a strong doping of the second type, and the a surface semiconducting strip extending in said first direction over said length of said capacitive fill structure, and wherein said capacitive interface is in said second direction for all but the width of said surface semiconducting strip extending over the entire width of the two adjacent rows of the capacitive fill structure. 14. The method of claim 13, wherein forming the conductive structure further comprises forming a silicide of a metal suicide in the surface semiconductor strip. 15. The method of claim 13, wherein the forming of the conductive structure further comprises forming shallow insulating trenches on either side of the surface semiconductor strip extending in the second direction. 16. The method according to claim 13 , wherein forming the surface semiconductor band comprises implanting the first type of dopant in the first semiconductor well, the density of the first type of dopant being between Between 10 ¹⁵ atoms/cubic centimeter and 10 ¹⁶ atoms/cubic centimeter. 17. The method of claim 11, wherein forming the conductive armature comprises forming at least one vertical gate structure extending a depth in the first semiconductor well. 18. The method of claim 17, wherein forming the vertical gate structure comprises: forming trenches etched into the first semiconductor well and covered with a dielectric encapsulation on the bottom and sides; implanting a region with doping of the second type in the first semiconductor well at the bottom of the trench; filling the trench with a conductive material; and A region with the second type of doping adjacent to the trench is implanted on the surface of the first semiconductor well. 19. The method of claim 17, wherein forming the conductive armature of the capacitive fill structure further comprises forming a horizontal armature on a surface of the first semiconductor well facing the at least one vertical gate structure. grid structure. 20. The method of claim 17, further comprising: Fabrication of a non-volatile memory comprising a memory cell provided with a vertical gate buried access transistor and a floating gate state transistor; Wherein, forming the vertical gate structure of the conductive armature and forming the vertical gate of the vertical gate-buried access transistor are performed simultaneously.

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