CN116153972B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and belongs to the technical field of semiconductors. The semiconductor device includes: a semiconductor substrate; the source light doping region and the drain light doping region are arranged in the semiconductor substrate, and the drain light doping region and the source light doping region are arranged at intervals; the gate oxide layer is arranged on the semiconductor substrate and comprises a first subsection and a second subsection, the thickness of the second subsection is larger than that of the first subsection, the first subsection is arranged above the source light doping region and part of the drain light doping region, and the second subsection is arranged above the part of the drain light doping region and close to the source light doping region; the drain electrode heavy doping region is arranged in the drain electrode light doping region at one side of the second partition part far away from the source electrode light doping region, and the interface depth of the drain electrode heavy doping region is smaller than that of the drain electrode light doping region. The semiconductor device and the manufacturing method thereof can improve the performance of the semiconductor device.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention belongs to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). In a lateral double-diffused field effect transistor (LateralDouble-diffused MOSFET, LDMOSFET), increasing the thickness of the oxide layer near the drain will not affect the performance of the field oxide layer isolated from semiconductor components, and can improve the on-resistance or breakdown voltage.

In LDMOSFET, the lightly doped region (Lightly Doped Drain, LDD) on the source side is not set, where the source-drain (Source-Drain, SD) impurity distribution, LDD, channel (Channel), etc. Metal Oxide Semiconductor Field Effect Transistor (Medium Voltage MOSFET, MVMOSFET) is not the same. Therefore, if the structure of the LDMOSFET is applied to the MVMOSFET, the source resistance of the MVMOSFET will increase, resulting in a decrease in the conduction current (Ion). In addition, in MVMOSFET, when the substrate bias is zero, the gate-induced drain leakage current (Gate-Induced-Drain-Leakagecurrent, GIDL) has nothing to do with the overlapping amount of polysilicon and LDD of the gate.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can improve the performance of the semiconductor device without increasing the manufacturing cost.

To achieve the above object and other related objects, the present invention provides a semiconductor device, comprising:

semiconductor substrate;

a lightly doped source region, disposed in the semiconductor substrate;

The lightly doped drain region is arranged in the semiconductor substrate, and the lightly doped drain region and the lightly doped source region are arranged at intervals;

a gate oxide layer disposed on the semiconductor substrate, and the gate oxide layer includes a first subsection and a second subsection, the thickness of the second subsection is greater than the thickness of the first subsection, The first subsection is arranged above the lightly doped source region and part of the lightly doped drain region, the second subsection is arranged above part of the lightly doped drain region, and the second subsection is disposed close to the source lightly doped region; and

The heavily doped drain region is arranged in the lightly doped drain region on the side of the second subsection away from the lightly doped source region, and the interface depth of the heavily doped drain region is less than the The interface depth of the drain lightly doped region.

In an embodiment of the present invention, the semiconductor device further includes a gate, the gate is disposed on the gate oxide layer, and part of the gate is disposed on the second subsection.

In an embodiment of the present invention, an offset portion is provided between the end of the gate close to the heavily doped drain region and the end of the second subsection close to the heavily doped drain region.

In an embodiment of the present invention, an end of the gate close to the heavily doped drain region is aligned with an end of the second subsection close to the heavily doped drain region.

In an embodiment of the present invention, the semiconductor device further includes a gate, the gate is disposed on the gate oxide layer, and part of the gate is disposed on the second subsection and extends to On a transition region between the second subsection and the first subsection on a side close to the heavily doped drain region.

In an embodiment of the present invention, the impurity implanted into the source lightly doped region and the drain lightly doped region is the same, and the implantation doses of the impurities are equal.

The present invention also provides a method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a source lightly doped region in the semiconductor substrate;

A lightly doped drain region is formed in the semiconductor substrate, and the lightly doped drain region and the lightly doped source region are spaced apart;

A gate oxide layer is formed on the semiconductor substrate, and the gate oxide layer includes a first subsection and a second subsection, the thickness of the second subsection is greater than the thickness of the first subsection, so The first subsection is arranged above the lightly doped source region and part of the lightly doped drain region, the second subsection is arranged above part of the lightly doped drain region, and the The second subsection is disposed close to the source lightly doped region; and

A heavily doped drain region is formed in the lightly doped drain region, and the heavily doped drain region is arranged on the lightly doped drain region of the second subsection away from the lightly doped source region. In the doped region, and the implantation energy of the heavily doped drain region is less than that of the lightly doped drain region.

In an embodiment of the present invention, the implantation dose of impurities in the lightly doped source region and the lightly doped drain region is 1×10 ¹³ atoms/cm ² .

In an embodiment of the present invention, the step of forming the lightly doped source region and the lightly doped drain region is before the step of forming the gate oxide layer.

In an embodiment of the present invention, the step of forming the gate oxide layer includes:

Forming a hard mask layer on a semiconductor substrate with a lightly doped drain region;

forming a photoresist layer on the hard mask layer, the photoresist layer exposing part of the hard mask layer on the lightly doped drain region;

Using the photoresist layer as a mask, etching the hard mask layer to the semiconductor substrate to form an opening;

removing the photoresist layer;

forming the second subdivision on the semiconductor substrate within the opening;

removing the hard mask layer; and

The first subsection is formed on the semiconductor substrate other than the second subsection.

In summary, the present invention provides a semiconductor device and a manufacturing method thereof, which can increase the breakdown voltage of the semiconductor device, reduce the gate-induced drain leakage current of the semiconductor device, and improve the reliability of the semiconductor device. At the same time, the resistance of the source region is reduced, and the decrease of the on-current can be suppressed. The potential barrier of the semiconductor device can be enlarged, the number of electrons passing through the potential barrier can be reduced, and the gate-induced drain leakage current can be further suppressed. The volume of the semiconductor device can be reduced without reducing the performance of the semiconductor device. At the same time, in the manufacturing process of the semiconductor device, there is no need to add a new manufacturing process or mask, the difficulty of the production process and the production cost are reduced, and the performance of the semiconductor device can be improved without increasing the manufacturing cost.

Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of drawings

FIG. 1 is a cross-sectional view of a semiconductor device in an embodiment of the present invention.

FIG. 2 is a schematic diagram of a P-well in a semiconductor substrate in an embodiment of the present invention.

FIG. 3 is a schematic diagram of forming a lightly doped region in an embodiment of the present invention.

FIG. 4 is a schematic diagram of openings formed in a hard mask layer according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a second section for forming a gate oxide layer in an embodiment of the present invention.

FIG. 6 is a schematic diagram of a first section for forming a gate oxide layer in an embodiment of the present invention.

FIG. 7 is a schematic diagram of a process of forming a gate in an embodiment of the present invention.

FIG. 8 is a schematic diagram of a gate formed in an embodiment of the present invention.

FIG. 9 is a schematic diagram of a side wall structure in an embodiment of the present invention.

FIG. 10 is a schematic diagram of forming a metal silicide in an embodiment of the present invention.

FIG. 11 is a schematic diagram of forming a contact portion in an embodiment of the present invention.

FIG. 12 is a comparison diagram of potential barriers of semiconductor devices in different implementations in an embodiment of the present invention.

FIG. 13 is a comparison diagram of output characteristics of semiconductor devices in different implementations in an example of the present invention.

FIG. 14 is a comparison diagram of potential barriers of semiconductor devices in different implementations in an embodiment of the present invention.

FIG. 15 is a cross-sectional view of a semiconductor device in another embodiment of the present invention.

FIG. 16 is a cross-sectional view of a semiconductor device in another embodiment of the present invention.

Label description:

1. Semiconductor device; 2. Semiconductor substrate; 3. Source lightly doped region; 4. Drain lightly doped region; 5. Source heavily doped region; 6. Drain heavily doped region; 7. Gate Polar oxide layer; 8, the first division; 9, the second division.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

In the present invention, it should be noted that if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. , the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, in order to Specific orientation configurations and operations, therefore, are not to be construed as limitations on the application. In addition, the terms "first" and "second" are used for description and distinction purposes only, and should not be understood as indicating or implying relative importance.

Please refer to FIG. 1 , in an embodiment of the present invention, a cross-sectional view of a device structure of a semiconductor device such as a Medium Voltage MOSFET (MVMOSFET) is provided. In this embodiment, as shown in FIG. 1 , the thickness direction of the semiconductor substrate 2 is defined as a thickness direction X, and the direction perpendicular to the thickness direction X is referred to as a width direction Y. In addition, the semiconductor devices shown in FIG. 1 are continuously formed within a predetermined range in the depth directions perpendicular to the thickness direction X and the width direction Y, respectively, and descriptions of other devices are omitted here. In addition, in the following description, specific examples are given regarding the thickness and width, but are not limited to this specific example. within the allowable range.

Please refer to FIG. 1 , in an embodiment of the present invention, the semiconductor device 1 is, for example, an MV MOSFET. Wherein, the semiconductor device 1 includes a semiconductor substrate 2, a P well, a shallow trench isolation STI (not shown in the figure), a lightly doped source region 3, a lightly doped drain region 4, a heavily doped source region 5, Drain heavily doped region 6 , gate oxide layer 7 and gate G. Among them, in the semiconductor substrate 2, a P well (Pwell) is formed by implanting P-type impurities, and the ion doping type of the source lightly doped region 3 and the drain lightly doped region 4 is, for example, N-type, forming an N-type In the lightly doped region (Negative Lightly Doped Drain, NLDD), the ion doping type of the heavily doped source region 5 and the heavily doped drain region 6 is, for example, N-type, forming an N-type heavily doped region as the source of the semiconductor device Pole and drain, denoted as Negative Source Drain (NSD). Wherein, the gate oxide layer 7 includes a first subsection 8 and a second subsection 9 , and the thickness of the first subsection 8 is smaller than the thickness of the second subsection 9 .

Please refer to FIG. 1 , in an embodiment of the present invention, the semiconductor device 1 is, for example, an MVMOSFET, and the MVMOSFET is described using MVNMOS as an example. In other embodiments, other MOS structures can also be selected. In this embodiment, the MVNMOS is, for example, a MOSFET with an operating voltage of 2.5V-8V.

Please refer to FIG. 1 , in an embodiment of the present invention, the semiconductor substrate 2 is, for example, a silicon substrate, and a P well and a shallow trench isolation (STI) are formed in the semiconductor substrate 2 (not shown in the figure). Among them, the P well is a region with P-type polarity formed by implanting P-type impurities such as boron (B) into the semiconductor substrate 2, and the shallow trench isolation STI is used to isolate the gap between the regions in the semiconductor substrate 2. structure. Shallow trench isolation (STI) is formed by forming a trench at a preset position and filling the trench with silicon oxide. The shallow trench isolation (STI) is made of insulating material, so it electrically isolates the regions formed on the surface of the semiconductor substrate 2 .

Please refer to FIG. 1. In one embodiment of the present invention, the source lightly doped region 3 is formed on the semiconductor substrate 2 by implanting N-type impurities such as arsenic (As) or phosphorus (P). Low concentration area in bottom 2. As a low-concentration region is formed in the semiconductor substrate 2, the depletion layer in the P well expands, thereby reducing the surface electric field intensity. Wherein, the source lightly doped region 3 is located below the first subsection 8 in the thickness direction X, that is, below the first subsection 8 of the source region, and the source lightly doped region 3 and the first subsection 8 The lower surface is snugly set.

Please refer to FIG. 1. In one embodiment of the present invention, the lightly doped drain region 4 is formed in the semiconductor substrate 2 by implanting N-type impurities such as arsenic or phosphorus into the semiconductor substrate 2. area. As a low-concentration region is formed in the semiconductor substrate 2, the depletion layer in the P well below the gate G expands, thereby reducing the surface electric field intensity. In addition, the lightly doped drain region 4 is located below the second subsection 9 and the first subsection 8 away from the lightly doped source region 3 in the thickness direction X, and the lightly doped drain region 4 and the second subsection 9 and the lower surface of the first subsection 8 are arranged in close contact.

Referring to FIG. 1 , in one embodiment of the present invention, the source heavily doped region 5 is formed by implanting impurities into the region where the source of the transistor is disposed. Wherein, the heavily doped source region 5 is, for example, made of polysilicon or the like, which is used to form the source region of the transistor. In addition, the interface depth of the heavily doped source region 5 is smaller than the interface depth of the lightly doped source region 3 .

Referring to FIG. 1 , in one embodiment of the present invention, the heavily doped drain region 6 is formed by implanting impurities into the region where the drain of the transistor is disposed. Wherein, the heavily doped drain region 6 is, for example, made of polysilicon or the like, and is used to form a drain region of the transistor. In addition, the interface depth of the heavily doped drain region 6 is smaller than the interface depth of the lightly doped drain region 4 . In this embodiment, the heavily doped source region 5 and the heavily doped drain region 6 are implanted with N-type impurities such as arsenic or phosphorus.

Referring to FIG. 1 , in an embodiment of the present invention, a gate oxide layer 7 is disposed on the surface of a semiconductor substrate 2 , and the gate oxide layer 7 includes a first subsection 8 and a second subsection 9 . Wherein, the first subsection 8 is located on the semiconductor substrate 2 in the source region and part of the drain region, and the thickness of the first subsection 8 is, for example, 14 nm. The second subsection 9 is located on the semiconductor substrate 2 close to the drain, and the thickness of the second subsection 9 is, for example, 120 nm, and the width of the second subsection 9 is, for example, 200 nm˜300 nm. By increasing the thickness of the gate oxide layer 7 near the drain, the breakdown voltage of the semiconductor device 1 can be increased, the gate-induced drain leakage current of the semiconductor device can be reduced, and the reliability of the semiconductor device can be improved.

Please refer to FIG. 1, in one embodiment of the present invention, the source lightly doped region 3 and the drain lightly doped region 4 are selected to implant N-type impurities with the same impurity type and implantation dose, which can effectively improve the performance of the semiconductor device 1. Breakdown voltage, reducing gate-induced drain leakage current of semiconductor devices.

Please refer to FIG. 1 , in an embodiment of the present invention, the gate G is made of, for example, polysilicon (Poly), and the gate G is formed on the gate oxide layer 7 , and the film thickness of the gate G is, for example, 200 nm. In other embodiments, the gate G is, for example, a high dielectric constant insulating film/metal gate (metal gate/high-k, MGHK) structure. Wherein, in the width direction Y, the gate G and the source lightly doped region 3 and the gate G and the drain lightly doped region 4 have an overlapping region Overlap, and the size of the overlapping region Overlap is equal to the length in the width direction Y , and the length of the overlapping region Overlap is, for example, 200 nm.

Referring to FIG. 2 to FIG. 11 , in an embodiment of the present invention, a manufacturing process of a semiconductor device is also provided, for example, taking the manufacturing of MV MOSFET as an example for illustration.

Please refer to FIG. 2 , in an embodiment of the present invention, in step S10 , a shallow trench isolation (STI) is formed in the semiconductor substrate 2 , and the shallow trench isolation STI is used to isolate various regions. Specifically, trenches are first formed at predetermined positions on the semiconductor substrate 2 , and insulating materials such as silicon oxide are deposited in the trenches for electrical isolation of regions of the semiconductor substrate 2 . Then, P-type impurities such as boron are implanted into the semiconductor substrate 2 to form a P-well in the semiconductor substrate 2 . After the shallow trench isolation (STI) is formed, there is a sacrificial oxide layer on the surface of the semiconductor substrate 2 , which can prevent damage to the semiconductor substrate 2 during implantation of the P well and the lightly doped region.

Please refer to FIG. 3 , in an embodiment of the present invention, in step S12 , a lightly doped source region 3 and a lightly doped drain region 4 are formed in the P well. Specifically, the first photoresist layer PR1 is formed on the semiconductor substrate 2, and the first photoresist layer PR1 exposes the region where the source lightly doped region 3 and the drain lightly doped region 4 are formed. In different embodiments, the source The regions of the very lightly doped region 3 and the drain lightly doped region 4 are selected according to the designed semiconductor device. Using the first photoresist layer PR1 as a mask, impurities are implanted into the P well to form a lightly doped source region 3 and a lightly doped drain region 4 . Wherein, the impurities are, for example, N-type impurities such as phosphorus, and the implantation dose of the impurities is, for example, 1×10 ¹³ atoms/cm ² . By implanting the same type and the same amount of ions in the source lightly doped region 3 and the drain lightly doped region 4, the number of masks can not be increased in the manufacturing process, the production process difficulty and production cost can be reduced, and the source electrode can be reduced. The resistance of the area can suppress the decrease of the conduction current (Ion).

1, 3 and 4, in one embodiment of the present invention, in step S14, after the lightly doped source region 3 and the lightly doped drain region 4 are formed, the first photoresist is removed layer PR1 and a sacrificial oxide layer on the semiconductor substrate 2 . A hard mask layer SiN is formed on the semiconductor substrate 2 . The hard mask layer SiN is formed by methods such as chemical vapor deposition (Chemical Vapor Deposition, CVD), and the thickness of the hard mask layer SiN is, for example, 70 nm to 200 nm. After the hard mask layer SiN is formed, a second photoresist layer PR2 is formed on the hard mask layer SiN, and the second photoresist layer PR2 covers the area where the second subsection 9 is formed. Using the second photoresist layer PR2 as a mask, the hard mask layer SiN is etched to the semiconductor substrate 2 to form an opening for forming the second subsection 9 . Wherein, the method of etching the SiN hard mask layer is, for example, dry etching, and the dry etching method is, for example, using high radio frequency (Radio Frequency, RF) discharge for etching.

Referring to FIG. 4 to FIG. 5 , in an embodiment of the present invention, in step S16 , after the opening is formed, the second photoresist layer PR2 is removed, for example, by cleaning with a chemical reagent. A second subsection 9 is then formed in the opening, wherein the second subsection 9 is formed, for example, by thermal oxidation, such as any one of dry oxidation, wet oxidation and steam oxidation in thermal oxidation. In this embodiment, the thickness of the second subsection 9 is, for example, 120 nm.

Referring to FIG. 5 to FIG. 6 , in an embodiment of the present invention, in step S18 , after the second subsection 9 is formed, the hard mask layer SiN on the semiconductor substrate 2 is removed. Wherein, the hard mask layer SiN is removed by, for example, wet etching, and the wet etching solution is, for example, a phosphoric acid (H ₃ PO ₄ )-based solution. After removing the hard mask layer SiN, a first subsection 8 is formed on the semiconductor substrate 2 other than the second subsection 9 by thermal oxidation, wherein the thickness of the first subsection 8 is, for example, 14 nm. Gate oxide layers with different thicknesses are formed on the semiconductor substrate 2 through two thermal oxidation processes, wherein a thicker second subsection 9 is formed on a part of the area close to the drain, and a thicker second subsection 9 is formed on the area on the source side and Thinner first subsections 8 are formed on the remaining areas. In the present invention, when forming the gate oxide layer, the LDD region has already been formed in the substrate, that is, the forming step of the LDD region is a step before the forming step of the gate oxide layer. Therefore, when forming the gate electrode, the penetration phenomenon caused by the ion implantation of polysilicon can be avoided, and a deep LDD region can be formed, that is, the gate-induced drain leakage current of the semiconductor device can be suppressed through the improvement of the manufacturing process.

7 to 8, in an embodiment of the present invention, in step S20, after the first subsection 8 is formed, a polysilicon layer (Poly) is formed on the semiconductor substrate 2, and the polysilicon layer (Poly) is formed, for example, by chemical Formed by methods such as vapor deposition, and the thickness of the polysilicon layer is, for example, 200 nm. A patterned photoresist layer is formed on the polysilicon layer, and the patterned photoresist layer covers the polysilicon layer for forming the gate G. Then, etching is used to remove the polysilicon layer in the remaining area. In this embodiment, for example, the polysilicon layer is removed by dry etching to form the gate G, and then the patterned photoresist layer is removed. Wherein, the gate G on the drain region covers part of the second subsection 9 and covers the channel of the semiconductor device.

Please refer to FIG. 9 , in one embodiment of the present invention, in step S24 , after forming the gate G, a dielectric film layer (not shown) is formed on the semiconductor substrate 2 and the gate G. After removing the dielectric film layer on the semiconductor substrate 2 and the gate G by etching, such as reactive ion etching (Reaction Ion Etching, RIE), the dielectric film layer on both sides of the gate G is retained to form the side wall structure SW . Wherein, the sidewall structure SW in the source side region is formed on the first subsection 8 , and the sidewall structure SW in the source side region is formed on the second subsection 9 .

Please refer to FIG. 9, in one embodiment of the present invention, in step S24, N-type impurities such as phosphorus are implanted into the lightly doped source region 3 and the lightly doped drain region 4 to form an N-type source Extremely heavily doped region 5 and drain heavily doped region 6 . Wherein, in the drain region, the gate G is arranged on a part of the second subsection 9 of the gate oxide layer, and there is a preset distance from the gate G to the edge of the second subsection 9, therefore, the heavily doped drain region There is a preset distance between 6 and the grid G, and the preset distance is defined as an offset part OS (Offset). When forming the source heavily doped region 5 and the drain heavily doped region 6, the impurity implantation energy is less than the implantation energy when forming the source lightly doped region 3 and the drain lightly doped region 4, therefore, the source is heavily doped The depth of the impurity region 5 and the heavily doped drain region 6 in the semiconductor substrate 2 is smaller than the depth of the lightly doped source region 3 and the lightly doped drain region 4, that is, the interface depth of the heavily doped region is less than that of the lightly doped region. The interface depth of the zone. And because the thickness of the second subsection 9 is relatively large, when the heavily doped drain region 6 is formed, N-type impurities will not be implanted into the lightly doped drain region 4 under the second subsection 9 . That is, by setting the offset part OS, it is possible to suppress the diffusion of impurities from the heavily doped drain region 6 to the lightly doped drain region 4 to the region below the gate G, thereby preventing the lightly doped drain region 4 below the gate G from In the case where the impurity concentration is too high, the GIDL of the semiconductor device can be suppressed.

Please refer to FIG. 9 , in an embodiment of the present invention, when forming the heavily doped region, the depth of the heavily doped region is smaller than the depth of the lightly doped region, which can be controlled according to the implantation energy. In one embodiment of the present invention, when the semiconductor device is a P-type device, the implantation energy is, for example, 20KeV, and the implanted ions are, for example, boron and other P-type impurities to form the LDD region, and then the implantation energy is, for example, 6KeV to implant boron and other P Type impurities form heavily doped regions. In one embodiment of the present invention, when the semiconductor device is an N-type device, the implanted ions are, for example, N-type impurities such as phosphorus to form an LDD region with an implantation energy of, for example, 70KeV, and then implanted with an implantation energy of, for example, 30KeV to implant N-type impurities such as phosphorus. Impurities form heavily doped regions. That is, in the present invention, according to different types of semiconductor devices to be formed, different implantation energies are selected for the lightly doped region and the heavily doped region, so that GIDL can be more effectively suppressed.

Please refer to FIG. 10 , in one embodiment of the present invention, in step S26, after the heavily doped source region 5 and the heavily doped drain region 6 are formed, a metal layer is formed on the semiconductor substrate 2 (not shown in the figure), for example, a metal nickel layer is formed, and the metal layer is formed by methods such as sputtering or physical vapor deposition (Physical Vapor Deposition, PVD). After the metal layer is formed, the semiconductor substrate 2 is annealed, and the metal nickel reacts with silicon in the semiconductor substrate 2 or the gate G to produce nickel silicide (NiSi). After the reaction is completed, the unreacted metal layer on the oxide layer is removed, for example, by cleaning with a chemical reagent. In other embodiments, the nickel silicide can be replaced by other metal silicides, and the silicide production process can also be selected for preparation.

Please refer to FIG. 10 to FIG. 11 , in an embodiment of the present invention, in step S28 , after forming nickel silicide, an interlayer insulating layer is formed on the conductive layer, electrode or wiring of the semiconductor device 1 . Then etching, such as dry etching, is used to etch the interlayer insulating layer to form contact holes for connecting the electrodes of the source S, the drain D and the gate G. Fill the contact hole with metal such as tungsten (W) to form a contact part, and lay metal wiring on the surface of the contact part to connect the electrodes of the source S, drain D and gate G.

Please refer to FIG. 1 and FIG. 12 , in an embodiment of the present invention, a comparative diagram of potential barriers of MVMOSFETs prepared in different embodiments is provided. Among them, the horizontal axis represents the electric field strength (G-D) between the gate G and the drain D in the thickness direction X, and the vertical axis represents the electric field strength (S-D) between the source S and the drain D in the width direction Y. Wherein, embodiment a represents the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band in the MOSFET device with the shallower LDD region, and embodiment b represents the electric field strength Ec and the valence band of the conduction band in the MOSFET device with the darker LDD region The electric field strength Ev of the embodiment c represents the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band in the MOSFET device with a deeper LDD region and a thicker second subsection 9 in the gate oxide layer 7 . In addition, in Fig. 12, the solid line, dotted line, and dotted line close to the horizontal axis X in the direction of the vertical axis Y represent the electric field intensity Ev of the valence band in different embodiments, respectively, and the solid line far away from the horizontal axis X in the direction of the vertical axis Y Lines, dotted lines, and dashed lines represent the electric field strength Ec of the conduction band, respectively.

Please refer to FIG. 12 , in an embodiment of the present invention, the area sandwiched between the electric field intensity Ec of the conduction band and the electric field intensity Ev of the valence band represents a potential barrier. According to the lines in the figure, compare the MVMOSFET barriers provided in different embodiments. It can be seen from FIG. 12 that the potential barrier of the semiconductor device gradually expands from embodiment a to embodiment c. That is, since the LDD region in the MVMOSFET is formed deeper than the gate oxide layer, the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band in the X-axis direction decrease near the gate oxide layer. , the barrier expands. In addition, since the LDD region in the MVMOSFET is formed deeper than the gate oxide layer, an electric field can also be generated at a position deeper than the gate oxide layer, that is, on the right side of the X-axis direction in Figure 12, forming a potential barrier . In this way, since the potential barrier is expanded, the number of electrons passing through the potential barrier is reduced, and the gate-induced drain leakage current can be further suppressed.

Please refer to FIG. 12 , in an embodiment of the present invention, the implementation b is compared with the implementation c, and the potential barrier of the implementation c is further enlarged. Since in embodiment b and embodiment c, the LDD region in the MVMOSFET is formed deeper relative to the gate oxide layer, but in embodiment c the gate oxide layer has a thicker second subdivision, so in the gate oxide In the vicinity of the layer, the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band further decrease in the X-axis direction, and the potential barrier expands. In this way, since the potential barrier is expanded, the number of electrons passing through the potential barrier is reduced, and the gate-induced drain leakage current can be further suppressed.

Please refer to FIG. 13 , in an embodiment of the present invention, a comparison chart of output characteristics of MV MOSFETs prepared in different implementations is provided. The horizontal axis in FIG. 13 represents the gate voltage Vg, and the vertical axis represents the drain current Id. In FIG. 13 , the dotted line indicates the GIDL of embodiment b, and the solid line indicates the GIDL of embodiment c. Here, the minimum value of the drain current Id indicated by the different lines is the evaluation value of the GIDL of the MOSFET.

Please refer to FIG. 13, in an embodiment of the present invention, compared with the GIDL of the MOSFET in which the LDD region is formed deeper than the gate oxide layer in the embodiment b, in the embodiment c, the LDD region is formed deeper than the gate oxide layer. For MOSFETs where the pole oxide is formed deeper and has a thicker second subdivision at the gate oxide, the GIDL of embodiment c is lower than the GIDL of embodiment b by an amount such as 2.5 orders of magnitude. That is, by forming a thicker second subdivision in the gate oxide film, the GIDL of the obtained MOSFET is improved. That is, the present invention can suppress GIDL by increasing the potential barrier of the semiconductor device by changing the structure of the MOSFET.

Please refer to FIG. 14 , in an embodiment of the present invention, a comparative diagram of potential barriers of MV MOSFETs prepared in different embodiments is provided. Among them, the horizontal axis represents the electric field strength (G-D) between the gate G and the drain D in the thickness direction X, and the vertical axis represents the electric field strength (S-D) between the source S and the drain D in the width direction Y. Among them, the solid line represents the electric field intensity Ec of the conduction band and the electric field intensity Ev of the valence band of the MVMOSFET in embodiment c, and embodiment c is that the LDD region is formed deeper than the gate oxide layer and the gate oxide layer has a thicker of the second division. The dotted line represents the electric field intensity Ec of the conduction band and the electric field intensity Ev of the valence band of the MVMOSFET in embodiment d, and embodiment d is that the LDD region is formed deeper than the gate oxide layer and the gate oxide layer has a thicker second The MVMOSFET is subdivided, and an offset part OS is provided between the end of the heavily doped drain region and the end of the gate electrode G close to the drain.

Please refer to FIG. 14 , in an embodiment of the present invention, in implementation d, the end of the heavily doped drain region is offset from the LDD region close to the drain, so that The drain lightly doped region below the gate produces a reduced amount of diffused impurities. Accordingly, in the vicinity of the gate oxide layer, the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band in the X-axis direction are further reduced, and the potential barrier is enlarged. That is, the GIDL of the MOSFET can also be suppressed by providing the offset portion OS between the end of the heavily doped drain region and the end of the gate near the drain.

Please refer to FIG. 1 and FIG. 15 , in another embodiment of the present invention, the present invention also provides a cross-sectional view of another MVMOSFET 11 structure. Compared with the semiconductor device 1 , in the MVMOSFET 11 , in the MVMOSFET 11 , the end of the heavily doped drain region 6 is aligned with the sidewall structure, and no offset is provided. The end of the grid G is located on the "Bird's" of the thicker second subsection 9, which is the double-dotted dash circle in the figure, and the "bird's beak" is also the second subsection 9 and The transition area of the first subdivision 8. And in the manufacturing process of MVMOSFET11, except that in the above-mentioned steps S14 and S16, the photoresist layer formed and the position of the second subsection 9 are different, the manufacturing process of MVMOSFET11 in this embodiment is the same as the manufacturing process of semiconductor device 1 same.

1 and 15, in an embodiment of the present invention, in the MVMOSFET 11, no bias is provided between the end of the heavily doped drain region 6 and the end of the gate G close to the drain side. As a result, the dimension of the MVMOSFET 11 in the width direction Y is shortened, and the size of the semiconductor device can be reduced. In addition, the manufacturing process of the MV MOSFET 11 in this embodiment is the same as that of the semiconductor device 1 except that the position of the polysilicon formed in the above-mentioned step S20 is different. By disposing the gate G on the gate oxide layer, and the end of the gate G near the drain side is located on the bird's beak of the second subsection 9, passing between the gate G and the heavily doped drain region 6 Without providing the offset portion, the GIDL of the semiconductor device can be suppressed while reducing the size of the semiconductor device.

Please refer to FIG. 1 and FIG. 16 , in another embodiment of the present invention, the present invention also provides a cross-sectional view of another MVMOSFET 21 structure. In this embodiment, the thicker second subsection 9 is formed by chemical vapor deposition, and the end of the gate G near the drain is aligned with the end of the second subsection 9 near the drain. In the manufacturing process of the MV MOSFET 21 , the manufacturing process of the MV MOSFET 21 in this embodiment is the same as that of the semiconductor device 1 except that the method of forming the second subsection 9 in the above-mentioned step S16 is chemical vapor deposition. Among them, the thermal oxidation method heat-treats the semiconductor substrate by using a high-temperature process to form a gate oxide layer, thus forming a "bird's beak" at both ends of the second subsection. Unlike the thermal oxidation method, the chemical vapor deposition method does not form a "bird's beak" at both ends of the second subsection, and can precisely control the shapes of the first subsection and the second subsection when the gate oxide layer is formed.

Please refer to FIG. 16 , in an embodiment of the present invention, when the second subsection 9 is formed by chemical vapor deposition, no new mask is needed, the manufacturing cost does not increase, and a MOSFET with improved GIDL performance can be obtained. And in the manufacturing process, before the gate oxide layer is formed by chemical vapor deposition, the semiconductor substrate is first sacrificially oxidized, and the damaged layer or contamination on the surface of the semiconductor substrate is removed, and then the gate oxide layer is formed. , a gate oxide layer with higher uniformity can be obtained.

Please refer to FIG. 1, FIG. 12 and FIG. 16, in one embodiment of the present invention, in the semiconductor device, the thickness of the gate oxide layer 7 on the side near the drain is greater than the thickness on the side near the source, that is, on the side near the source A thicker second subsection 9 is formed on the drain side. Wherein, the contact between the lightly doped drain region 4 and the lower surface of the second subsection 9 is provided. The lightly doped source region 3 is located on the lower surface of the first subsection 8 , and the lightly doped source region 3 and the lightly doped drain region 4 are arranged at intervals in the width direction Y. The heavily doped drain region 6 is formed in the lightly doped drain region away from the second subsection 9 , and the depth of the heavily doped drain region 6 is smaller than that of the lightly doped drain region 4 . Therefore, near the gate oxide layer, the potential barrier expands, and the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band decrease in each direction, so that the obtained MVMOSFET can suppress GIDL. And the manufacturing process is the same as the MOSFET manufacturing process, without adding a new manufacturing process or mask. The performance of the semiconductor device can be improved without increasing the manufacturing cost.

To sum up, the semiconductor device has a MOSFET structure, and the manufacturing method of the semiconductor device includes: a gate oxide layer forming process for forming a second subsection of the gate oxide layer in the drain region that is thicker than the source region. The lightly doped region forming process, the source lightly doped region and the drain lightly doped region are arranged at intervals, and the drain lightly doped region is formed under the second subsection, and the source lightly doped region is formed on the gate oxide layer below. The heavily doped region forming process, the heavily doped drain region is formed on the lightly doped drain region on the outside of the second subsection near the drain side, and the implantation energy of the heavily doped drain region is lower than that of the lightly doped drain region Implantation energy in the impurity region. The formed semiconductor device includes: a gate oxide layer, the thickness of the second subsection on the drain side is greater than the thickness of the first subsection on the source side. The lightly doped drain region is located on the lower surface of the second subsection, and the lightly doped source region is located on the lower surface of the second subsection, and is spaced apart from the lightly doped drain region in the width direction. The heavily doped drain region is formed away from the end of the second subsection. Since the impurity implantation energy of the heavily doped drain region is less than the impurity implantation energy of the lightly doped drain region, the interface depth of the heavily doped drain region is smaller than that of the drain The interface depth of the very lightly doped region. In addition, in the semiconductor device, the potential barrier expands near the gate oxide layer, and the electric field strength Ec of the conduction band and the electric field strength Ev of the valence band are small in each direction, so GIDL of the semiconductor device can be suppressed. At the same time, there is no need to add a new manufacturing process or mask in the manufacturing process of the semiconductor device. Therefore, it is possible to improve the performance of the semiconductor device without increasing the manufacturing cost.

Reference throughout this specification to "one embodiment," "an embodiment" or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment includes In at least one embodiment of the invention, and not necessarily in all embodiments. Thus, the various appearances of the phrases "in one embodiment", "in an embodiment" or "in a specific embodiment" at various places throughout the specification Not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics of any particular embodiment of the invention may be combined in any suitable manner with one or more other embodiments. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the invention.

The embodiments of the present invention disclosed above are only used to help explain the present invention. The examples do not exhaust all details nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the contents of this specification. This description selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The invention is to be limited only by the claims, along with their full scope and equivalents.

Claims (8)

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a source light doping region in the semiconductor substrate;

forming a drain light doping region in the semiconductor substrate, wherein the drain light doping region and the source light doping region are arranged at intervals;

forming a gate oxide layer on the semiconductor substrate, wherein the gate oxide layer comprises a first subsection and a second subsection, the thickness of the second subsection is larger than that of the first subsection, the first subsection is arranged above the source light doping region and part of the drain light doping region, the second subsection is arranged above part of the drain light doping region, and the second subsection is arranged close to the source light doping region; and

forming a drain heavy doping region in the drain light doping region, wherein the drain heavy doping region is arranged in the drain light doping region at one side of the second partition part far away from the source light doping region, and the implantation energy of the drain heavy doping region is smaller than that of the drain light doping region;

the forming step of the gate oxide layer comprises the following steps:

forming a hard mask layer on the semiconductor substrate with the drain lightly doped region;

forming a photoresist layer on the hard mask layer, wherein the photoresist layer exposes part of the hard mask layer on the drain light doped region;

etching the hard mask layer to the semiconductor substrate by taking the photoresist layer as a mask to form an opening;

removing the photoresist layer;

forming a second part on the semiconductor substrate in the opening, wherein the thickness of the second part is 120nm, and the width of the second part is 200-300 nm;

removing the hard mask layer; and

the first branch is formed on the semiconductor substrate except the second branch.

2. The method according to claim 1, wherein the semiconductor device further comprises a gate electrode, wherein the gate electrode is provided over the gate oxide layer, and wherein a portion of the gate electrode is provided over the second portion.

3. The method according to claim 2, wherein an offset portion is provided between the gate electrode and the second portion at an end of the gate electrode adjacent to the drain heavily doped region.

4. The method of manufacturing a semiconductor device according to claim 2, wherein an end of the gate adjacent to the drain heavily doped region is aligned with an end of the second partition adjacent to the drain heavily doped region.

5. The method of manufacturing a semiconductor device according to claim 1, further comprising a gate electrode provided on the gate oxide layer, wherein a portion of the gate electrode is provided on the second portion and extends to a transition region between the second portion and the first portion near the side of the drain heavily doped region.

6. The method according to claim 1, wherein the source lightly doped region and the drain lightly doped region are the same in the kind of impurity implanted therein, and wherein the impurity implantation doses are the same.

7. The method for manufacturing a semiconductor device according to claim 1, wherein an implantation dose of impurities in the source light-doped region and the drain light-doped region is 1×10 ¹³ atoms/cm ² 。

8. The method according to claim 1, wherein the step of forming the source lightly doped region and the drain lightly doped region is before the step of forming the gate oxide layer.

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