CN110120346B - LDMOS transistor and manufacturing method thereof - Google Patents

Abstract

The present invention provides an LDMOS transistor and a manufacturing method thereof, wherein a shielding trench with an upper width and a lower width is formed in the shielding insulating layer between the gate structure and the drain region, and the distance from the gate structure can be increased by the shielding trench. The average thickness of the shielding insulating layer on the side of the gate reduces the electric field strength under the metal layer, and at the same time makes the electric field under the metal layer more uniformly distributed, and is conducive to suppressing the hot carrier injection effect at the edge of the gate structure, so as to achieve Higher breakdown voltage and lower on-resistance ultimately improve device performance.

Description

LDMOS transistor and its manufacturing method

technical field

The present invention relates to the technical field of integrated circuit manufacturing, in particular to an LDMOS transistor and a manufacturing method thereof.

Background technique

Lateral double diffused MOS transistor (LDMOS, lateral double diffused MOS transistor) has good linearity, high gain, high withstand voltage, high output power, good thermal stability, high efficiency, good broadband matching performance, easy to integrate with MOS process, etc. Advantages, and its price is much lower than GaAs device, is a very competitive power device, is widely used in GSM, PCS, W-CDMA base station power amplifier, as well as wireless broadcasting and nuclear magnetic resonance and so on. The breakdown voltage BV and the on-resistance Rdson of the LDMOS device are two important parameters used to measure the performance of the device. A higher breakdown voltage helps to ensure the stability of the device during actual operation. For example, an LDMOS device with an operating voltage of 50V needs to have a breakdown voltage of more than 110V. The on-resistance Rdson directly affects the output power and gain of the device.

Therefore, there is a need for a new LDMOS transistor and a method for fabricating the same, which can have higher breakdown voltage and lower on-resistance.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an LDMOS transistor and a manufacturing method thereof, which can have higher breakdown voltage and lower on-resistance.

In order to achieve the above purpose, the present invention provides an LDMOS transistor, comprising:

semiconductor substrate;

a well region and a drift region with different doping types, the well region and the drift region are laterally distributed in the semiconductor substrate and separated by a first lateral distance, an active region is formed in the well region, and a drain region is formed in the drift region Area;

a gate structure located on the surface of the semiconductor substrate and spanning the edge of the well region and the edge of the drift region, the source region and the drain region flanking the gate structure;

a shielding insulating layer covering the top of the gate structure and extending to part of the surface of the drift region, the shielding insulating layer exposing the drain region, and covering between the drain region and the gate structure A shielding trench with an upper width and a lower width is formed in the shielding insulating layer on the surface of the drift region, and the shielding trench does not penetrate the shielding insulating layer;

a metal layer covering the source region and the surface of the shielding insulating layer.

Optionally, the LDMOS transistor further includes a body connection region with a doping type different from that of the source region, the body connection region and the source region are laterally distributed in the well region and separated by a second lateral distance.

Optionally, a field oxygen isolation structure is provided between the body connection region and the source region, so that the body connection region and the source region are separated by another lateral distance.

Optionally, there is no field oxygen isolation structure between the drain region and the gate structure.

Optionally, the metal layer covers one end of the surface of the shielding insulating layer, covers the edge of the shielding trench close to the drain region, or covers the shielding insulating layer close to the drain on the edge of the area.

Optionally, the material of the shielding insulating layer includes at least one of silicon oxide, silicon nitride and silicon oxynitride.

Optionally, the gate structure includes a gate dielectric layer and a gate electrode layer sequentially stacked on the surface of the semiconductor substrate, and a spacer covering the sidewalls of the gate dielectric layer and the gate electrode layer, the The thickness of the shielding insulating layer at the bottom of the shielding trench is greater than or equal to the thickness of the gate dielectric layer.

Optionally, the shape of the shielding trench in the film stacking direction is a right-angled trapezoid that is wide at the top and narrow at the bottom, and the right angle of the right-angled trapezoid is located on the side close to the gate structure; or, the shielding trench is The shape of the film layer stacking direction is a fan shape; or, the shape of the shielding trench in the film layer stacking direction is a polygon with a right angle, and the side of the polygon close to the gate structure is a right angle side, away from all One side of the gate structure is a continuous arc line segment or a polygonal side formed by connecting a plurality of line segments with gradually increasing slopes in sequence.

Optionally, the acute angle of the right-angled trapezoid is 45°˜70°.

The present invention also provides a method for manufacturing an LDMOS transistor, comprising the following steps:

A semiconductor substrate is provided, in which a well region and a drift region of different doping types are formed, the well region and the drift region are laterally distributed in the semiconductor substrate and separated by a first lateral distance, the semiconductor substrate A gate structure spanning the edge of the well region and the edge of the drift region is formed on the surface of the bottom;

forming a shielding insulating layer with a shielding trench that is wide at the top and narrow at the bottom on the surfaces of the semiconductor substrate and the gate structure, and the shielding trench does not penetrate the shielding insulating layer;

etching the shielding insulating layer to at least form a source contact hole exposing a part of the surface of the well region;

A metal layer is formed on the surface of the source contact hole and the remaining shielding insulating layer.

Optionally, the process of forming a shielding insulating layer with shielding trenches that are wide at the top and narrow at the bottom on the surfaces of the semiconductor substrate and the gate structure includes:

forming a shielding insulating layer with a first trench on the surfaces of the semiconductor substrate and the gate structure, and a shielding insulating layer with a certain thickness is reserved at the bottom of the first trench;

A sacrificial layer is covered on the surface of the shielding insulating layer with the first trench, and the sacrificial layer fills the first trench;

The sacrificial layer and the shielding insulating layer are etched in the upper region of the side of the first trench away from the gate structure, so as to form a second trench that is wide at the top and narrow at the bottom. The second trench is The sidewall close to the gate structure is the sacrificial layer, the sidewall far from the gate structure is the shielding insulating layer, and the bottom of the second trench is lower than or equal to the first trench the bottom of the groove;

The sacrificial layer is removed, so as to form a shielding trench with a wide upper portion and a narrow lower portion in the shielding insulating layer.

Optionally, the process of forming the shielding insulating layer with the first trench on the surfaces of the semiconductor substrate and the gate structure includes:

forming a first insulating layer on a part of the surface of the drift region of the semiconductor substrate;

forming a top planarized second insulating layer and a patterned mask layer having an opening above the first insulating layer in sequence on the surfaces of the semiconductor substrate, the gate structure and the first insulating layer;

Using the patterned mask layer as a mask, a vertical etching process or an approximately vertical etching process is used to etch the second insulating layer to form a first trench exposing the surface of the first insulating layer.

Optionally, the material of the patterned mask layer includes photoresist, the first insulating layer is a silicon oxide layer, and the second insulating layer is a nitride layer sequentially stacked on the surface of the first insulating layer. silicon layer and silicon oxide layer.

Optionally, the etching gas of the vertical etching process or the approximately vertical etching process includes a gas containing carbon and fluorine.

Optionally, after the first insulating layer is formed and before the second insulating layer is formed, the gate structure and the first insulating layer are used as masks, and the gate structure and the first insulating layer are used as masks. performing source-drain ion implantation on the semiconductor substrate to form a source region in the well region and a drain region in the drift region on the side of the first insulating layer away from the gate structure; or, etching the shielding The insulating layer forms a source contact hole exposing part of the surface of the well region, and also forms a drain contact hole exposing part of the surface of the drift region, the drain contact hole is located in the shielding trench away from the gate In the shielding insulating layer on one side of the electrode structure, after the source contact hole and the drain contact hole are formed, using the gate structure and the shielding insulating layer as a mask, the source contact hole and the drain contact hole are formed. The semiconductor substrate at the bottom of the drain contact hole is implanted with source and drain ions to form a source region in the well region and a drain region in the drift region.

Optionally, after the source region is formed, a body connection region having a different doping type from that of the source region and being farther away from the gate structure than the source region is formed in the well region, the body connection region and The source regions are distributed laterally within the well region and are separated by a second lateral distance.

Optionally, a field oxygen isolation structure is provided between the body connection region and the source region, so that the body connection region and the source region are separated by a second lateral distance; and/or, the drain region and There is no field oxygen isolation structure between the gate structures.

Optionally, in the process of providing the semiconductor substrate, before or after forming the drift region, a multi-step ion implantation process is used to perform multiple operations on the semiconductor substrate on the side of the gate structure away from the drift region. ion implantation to form the well region.

Optionally, the process of etching the sacrificial layer and the shielding insulating layer in the upper region of the side of the first trench away from the gate structure to form a second trench with an upper width and a lower width includes: :

First, a patterned photoresist layer is formed on the surface of the sacrificial layer, the patterned photoresist layer has an opening that is displaced from the first trench, and the opening is opposite to the first trench further away from the gate structure;

Then, using the patterned photoresist layer as a mask, the sacrificial layer and the shielding insulating layer are etched, so as to form a second trench with an upper width and a lower width.

Optionally, the sacrificial layer includes an anti-reflection layer having a flat top surface.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

1. In the LDMOS transistor of the present invention, the shielding trench can increase the average thickness of the shielding insulating layer on the side away from the gate structure, reduce the electric field intensity under the metal layer, and at the same time make the electric field under the metal layer more uniform. distribution, and is beneficial to suppress the hot carrier injection (HCI) effect at the edge of the gate structure, thereby enabling higher breakdown voltage and lower on-resistance, and ultimately improving device performance _.

2. The manufacturing method of the LDMOS transistor of the present invention only needs to change the rectangular trench formed in the shielding insulating layer into a shielding trench that is wide at the top and narrow at the bottom, and the manufacturing process is simple.

Description of drawings

1 is a schematic diagram of a cross-sectional structure of an LDMOS device;

2A to 2F are schematic cross-sectional structural diagrams of an LDMOS device according to a specific embodiment of the present invention;

3 is a flowchart of a method for manufacturing an LDMOS device according to a specific embodiment of the present invention;

4A to 4F are schematic cross-sectional structural diagrams of a device in a method for manufacturing an LDMOS device according to a specific embodiment of the present invention;

5A to 5B are schematic diagrams showing the results of performance testing of the LDMOS shown in FIG. 1 and the LDMOS of the present invention, respectively.

Detailed ways

As described in the background, higher performance LDMOS transistors are required to have higher breakdown voltages and lower on-resistances. In order to obtain higher breakdown voltage and lower on-resistance, one current approach is to form a shield plate with rectangular grooves over the gate structure and drain region, and cover the shield plate with aluminum A high-performance LDMOS transistor is formed by using other metal layers. The specific structure of this LDMOS transistor is shown in FIG. 1, including: a semiconductor substrate 100, and N-type drift regions (N-type drift regions (N -drift) 103 and P-well (P-WELL) 105, the gate structure 101 formed on the surface of the semiconductor substrate 100 and the spacers 102 located on the sidewalls of the gate structure 101 are formed in the N-type drift region (N- The drain region (N+, drain) 104 in the drift) 103, the source region (N+, source) 107, the body connection region (P-body) 108 and the isolation source region 107 and The field oxygen isolation structure 106 of the body connection region 108, the shielding insulating layer 109 covering the surface of the spacer 102, the gate structure 101 and the N-type drift region 103 between the drain region 104 and the gate structure 101, covering the source Metal layer 110 on the surface of region 107 and shield insulating layer 109 . A rectangular groove is formed in the shielding insulating layer 109 between the gate structure 101 and the drain region 104. The metal layer 110 on the surface of the shielding insulating layer 109 can evenly distribute the field intensity of the N-type drift region 104 and reduce the gate-drain fringe electric field. Increase the breakdown voltage and reduce the on-resistance.

However, the breakdown voltage of the LDMOS transistor with this structure is difficult to improve, because the shielding insulating layer 109 at the bottom of the rectangular groove accumulates charges due to the hot carrier injection effect, so that the electric field at the edge of the gate structure is still high.

Based on this, the present invention provides an LDMOS transistor and a manufacturing method thereof, which can improve the hot carrier injection effect at the bottom of the trench of the shielding insulating layer, uniform the field intensity distribution of the drift region, reduce the gate-drain fringe electric field, and improve the breakdown voltage. , reduce the on-resistance.

In order to make the purpose and features of the present invention more clearly understood, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited to the described embodiments.

2A to 2E, the present invention provides an LDMOS transistor including: a semiconductor substrate 200, a gate structure 201, a sidewall spacer 202, a drift region 203, a drain region 204, a well region 205, a field oxygen isolation structure 206, a source region 207 , body connection region 208 , shield insulating layer 209 and metal layer 210 .

The semiconductor substrate 100 can be any semiconductor material well known to those skilled in the art, such as bulk silicon substrate, silicon-on-insulator substrate, silicon-germanium epitaxial layer on silicon, etc.; the well region 205 and the drift region The doping type of 203 is different. For example, when the LDMOS transistor is an N-type transistor, the doping type of the well region 205 is P-type, that is, the well region 205 is a P-well (P-well), and the doping type of the drift region 203 is N. When the LDMOS transistor is a P-type transistor, the doping type of the well region 205 is N-type, that is, the well region 205 is an N-well, the doping type of the drift region 204 is P-type, and the well region 205 and the drift region 203 Distributed laterally within the semiconductor substrate 200 and separated by a lateral distance.

The gate structure 201 is located on the surface of the semiconductor substrate 200 and spans the edge of the well region 205 and the edge of the drift region 203 , that is, the gate structure 201 does not only cover between the well region 205 and the drift region 204 . It also partially covers the surface of the well region 205 and partially covers the surface of the drift region 203 on the surface of the semiconductor substrate in between. The gate structure 201 may include a gate dielectric layer (not shown, for example, silicon dioxide or a high-K dielectric with a dielectric constant K greater than or equal to 4) and a gate electrode layer (for example, a gate electrode layer) stacked on the surface of the gate dielectric layer. for polysilicon or metal). Spacers 202 are located on the surface of the semiconductor substrate 200 and cover the sidewalls of the gate structure 201 .

The drain region 204 is located in the drift region 203 , and has the same doping type as the drift region 203 , but with different doping concentrations. There is no field oxygen isolation structure between the drain region 204 and the gate structure 201 . The body connection region 208 and the source region 207 are laterally distributed in the well region 205 and separated by another lateral distance by the field oxygen isolation structure 206. The source region 207 is closer to the gate structure 201 than the body connection region 208, so that the source The region 207 and the drain region 204 are located on both sides of the gate structure 201, and the source region 207 is closer to the gate structure 201 than the drain region 204. The doping types of the body connection region 208 and the source region 207 are different. The doping type of the connection region 206 is the same as that of the well region 205, but the doping concentration is different. The doping type of the source region 207 is the same as that of the drift region 203, but the doping concentration is different. The field oxygen isolation structure 206 may be a field oxygen isolation structure formed by a shallow trench isolation process, or may be a field oxygen isolation structure formed by a local field oxygen isolation process.

The shielding insulating layer 209 covers the spacers 202 , the gate structure 201 and the surface of the drift region 203 between the gate structure 201 and the drain region 204 , and has an upper narrowing in the region between the gate structure 201 and the drain region 204 The lower width of the shielding trench, the shielding trench extends from the surface of the shielding insulating layer 209 into the shielding insulating layer 209, and does not penetrate the shielding insulating layer 209, and the thickness of the shielding insulating layer 209 remaining at the bottom of the shielding trench It can be greater than or equal to the thickness of the gate dielectric layer in the gate structure 201 . At this time, the portion of the shielding insulating layer 209 above the drift region 203 only exposes the drain region 204 . Referring to FIG. 2A , the shape of the shielding trench in the film stacking direction (ie, the direction from the bottom to the top) can be a right-angled trapezoid 209 a with a wide upper and a lower narrow, and the right angle of the right-angled trapezoid 209 a is located close to the gate On one side of the pole structure 201, the acute angle in the right-angled trapezoid is 45°-70°; or, please refer to FIG. 2C, the shape of the shielding trench in the film stacking direction is wide at the top and narrow at the bottom, with right angles and A polygon 209b with an arc side, the bottom angle Q of the side of the polygon 209b close to the gate structure 201 is a right angle, the bottom is a horizontal line segment, and the side away from the gate structure 201 is an arc line segment; or 2D, the shape of the shielding trench in the film stacking direction is a sector 209c, the side of the sector 209c close to the gate structure 201 is a vertical side, away from the gate structure One side of the 201 is an arc segment, and the arc segment makes the shielding insulating layer 209 at the bottom of the shielding trench thicker and thicker along the direction away from the gate structure 201; alternatively, please refer to FIG. The shape of the shielding trench in the film stacking direction is a polygon 209d that is wide at the top and narrow at the bottom and has a right angle. The side away from the gate structure 201 is a polygonal edge formed by connecting a plurality of line segments with gradually increasing slopes in sequence, and the slope of the edge with the largest slope among the polygonal edges is less than or equal to tg70°. The material of the shielding insulating layer 209 can be silicon oxide, silicon nitride or silicon oxynitride, as shown in FIGS. 2A to 2E , and can also include two or more of silicon oxide, silicon nitride and silicon oxynitride, as shown in FIG. 2F As shown in 2091, 2092, and 2093 in FIG. 2F, that is, the materials of layers 2091 and 2093 in FIG. 2F may be the same or different; the materials of layer 2092 in FIG. 2F are different from those of layer 2091.

The metal layer 210 covers the source region 207, the sidewalls of the gate structure 201 and the surface of the shielding insulating layer 209, and one end of the metal layer 210 covering the surface of the shielding insulating layer 209 may cover the surface of the shielding insulating layer 209. The shielding trench is close to the edge of the drain region 204, as shown in FIG. 2A, FIG. 2C to FIG. 2F, and can also cover the edge of the shielding insulating layer 209 close to the drain region 204, as shown in FIG. 2B. , that is, the metal layer 210 may cover the shielding insulating layer 209 completely or partially. The material of the metal layer 210 includes at least one of Ti, Al, W, TiN or TiW.

Referring to FIGS. 5A and 5B , the saturation current Idsat (that is, the maximum current flowing between the source/drain when the gate voltage is constant) and the LDMOS transistor shown in FIG. 1 are subjected to the same breakdown voltage BV and According to the FOM2 (figure of merit) test analysis, the selected LDMOS transistor of the present invention and the LDMOS transistor shown in FIG. 1 only have different trench shapes in the region between the gate structure and the drain region of the shielding insulating layer. The shielding trench shape of the shielding insulating layer of the LDMOS transistor of the present invention in the region between the gate structure and the drain region is a right-angled trapezoid, and the trench shape of the shielding insulating layer of the LDMOS transistor shown in FIG. 1 is a rectangle, and the present The width of the top opening of the shielding trench of the inventive LDMOS transistor is the same as the width of the top opening of the trench of the shielding insulating layer of the LDMOS transistor shown in FIG. 1 . It can be seen from FIGS. 5A and 5B that the LDMOS transistor of the present invention has relatively better saturation current Idsat and quality factor FOM2 than the LDMOS transistor shown in FIG. 1 with the same breakdown voltage, wherein FOM2 or device The figure of merit is related to the on-resistance. The lower the value, the lower the on-resistance and the better the device performance. That is to say, with the same Idsat and FOM2, the LDMOS transistor of the present invention has a higher breakdown voltage and lower on-resistance. This is because the shielding insulating layer of the LDMOS transistor of the present invention has a shielding trench with a wide top and a narrow bottom above the drift region, when the top opening width of the shielding trench is the same as the top opening width of the rectangular trench of the existing LDMOS transistor At the same time, the shielding trench can increase the average thickness of the shielding insulating layer on the side away from the gate structure, reduce the electric field intensity under the metal layer, and at the same time make the electric field under the metal layer more uniformly distributed, which is beneficial to suppress the gate The hot carrier injection (HCI) effect at the edge of the polar structure enables higher breakdown voltage and lower on-resistance, ultimately improving device performance _.

Please refer to FIG. 3 , the present invention also provides a method for manufacturing an LDMOS transistor, comprising the following steps:

S1, providing a semiconductor substrate, in which a well region and a drift region of different doping types are formed, the well region and the drift region are laterally distributed in the semiconductor substrate and separated by a first lateral distance, the A gate structure spanning the edge of the well region and the edge of the drift region is formed on the surface of the semiconductor substrate;

S2, forming a shielding insulating layer having a shielding trench that is wide at the top and narrow at the bottom on the surfaces of the semiconductor substrate and the gate structure, and the shielding trench does not penetrate the shielding insulating layer;

S3, etching the shielding insulating layer to at least form a source contact hole exposing a part of the surface of the well region;

S4, forming a metal layer on the surface of the source contact hole and the remaining shielding insulating layer.

Referring to FIG. 4A, in step S1, the provided semiconductor substrate 400 may be any semiconductor material known to those skilled in the art, such as a bulk silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, or a Doped semiconductor epitaxial layer structure. When the semiconductor substrate 400 is used for the subsequent formation of N-type LDMOS transistors, the semiconductor substrate 400 is P-type doped; when the semiconductor substrate 400 is used for the subsequent formation of P-type LDMOS transistors, the semiconductor substrate 400 is doped The bottom 400 is N-type doped, the P-type doped ions are one or more of boron ions, indium ions, and gallium ions, and the N-type doped ions are phosphorus ions, arsenic ions, and antimony ions. one or more of them. In step S1, a device isolation process such as a shallow trench isolation process or a local field oxygen isolation process (including steps such as photolithography, etching, and dielectric filling) may be used to form a well region located in the semiconductor substrate 400 to be formed. 405 medium field oxygen isolation structure 401; then, on the surface of the semiconductor substrate 400, a gate dielectric layer 402a is formed by a deposition process or a thermal growth process, and a gate electrode layer 402b is deposited on the surface of the gate dielectric layer 402a; The gate electrode layer 402b and the gate dielectric layer 402a are sequentially etched by the polar lithography and etching processes to form the gate structure 402, wherein the gate dielectric layer 402a can be silicon nitride, silicon oxynitride, silicon oxide or high-K dielectric. Electrical material, the high-K dielectric material is HfO, ZrO, WN, Al ₂ O ₃ , HfSiO or any combination thereof, and the gate electrode 402b may be polysilicon or metal. Afterwards, a spacer 403 may be formed on the sidewall of the gate structure 402 by a spacer forming process (including deposition of a spacer material, etching, etc.).

In step S1, before the gate structure 402 is formed, or after the gate structure 402 is formed, or after the spacer 403 is formed, the drift region 404 and the well region 405 are respectively formed through a corresponding photomask process and an ion implantation process, specifically , first, a layer of photoresist mask is used to protect the surface of the semiconductor substrate 400 on the side of the source region, and the surface of the semiconductor substrate 400 on the side of the drain region is exposed, and then the exposed semiconductor substrate 400 is exposed. A step of lightly doped LDD ion implantation is performed on the surface of the bottom 400 to form a lightly doped drift region 404, and ions such as phosphorus and arsenic are implanted with an energy of 50keV to 300keV and a dose of 5e ¹¹ cm ^-2 -4e ¹² cm ^-2 , after which the photoresist mask is removed. The drift region 404 may be formed without any field oxygen isolation structure.

In step S1, before or after the drift region 404 is formed, a new photoresist mask is first formed to expose the surface of the semiconductor substrate 400 where the well region is to be formed and to protect the surface of the drift region 404 including the surface of the semiconductor substrate 400. The other surfaces of the semiconductor substrate 400 are then ion-implanted to the exposed surface of the semiconductor substrate 400 using a multi-step ion implantation process to form well regions 405 . The specific process of using the multi-step ion implantation process to form the well region 405 includes: firstly performing a first ion implantation on the exposed surface of the semiconductor substrate 400 through a one-step high-dose, high-energy vertical ion implantation process, and the implanted ion type is the same as The type of doping ions in the drift region 404 is opposite to neutralize the inversion ions in the semiconductor substrate 400 , wherein the implantation dose is, for example, 5e ¹³ cm ⁻² , and the implantation energy is, for example, 300keV. When the well region 405 is a P-well , the ions of the first ion implantation are, for example, boron ions; then, a second ion implantation is performed on the exposed surface of the semiconductor substrate 400 by a one-step low-dose, low-energy vertical ion implantation process, and the implanted ions are The type is opposite to the doping ion type of the drift region 404, and is used to adjust the threshold voltage and form the channel, wherein the implantation dose is, for example, 1e ¹³ cm ^-2 , and the implantation energy is, for example, 80keV. When the well region 405 is a P well, The ions of the second ion implantation are, for example, boron ions; then, a third ion implantation is performed on the exposed surface of the semiconductor substrate 400 using a low-energy, high-dose oblique ion implantation process, and the implanted ions are of the same type as the ion implanted. The doping ion type of the drift region 404 is opposite to prevent punch-through, wherein the implantation dose is, for example, 2.5e ¹³ cm ^-2 , and the implantation energy is, for example, 30keV, and the angle between the vertical line on the surface of the semiconductor substrate 300 (ie, the inclination angle) is 30 degrees to 45 degrees. When the well region 405 is a P well, the ions of the third ion implantation are, for example, boron ions. Finally, through annealing treatment, the dopant ions in the drift region 404 and the well region 405 can be diffused in place, and the edges of the well region 405 and the drift region 404 will diffuse to the bottom of the gate structure 402 for a certain distance. The region 405 and the drift region 404 are distributed laterally within the semiconductor substrate 404 and are separated by a lateral distance, and the gate structure 402 spans the edge of the well region 405 and the edge of the drift region 404 .

Referring to FIGS. 4B to 4E , in step S2 of the present embodiment, the specific process of forming a shielding insulating layer having shielding trenches with upper width and lower width on the surfaces of the semiconductor substrate 400 and the gate structure 402 may include:

First, referring to FIG. 4B , a deposition process or a thermal growth (thermal oxidation, thermal nitridation or thermal oxynitridation) process is used to cover at least the surfaces of the drift region 404 and the well region 405 with a first insulating layer 406 of a certain thickness, The thickness of the first insulating layer 406 depends on the performance requirements of the device, and its thickness is usually greater than or equal to the thickness of the gate dielectric layer 402a, and the material of the first insulating layer 406 is silicon oxide, silicon nitride or silicon oxynitride; An insulating layer 406 is etched to remove the well region 405 and the first insulating layer 406 on the surface of the drift region 404 used to form the drain region. The first insulating layer 406 is used to protect the drift region during subsequent formation of the shielding trench 404, and the thickness of the shielding insulating layer used as an etch stop layer to ensure subsequent shielding trench bottoms. In an embodiment of the present invention, after the etching of the first insulating layer 406 is completed, the gate structure 402 , the sidewall spacers 403 and the first insulating layer 406 may be used as masks to cover the semiconductor linings on both sides of the gate structure 402 . The bottom 400 is implanted with source and drain ions, and the implanted ions are of the same type as the doping ions of the drift region 404, so as to form the source region 407 in the well region 405, and the drift on the side of the first insulating layer 406 away from the gate structure 402 A drain region 408 is formed in the region 404, and after the source region 407 is formed, a doping type different from the source region 407 and further away from the gate structure 402 is further formed in the well region 405. A body connection region 409, the body connection region 409 and the source region 407 are distributed laterally within the well region 404 and are separated by a second lateral distance. In another embodiment of the present invention, the source region 407 , the drain region 408 and the body connection region 409 can also be formed after the subsequent etching of the shielding insulating layer to form source contact holes and drain contact holes, using the shielding insulating layer as the mask, and perform source-drain ion implantation on the surface of the well region 405 at the bottom of the source contact hole and the surface of the drift region at the bottom of the drain contact hole to form the source region 407 and the drain region 408 . In addition, in other embodiments of the present invention, before forming the source region 407 and the drain region 408, a patterned photomask may be formed first, and the patterned photomask exposes the well in which the body region 409 is to be formed The surface of the well region 405 for forming the source region 407 and the surface of the drift region 404 for forming the drain region 408 are protected by the surface of the region 405, and then the well region 405 where the body region 409 is to be formed is exposed to the patterned photomask. The surface is implanted with ions of the same doping type as the well region 405 to form a body connection region 409 in the well region 405 . In addition, when the LDMOS transistor to be formed is an N-type LDMOS transistor, the source and drain ions implanted in the source region 407 and the drain region 408 are N+ ions, such as phosphorus, arsenic or antimony, and the dose ratio in the well region 405 and the drift region 404 is higher than that in the well region 405 and the drift region 404 The dose of the doped ions is large, for example, 1e ¹⁴ cm ^-2 to 1e ¹⁶ cm ^-2 , and the ions implanted in the body region 409 are P+ ions, such as boron or boron difluoride or indium or gallium, and the dose is higher than that of the well region The dose of ions doped in 405 is large, for example, 1e ¹⁴ cm ^-2 -1e ¹⁶ cm ^-2 .

Next, please continue to refer to FIG. 4B , in the well region 405 (including the body connection region 409 and the source region 407 ), the field oxide isolation structure 401 , the spacers 403 , the gate structure 402 , the first insulating layer 406 and the drift region 404 (including the A second insulating layer with top planarization is formed on the surface of the drain region 408) by a deposition process and a chemical mechanical polishing process. Flat process window. The second insulating layer may be a single-layer structure or a stacked-layer structure, for example, the stacked-layer structure includes a thinner dielectric insulating layer 410 and a thicker dielectric insulating layer 410 adjacent to the first insulating layer 406 in sequence. The dielectric insulating layer 411, wherein the deposition thickness of the thicker dielectric insulating layer 411 is sufficient to make it have a flat upper surface after being processed by the chemical mechanical planarization process, and the thinner dielectric insulating layer 410 is relative to the first insulating layer. 406 and the thicker dielectric insulating layer 411 both have a high etching selectivity ratio, and their materials are, for example, silicon nitride or silicon oxynitride, and the materials of the first insulating layer 406 and the thicker dielectric insulating layer 411 can be the same , or different, the materials of the first insulating layer 406 and the thicker dielectric insulating layer 411 can be selected from silicon oxide, silicon nitride or silicon oxynitride. In an embodiment of the present invention, the first insulating layer 406 For example, it is a silicon oxide layer, and the second insulating layer is, for example, a silicon nitride layer (that is, a thinner dielectric insulating layer 410 ) and a silicon oxide layer (that is, a thicker insulating layer 406 ) sequentially stacked on the surface of the first insulating layer 406 . dielectric insulating layer 411). Afterwards, a patterned mask layer 414 with openings is formed on the surface of the second insulating layer. The patterned mask layer 414 can be a single-layer structure or a laminated structure, and its material includes photoresist. The opening of the patterned mask layer 414 is located above the drift region 404 between the gate structure 402 and the drain region 408. Using the patterned mask layer 414 as a mask, a vertical etching process or an approximately vertical etching process is used. The second insulating layer is etched by the etching process, and the etching stops to form a first trench 413 exposing the surface of the first insulating layer 406 . The first trench 413 is a linear trench, that is, a first trench The side wall of 413 is vertical, or approximately vertical (ie, the bottom angle is close to 90°, for example, 75°˜89°). The vertical etching process or the approximately vertical etching process is a dry etching process, such as a plasma etching process. In an embodiment of the present invention, the etching gas used in the plasma etching process includes a gas containing carbon and fluorine (such as CF ₄ , CHF ₃ , C ₂ F ₆ , C ₃ F ₈ , etc.). The precision of the formed first trench 413 is improved, and the damage to the surface of the first insulating layer 406 exposed at the bottom of the first trench is reduced.

Then, referring to FIG. 4C , a suitable process (eg, ashing process, chemical mechanical polishing process or etching process) can be selected according to the material of the patterned mask layer 414 to remove the patterned mask layer 414 , and the patterned mask layer 414 can be removed by deposition, coating A sacrificial layer 414 is formed on the surface of the second insulating layer and the first trench 413 by processes such as It is a laminated structure, and its material can include silicon-containing anti-reflection layer (Si-ARC), polyimide (PMMA) or organic glass (PI); after that, a photolithography process can be used on the surface of the sacrificial layer 414 A patterned photoresist layer 415 is formed. The patterned photoresist layer 415 has an opening 416 that is displaced from the first trench 413 , and the opening 416 is farther away from the first trench 413 than the first trench 413 . Gate structure 402, the dislocation distance between the two is D, that is, the patterns in the patterned photoresist layer 415 and the patterned mask layer 414 can be the same, but there is some relative dislocation. Therefore, the patterned photoresist layer 415 and The patterned mask layer 414 may use the same mask, and the mask may be shifted to a certain extent when the patterned photoresist layer 415 is formed.

Next, referring to FIG. 4D , using the patterned photoresist layer 415 as a mask, the sacrificial layer 414 and the second sacrificial layer 414 and the second layer are etched with an etching gas (heavy polymer gas) that is conducive to generating more polymers. The insulating layer (including the dielectric insulating layer 410 and the dielectric insulating layer 411), that is, the sacrificial layer 414 and the shielding insulating layer are etched in the upper region of the side of the first trench away from the gate structure, so as to An inverted-tapered trench is formed, that is, a second trench 417 with a wide top and a narrow bottom. The sidewall of the second trench 417 close to the gate structure 402 is the sacrificial layer 414 , and the sidewall far from the gate structure 402 is the sacrificial layer 414 . In the shielding insulating layer (ie, the first insulating layer 406 , the dielectric insulating layer 410 and the dielectric insulating layer 411 stacked in sequence), the bottom of the second trench 417 is lower than or equal to that of the first trench 413 . The bottom, that is, the bottom of the second trench 417, exposes the surface of the first insulating layer 406, and the etching gas may include C ₄ F ₆ and may also include O ₂ .

Then, referring to FIG. 4E , the patterned photoresist layer 415 may be removed by an oxygen ashing process, and the remaining sacrificial layer may be removed by a suitable process (eg, wet etching, etc.), thereby forming a shielding trench with a wide top and a narrow bottom The groove 418, at this time, the shielding groove 418 is substantially formed by the superposition of the first groove 413 and the second groove 417, and is in the shape of a right-angled trapezoid, and the right angle of the right-angled trapezoid is located close to the gate structure 402. On one side, the acute angle in the right-angled trapezoid is 45°˜70°.

It should be noted that, the shape of the shielding trench 418 formed in step S2 in other embodiments of the present invention is not limited to the above-mentioned right-angled trapezoid with a wide upper and a narrow lower, but can also be a polygon with a wide upper and narrow lower, such as in The shielding trench 418 formed in step S2 of an embodiment of the present invention may be a polygon with a right angle and a wide upper part and a narrow lower part (209d in FIG. 2E ). One side of the gate structure is a right-angled side, and the side away from the gate structure is a polygonal side formed by successively connecting a plurality of line segments with gradually increasing slopes, and the slope of the side with the largest slope in the polygonal sides is less than or equal to tg70 °, please refer to FIGS. 4B to 4E, the forming process of the polygon with the upper width and the lower narrow and having a right angle includes: firstly forming the first trench 413, and then forming a plurality of tapered trenches whose bottoms are raised sequentially. The formation process of the shaped trench includes sacrificial layer deposition, patterned photoresist dislocation mask, tapered etching of the sacrificial layer and shielding insulating layer, photoresist and sacrificial layer removal). For the formation process, reference may be made to the above-mentioned formation process of the tapered trench (ie, the second trench 417 ), which is not repeated here. For another example, the shielding trench 418 formed in the step S2 of another embodiment of the present invention is a right-angled curved surface (shown as 209b in FIG. 2C ) with a wide top and a narrow bottom, and the right-angled curved surface is close to the gate structure The bottom angle of one side is a right angle, the bottom is a horizontal line segment, and the side away from the gate structure is an arc segment. Please refer to FIGS. 4B to 4E and FIG. 2C. The forming process includes: firstly forming the first trench 413, then through sacrificial layer deposition, patterned photoresist dislocation mask, circular etching or arc-shaped etching of the sacrificial layer and shielding insulating layer (to form arc-shaped trenches) ) and other steps to form a trench with arc-shaped sidewalls, the sidewall of the trench close to the gate structure is an arc-shaped sacrificial layer, and the sidewall of the trench away from the gate structure is an arc-shaped shielding insulating layer, After removing the photoresist and the sacrificial layer, the right-angled polygon with the upper width and the lower narrow is obtained. For the specific process, please refer to the formation process of the right-angled trapezoid shielding trench 418 with the upper width and the lower narrow. The etching process parameters at the time are adaptively adjusted to facilitate the formation of arc grooves. For another example, the shape of the shielding trench formed in step S2 of another embodiment of the present invention is a fan shape (209c in FIG. 2D ), and the side of the fan shape close to the gate structure is The vertical side, the side formed from the bottom of the vertical side to the side of the top of the trench away from the gate structure is an arc segment, and the arc segment makes the shielding insulating layer at the bottom of the shielding trench along the It gets thicker away from the gate structure.

Referring to FIG. 4E, in step S3, the shielding insulating layer is etched through corresponding photolithography and etching processes, that is, the source region 407, the drain region 408 and the dielectric insulating layer 410 and the dielectric insulating layer above the body connection region 409 are etched layer 411 until the surfaces of the source region 407, the drain region 408 and the body connection region 409 are exposed, thereby forming the source contact hole 420, the drain contact hole 419 and the body connection region 421 contact hole, and the source contact hole 420 can be exposed Sidewall surface of sidewall 403 . It should be noted that, in other embodiments of the present invention, when the source region 407 , the drain region 408 and the body connection region 409 have not been formed before step S3 , the shielding insulating layer in the corresponding region is etched in step S3 , until the surface of the well region 405 for forming the body connection region 409 and the source region 408 and the surface of the drift region 404 for forming the drain region 408 are exposed to form the source contact hole 420, the drain contact hole 419 and the body connection region contact hole 421; and, in some embodiments of the present invention, only the shielding dielectric layer above the source region 408 (or the well region used to form the source region 408) may be etched, and the etching stops at the source region 408 (or the surface of the well region 405), thereby forming the source contact hole 420.

In addition, when the source region 407, the drain region 408 and the body connection region 409 have not been formed before step S3, a patterned source-drain photoresist layer may be formed on the shielding insulating layer first, and the patterned source-drain photoresist layer may be formed first. Layer protection body connection area contact hole 421 and the well area 405 below it, and expose the source contact hole 420 and drain contact hole 419, and then use the patterned source-drain photoresist layer and shielding insulating layer as a mask source-drain ion implantation is performed on the semiconductor substrate 400 under the source contact hole 420 and the drain contact hole 419 to form a source region 407 in the well region 405 under the source contact hole 420; A drain region 408 is formed in the lower drift region 404, then the patterned source-drain photoresist layer is removed, and a patterned body region photoresist layer is formed, and the patterned body region photoresist layer protects the source contact hole 420 and the source region 407 under it, the drain contact hole 419 and the drain region 408 under it, and expose the body connection region contact hole 421 and the well region 405 under it; and then use the patterned body region lithography The adhesive layer and the shielding insulating layer are used as masks, and ion implantation is performed on the well region 405 under the contact hole 421 of the body connection region, thereby forming the body connection region 409 in the well region 405 under the contact hole 421 of the body connection region.

Referring to FIG. 4F , in step S4, firstly, at least one metal including Ti, Al, W, TiN or TiW may be covered on the entire surface of the device including the source contact hole 420 by a process such as sputtering deposition, so as to Formation of metal layer 422, ie, covering metal over the shielding insulating layer and its exposed surface of semiconductor substrate 400 (including exposed well region 405, drift region 404, drain region 407, source region 408, and body connection region 409) layer 422; the excess metal layer may then be etched away, leaving only the region from source region 408 (side away from gate structure 402) to shield trench 418 (side away from gate structure 402) The metal layer, or only the metal layer on the region from the source region 408 to the drain region 419 close to the edge of the gate structure 402 is retained, that is, the remaining metal layer 422 covers the source region 407 and the sidewall spacer 403. On the surface of the wall and the shielding insulating layer, and the remaining metal layer 422 can cover the shielding insulating layer completely or partially. Specifically, the remaining metal layer 422 covers the shielding insulating layer. One end on the surface may cover the edge of the shielding trench 418 on the side close to the drain region 408 , or may cover the edge of the shielding insulating layer on the side close to the drain region 408 . The remaining metal layer 422 spans over the gate structure 402 and has one end in contact with the source region 407 and the other end separated from the drain region 408 by a certain distance. The shielding insulating layer between the metal layer 422 and the gate structure 402 has a certain distance. With different thicknesses, the coupling capacitance of the device will also be different. The distance between the other end of the metal layer 422 and the drain region 408 is different, and the electric field strength between the source region 407 and the drain region 408 of the device will also be different. Therefore, the thickness of the shielding insulating layer and the position of the shielding trench 418 therein can be adaptively changed according to different device performance requirements.

The process steps of the semiconductor device manufacturing method of the present invention can be compatible with the existing standard CMOS process. It only needs to change the original rectangular trench into a shielding trench with a narrow top and a wide bottom to reduce the gate and drain interval. The electric field in the area of the device can be more uniformly distributed, and it is beneficial to suppress the hot carrier injection (HCI) effect at the edge of the gate structure, and the output resistance of the device can be greatly improved, so that higher breakdown voltage and lower on-resistance.

Obviously, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (22)

1. a LDMOS transistor, is characterized in that, comprises: semiconductor substrate; A well region and a drift region with different doping types, the well region and the drift region are laterally distributed in the semiconductor substrate and separated by a first lateral distance, a source region is formed in the well region, and a drain region is formed in the drift region Area; a gate structure located on the surface of the semiconductor substrate and spanning the edge of the well region and the edge of the drift region, the source region and the drain region flanking the gate structure; a shielding insulating layer covering the top of the gate structure and extending to a part of the surface of the drift region, the shielding insulating layer exposing the drain region, and covering between the drain region and the gate structure In the shielding insulating layer on the surface of the drift region, a shielding trench with an upper width and a lower width is formed, the shielding trench does not penetrate the shielding insulating layer, and the shielding trench is close to the gate structure. One side is a vertical sidewall, and the sidewall morphology of the sidewall of the shielding trench away from the gate structure makes the opening size of the shielding trench gradually widen from bottom to top, so as to increase the shielding trench the average thickness of the shielding insulating layer on the periphery of one side away from the gate structure; a metal layer covering the source region and the surface of the shielding insulating layer. 2 . The LDMOS transistor according to claim 1 , further comprising a body connection region with a different doping type from the source region, the body connection region and the source region are laterally distributed in the well region. 3 . and separated by a second lateral distance. 3. The LDMOS transistor according to claim 2, wherein a field oxygen isolation structure is provided between the body connection region and the source region, so that the body connection region and the source region are separated by a second a lateral distance; and/or, there is no field oxygen isolation structure between the drain region and the gate structure. 4 . The LDMOS transistor according to claim 1 , wherein the metal layer covers one end of the surface of the shielding insulating layer, covers the edge of the shielding trench close to the drain region, or , covering the edge of the shielding insulating layer close to the drain region. 5. The LDMOS transistor according to claim 1, wherein the material of the shielding insulating layer comprises at least one of silicon oxide, silicon nitride and silicon oxynitride. 6. The LDMOS transistor according to claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer sequentially stacked on the surface of the semiconductor substrate, and a gate dielectric layer and a gate electrode layer that cover the gate dielectric layer and the gate electrode layer. The thickness of the spacers on the sidewalls of the electrode layer, the shielding insulating layer at the bottom of the shielding trench is greater than or equal to the thickness of the gate dielectric layer. 7. The LDMOS transistor according to any one of claims 1 to 6, wherein the shape of the shielding trench in the film stacking direction is a right-angled trapezoid that is wide at the top and narrow at the bottom, and the right-angled trapezoid has a right angle. is located on the side close to the gate structure; or, the shape of the shielding trench in the film stacking direction is a fan shape; or, the shape of the shielding trench in the film stacking direction is a polygon with a right angle, The side of the polygon close to the gate structure is a right-angled side, and the side away from the gate structure is a continuous arc segment or a polygonal side formed by sequentially connecting a plurality of line segments with gradually increasing slopes. 8 . The LDMOS transistor according to claim 7 , wherein the acute angle of the right-angled trapezoid is 45°˜70°. 9 . 9. a manufacturing method of LDMOS transistor, is characterized in that, comprises the following steps: A semiconductor substrate is provided, in which a well region and a drift region of different doping types are formed, the well region and the drift region are laterally distributed in the semiconductor substrate and separated by a first lateral distance, the semiconductor substrate A gate structure spanning the edge of the well region and the edge of the drift region is formed on the surface of the bottom; A shielding insulating layer with a shielding trench that is wide at the top and narrow at the bottom is formed on the surface of the semiconductor substrate and the gate structure, the shielding trench does not penetrate the shielding insulating layer, and the shielding trench is close to the gate One side of the pole structure is a vertical sidewall, and the sidewall of the shielding trench away from the gate structure makes the opening size of the shielding trench gradually widen from bottom to top, so as to increase the shielding trench the average thickness of the shielding insulating layer on the periphery of the groove away from the gate structure; etching the shielding insulating layer to at least form a source contact hole exposing a part of the surface of the well region; A metal layer is formed on the surface of the source contact hole and the remaining shielding insulating layer. 10. The method for manufacturing an LDMOS transistor according to claim 9, wherein the process of forming a shielding insulating layer with a shielding trench having a wide upper and narrow lower shielding trenches on the surfaces of the semiconductor substrate and the gate structure comprises: forming a shielding insulating layer with a first trench on the surfaces of the semiconductor substrate and the gate structure, and a shielding insulating layer with a certain thickness is reserved at the bottom of the first trench; A sacrificial layer is covered on the surface of the shielding insulating layer with the first trench, and the sacrificial layer fills the first trench; The sacrificial layer and the shielding insulating layer are etched in the upper region of the side of the first trench away from the gate structure, so as to form a second trench that is wide at the top and narrow at the bottom. The second trench is The sidewall close to the gate structure is the sacrificial layer, the sidewall far from the gate structure is the shielding insulating layer, and the bottom of the second trench is lower than or equal to the first trench the bottom of the groove; The sacrificial layer is removed, so as to form a shielding trench with a wide upper portion and a narrow lower portion in the shielding insulating layer. 11. The method for manufacturing an LDMOS transistor according to claim 10, wherein the process of forming a shielding insulating layer having a first trench on the surfaces of the semiconductor substrate and the gate structure comprises: forming a first insulating layer on a part of the surface of the drift region of the semiconductor substrate; forming a top planarized second insulating layer and a patterned mask layer having an opening above the first insulating layer in sequence on the surfaces of the semiconductor substrate, the gate structure and the first insulating layer; Using the patterned mask layer as a mask, a vertical etching process or an approximately vertical etching process is used to etch the second insulating layer to form a first trench exposing the surface of the first insulating layer. 12 . The method for manufacturing an LDMOS transistor according to claim 11 , wherein the material of the patterned mask layer comprises photoresist, the first insulating layer is a silicon oxide layer, and the second insulating layer is a silicon oxide layer. 13 . The silicon nitride layer and the silicon oxide layer are sequentially stacked on the surface of the first insulating layer. 13 . The method for manufacturing an LDMOS transistor according to claim 11 , wherein the etching gas of the vertical etching process or the approximately vertical etching process comprises a gas containing carbon and fluorine. 14 . 14. The method for manufacturing an LDMOS transistor according to claim 11, wherein after the first insulating layer is formed and before the second insulating layer is formed, the gate structure and the first The insulating layer is a mask, and source and drain ions are implanted into the semiconductor substrate on both sides of the gate structure to form a source region in the well region, and the first insulating layer is on the side away from the gate structure. A drain region is formed in the drift region of the well region; alternatively, the source contact hole exposing part of the surface of the well region is formed by etching the shielding insulating layer, and the drain contact hole exposing part of the surface of the drift region is also formed, so The drain contact hole is located in the shielding insulating layer on the side of the shielding trench away from the gate structure, and after the source contact hole and the drain contact hole are formed, the gate structure and the The shielding insulating layer is a mask, and source-drain ion implantation is performed on the semiconductor substrate at the bottom of the source contact hole and the drain contact hole to form a source region in the well region and a drain region in the drift region . 15 . The method for manufacturing an LDMOS transistor according to claim 14 , further comprising: after forming the source region, forming in the well region a doping type different from that of the source region and opposite to the source region. 16 . Further away from the body-connect region of the gate structure, the body-connect region and the source region are distributed laterally within the well region and separated by a second lateral distance. 16. The method for manufacturing an LDMOS transistor according to claim 15, wherein a field oxygen isolation structure is provided between the body connection region and the source region, so that the body connection region and the source region are separated from each other. separated by a second lateral distance; and/or, there is no field oxygen isolation structure between the drain region and the gate structure. 17 . The method for manufacturing an LDMOS transistor according to claim 9 , wherein in the process of providing the semiconductor substrate, before or after the drift region is formed, a multi-step ion implantation process is used for the gate electrode. 18 . The semiconductor substrate on the side of the structure away from the drift region is subjected to multiple ion implantation to form the well region. 18 . The method for manufacturing an LDMOS transistor according to claim 10 , wherein the sacrificial layer and the shielding insulating layer are etched in the upper region of the side of the first trench away from the gate structure. 19 . , the process of forming a second trench with an upper width and a lower width includes: First, a patterned photoresist layer is formed on the surface of the sacrificial layer, the patterned photoresist layer has an opening that is displaced from the first trench, and the opening is opposite to the first trench further away from the gate structure; Then, using the patterned photoresist layer as a mask, the sacrificial layer and the shielding insulating layer are etched, so as to form a second trench with an upper width and a lower width. 19. The method of manufacturing an LDMOS transistor of claim 18, wherein the sacrificial layer comprises an anti-reflection layer having a flat top surface. 20. The method for manufacturing an LDMOS transistor according to any one of claims 9 to 19, wherein the shape of the shielding trench in the film stacking direction is a right-angled trapezoid that is wide at the top and narrow at the bottom, and the right-angle The right angle of the trapezoid is located on the side close to the gate structure; or, the shape of the shielding trench in the film stacking direction is a fan shape; or the shape of the shielding trench in the film stacking direction is a right angle The side of the polygon close to the gate structure is a right-angled side, and the side away from the gate structure is a continuous arc segment or a polygon formed by sequentially connecting multiple line segments with gradually increasing slopes side. 21 . The method for manufacturing an LDMOS transistor according to claim 20 , wherein the acute angle of the right-angled trapezoid is 45°˜70°. 22 . 22. The method for manufacturing an LDMOS transistor according to any one of claims 14 to 16, wherein the metal layer covers one end of the surface of the shielding insulating layer and covers the shielding trench close to the drain region on the edge of the shielding insulating layer, or covering the edge of the shielding insulating layer close to the drain region.

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