CN116314105A - Package substrate for integrated circuit, integrated circuit chip, circuit board and electronic device - Google Patents

Abstract

The invention provides a packaging substrate of an integrated circuit, an integrated circuit chip, a circuit board and electronic equipment, and relates to the field of integrated circuits. One surface of the packaging substrate is provided with a spherical grid array BGA, and the spherical grid array comprises a first BGA area and at least one second BGA area; the solder balls in the first BGA area are arranged in a diamond shape along the first direction; the solder balls of the second BGA area are arranged in a diamond shape along the second direction; the first direction is perpendicular to the second direction. The method has the advantages that the solder balls in the spherical grid array are arranged in a diamond shape, and the number of the solder balls in the diamond shape is larger than that of the solder balls in the square shape under the unified packaging size.

Description

Integrated circuit packaging substrates, integrated circuit chips, circuit boards and electronic equipment

technical field

The invention relates to the field of integrated circuits, in particular to an integrated circuit package substrate, an integrated circuit chip, a circuit board and electronic equipment.

Background technique

The packaging form of integrated circuits (IC) has progressed from the initial dual-in-line (DIP) packaging to the current flip-chip BGA packaging, and the number of pins of the chip has developed from the initial dozens to the current ones that can be connected.

With nearly 10,000 package pins, the signal speed has increased from the initial few MHz to 112Gbps, and the power consumption has also increased from the initial 1-2 watts to several hundred watts, further increasing the package size of the chip.

inch has encountered a certain bottleneck, in addition to the cost increase and yield decline, the warpage problem is currently the biggest challenge for large-size (50mm x 50mm) flip-chip packaging. Therefore, in the case of keeping the package size of the chip unchanged, how to avoid the crosstalk between adjacent signals while increasing the number of outgoing signals has become a very important research direction.

5 A typical solder ball arrangement (bottom view) is shown in Figure 1, and the schematic diagram of the solder ball arrangement shown in Figure 1

In the figure, the width of the package size is 8.000mm, the height is 8.000mm, the BGA solder balls are arranged in a square, the diameter of each solder ball is a typical value of 0.600mm, and the distance between two solder balls in the horizontal and vertical directions is a typical value It is 1.000mm. The BGA solder ball diameter and the BGA solder ball pitch are set to take into account the processability of the printed circuit board (PCB) and the crosstalk between signals.

0 And how to increase the number of BGA solder balls arranged while keeping the package size unchanged?

Questions to consider.

Contents of the invention

The object of the present invention is to provide an integrated circuit packaging substrate, integrated circuit chip, circuit board and electronic equipment, so as to improve the problems existing in the prior art.

Embodiments of the present invention can be realized like this:

In a first aspect, the present invention provides an integrated circuit packaging substrate, one side of the packaging substrate is provided with a ball grid array BGA; the ball grid array includes a first BGA area and at least one second BGA area;

Wherein, the BGA solder balls in the first BGA area are arranged in a diamond shape along a first direction; the BGA solder balls in the second BGA area are arranged in a diamond shape along a second direction; The two directions are vertical.

In an optional embodiment, the direction of the signal traces in the first BGA area is consistent with the first direction.

In an optional embodiment, in the first BGA region, the distance between any two adjacent BGA solder balls is the same.

In an optional embodiment, the direction of the signal wiring in the second BGA area is consistent with the second direction.

In an optional embodiment, one side of the substrate is a rectangle, and the second BGA area is located at an edge area of any side of the rectangle parallel to the first direction;

In the second BGA region, the distance between any two adjacent BGA solder balls is the same.

In an optional embodiment, in the second BGA region or in the second BGA region, the distance between any two adjacent BGA solder balls is a first value.

In an optional embodiment, the diameter of the BGA solder ball is the second value.

In a second aspect, the present invention provides an integrated circuit chip, comprising the package substrate of the integrated circuit described in any one embodiment of the first aspect above.

In an optional embodiment, several metal bumps are provided on the other surface of the substrate, the metal bumps are covered with a bare core layer, the bare core layer is covered with a heat conduction layer, and the heat conduction layer Covered with a metal top cover.

In a third aspect, the present invention provides a circuit board, comprising the integrated circuit chip described in any embodiment of the second aspect above.

In a fourth aspect, the present invention provides an electronic device, comprising the circuit board described in the above third aspect.

Compared with the prior art, the embodiment of the present invention provides an integrated circuit package substrate, an integrated circuit chip, a circuit board and electronic equipment. One side of the package substrate is provided with a ball grid array BGA, and the ball grid array includes a first A BGA area and at least one second BGA area; wherein, the solder balls in the first BGA area are arranged in a rhombus along the first direction; the solder balls in the second BGA area are arranged in a rhombus along the second direction; the first direction and the The second direction is vertical. The beneficial point is that the solder balls in the ball grid array are all arranged in a diamond shape, and under a uniform package size, the number of solder balls arranged in a diamond shape will be more than the number of solder balls arranged in a square shape.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and thus It should be regarded as a limitation on the scope, and those skilled in the art can also obtain other related drawings based on these drawings without creative work.

Figure 1 is a schematic diagram of a typical solder ball arrangement.

FIG. 2 is one of the schematic diagrams of solder balls arranged in a rhombus arrangement in the prior art.

FIG. 3 is a schematic diagram of signal routing in an east-west routing area in the prior art when solder balls are arranged in a diamond shape.

FIG. 4 is a schematic diagram of signal routing in the north-south routing area when the solder balls are arranged in a diamond shape in the prior art.

FIG. 5 is a schematic diagram of the size of rhombuses in the first BGA area and the second BGA area in the embodiment of the present invention.

FIG. 6 is a schematic diagram of a ball grid array provided by an embodiment of the present invention.

Fig. 7 is an enlarged view of a local area of the ball grid array provided by the embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of an integrated circuit chip.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that if the orientation or positional relationship indicated by the terms "upper", "lower", "inner" and "outer" appear, it is based on the orientation or positional relationship shown in the drawings, or It is the orientation or positional relationship that the invention product is usually placed in use, and it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation , and therefore cannot be construed as a limitation of the present invention.

In addition, terms such as "first" and "second" are used only for distinguishing descriptions, and should not be understood as indicating or implying relative importance.

It should be noted that, in the case of no conflict, the features in the embodiments of the present invention may be combined with each other.

The explanation of the specific names or special terms involved in the present invention is as follows:

1. IC: Integrated Circuit, namely integrated circuit;

2. Solder Ball: solder ball;

3. BGA: Ball Grid Array Package, that is, ball grid array package.

First, in combination with Figure 1, in order to increase the number of BGA solder balls under the same package size, a method in the prior art is as follows:

By simply reducing the spacing between two BGA solder balls from 1.000mm to 0.800mm or smaller, the number of BGA solder balls can be increased while maintaining the chip package size. For example, the package size in Figure 1 is 8.000mm×8.000mm. If the pitch of the BGA solder balls can be reduced from the original 1.000mm to 0.800mm, then the package size of the BGA solder balls will The number can be increased from 64 to 100.

In order for the solder balls to go out on the PCB board, since the pitch of the BGA solder balls is reduced, the diameter of the solder balls needs to be reduced accordingly. For example, if the pitch of the BGA solder balls is reduced to 0.800mm, then the diameter of the BGA solder balls will be reduced from 0.600mm to 0.500mm accordingly. mm.

However, on the one hand, the reduced pitch of BGA solder balls will increase the crosstalk between signals passing through adjacent signal traces. For high-speed signals such as 112Gbps, the requirements for crosstalk between differential lines are very strict, and the distance between a pair of differential lines must not be smaller than a certain size. Therefore, the reduction of BGA solder ball pitch cannot meet the crosstalk index requirements between high-speed signals and differential lines, that is, the reduction of BGA solder ball pitch cannot meet the spacing requirements between high-speed signals and differential lines.

On the other hand, the narrowing of the pitch of BGA solder balls will lead to greater processing difficulty, and the shrinking of the pitch will also arbitrarily make the solders of adjacent BGA solder balls stick together and cause short circuits. In addition, the diameter of BGA solder balls shrinks, and during the substrate soldering process, temperature changes can easily lead to solder ball warping, resulting in virtual soldering or even solder ball drop-off.

Secondly, in order to increase the number of BGA solder balls under the same package size or reduce the package size under the same number of BGA solder balls, another approach in the prior art is as follows:

The typical square arrangement of BGA solder balls is replaced by a diamond-shaped arrangement, which can ensure that the package size of the chip can be reduced without violating the requirements of the high-speed signal for the spacing of the solder balls, or conversely, the package size can be kept unchanged. In the case of increasing the number of BGA solder balls.

Please refer to Figure 2, which includes 64 BGA solder balls, the distance between BGA solder balls in the horizontal direction is 1.000mm, and the distance between adjacent BGA solder balls in the oblique direction (45-degree angle direction) is also 1.000mm, The diameter of the BGA solder ball remains unchanged at 0.600mm, while the package size shown in Figure 2 is 8.500mm×7.0620mm.

Figure 1 also includes 64 BGA solder balls. Therefore, compared with Figure 1, in the case of the same number of solder balls in Figure 2, the rhombus arrangement in Figure 2 can reduce the package size by 13.4% under ideal conditions. In other words, under the same package size, the diamond-shaped arrangement of solder balls increases the density of solder balls by 13.4% compared with the square arrangement.

However, the diamond pattern affects the length of the signal traces. analyse as below:

Assuming that the signal routing in Figure 2 needs to be routed in the east-west direction, then the corresponding signal routing schematic diagram can be shown in Figure 3 . In Figure 3, each pair of differential lines includes two signal traces, and the line width and line spacing of each pair of differential lines are 6mil and 7mil respectively (1mil=0.001inch=0.0254mm). Based on the diamond-shaped arrangement of BGA solder balls, it can Use two layers of wiring to lead the signal line from the BGA solder ball to the outside of the chip. The wiring layer 1 includes differential line 1A, differential line 1B, differential line 1C, and differential line 1D. The wiring layer 2 includes differential line 2A and differential line 2B. , Differential line 2C, Differential line 2D. It can be seen that the signal traces are parallel to the east-west direction, and the length of the signal traces is the shortest.

However, if the signal routing in FIG. 2 needs to be routed in the north-south direction, then the corresponding signal routing schematic diagram can be shown in FIG. 4 . In Figure 4, similarly, based on the diamond-shaped arrangement of BGA solder balls, two layers of wiring are used to lead the signal lines from the BGA solder balls to the outside of the chip. The wiring layer 1 includes differential line 1A, differential line 1B, and differential line 1C. 1. The differential line 1D, and the wiring layer 2 includes a differential line 2A, a differential line 2B, a differential line 2C, and a differential line 2D. However, due to the arrangement of the solder balls, the direction of the signal traces cannot be parallel to the north-south direction, and the direction of the signal traces forms an included angle of approximately 300° with a straight line in the north-south direction. In this way, in the north-south direction, since the signal routing is oblique, the length of the signal routing will be increased accordingly, and the insertion loss of the high-speed signal will also be increased accordingly.

Based on the discovery of the above technical problems, the inventor proposes the following technical solutions through creative efforts to solve or improve the above problems. It should be noted that the defects in the above solutions in the prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the following embodiments of the present application aim at the above problems The proposed solutions should all be contributions made by the inventors to this application during the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

The inventor found through long-term observation and research that if the diamond-shaped arrangement of BGA solder balls in the north-south routing area is required, the signal routing corresponding to this area can be parallel to the north-south direction, and the length of the signal routing can be reduced. , to reduce the insertion loss of high-speed signals.

In view of this, an embodiment of the present invention provides a packaging substrate for an integrated circuit, a ball grid array BGA is provided on one side of the packaging substrate, and the ball grid array includes a first BGA area and at least one second BGA area.

Wherein, the BGA solder balls in the first BGA area are arranged in a diamond shape along a first direction; the BGA solder balls in the second BGA area are arranged in a diamond shape along a second direction; the first direction is perpendicular to the second direction.

In an optional example, taking the four orientations of east, west, and northwest as an example, the first direction may be an east-west direction, and the second direction may be a north-south direction. Alternatively, taking the four directions of front, back, left, and right as an example, the first direction and the second direction may also refer to the front and rear directions and the left and right directions, respectively. This example is only an example, and it is not limited here. Under different orientation references, the definitions of the first direction and the second direction may be different.

In an optional embodiment, in the first BGA region, the distance between any two adjacent BGA solder balls is the same, and in the second BGA region, the distance between any two adjacent BGA solder balls is the same.

In an optional embodiment, in the ball grid array, the BGA solder balls are arranged to form several smallest rhombuses. The diagonal length of the smallest rhombus in the first direction in the first BGA area can be equal to the diagonal length of the smallest rhombus in the second direction in the second BGA area; similarly, the smallest rhombus in the first BGA area is in the second direction The diagonal length of the direction may be equal to the diagonal length of the smallest rhombus in the first direction in the second BGA area.

Referring to Fig. 5 , it is assumed that the smallest rhombus in the first BGA area is rhombus 1, and the smallest rhombus in the second BGA area is rhombus 2. Rhombus 1 and rhombus 2 have the same size but are placed in different orientations. Among them, the diagonal length of the smallest rhombus in the first direction in the first BGA area is D2, and the diagonal length of the smallest rhombus in the second direction in the first BGA area is D1; the smallest rhombus in the second BGA area is in the first direction. The length of the diagonal in the second direction is D3, and the length of the diagonal in the second direction of the smallest diamond in the second BGA area is D4. Then, D1=D3, D2=D4.

In an optional embodiment, the direction of the signal traces in the first BGA area may be consistent with the first direction. The direction of the signal traces in the second BGA area may be consistent with the second direction.

In an optional embodiment, one side of the substrate is a rectangle, and the second BGA area may be located at an edge area of any side parallel to the first direction in the rectangle.

For example, assume that a ball grid array includes a first BGA area and two second BGA areas, please refer to FIG. 6. In FIG. 6, several ball grid arrays include a number of BGA solder balls. All areas other than the second BGA area belong to the first BGA area.

On the basis of Figure 6, Figure 7 can be obtained by zooming in on the local area A. In Figure 7, it can be seen that: in the first BGA area, the direction of the signal routing can be parallel to the first direction shown in Figure 5; In the second BGA area, the direction of the signal traces can be parallel to the second direction shown in Figure 5, so that the length of the actual signal traces can be guaranteed to be the shortest, thereby reducing the insertion loss of high-speed signals.

It should be noted that the above examples in conjunction with FIG. 6 and FIG. 7 are only examples, and are not limited here.

In an optional embodiment, in the second BGA area or in the second BGA area, the distance between any two adjacent BGA solder balls can be a first value, and the first value can be but not limited to: 0.800 mm, 0.900mm, 1.000mm, etc. are not limited here.

In an optional embodiment, the diameter of each BGA solder ball in the ball grid array can be a second value, and the second value can be but not limited to: 0.500mm, 0.600mm, 0.700mm, etc., which is not limited here .

The present invention also provides an integrated circuit chip, which includes the packaging substrate of the integrated circuit described in the above-mentioned embodiments.

In an optional embodiment, in the composition of the integrated circuit chip, in addition to the packaging substrate (Substrate), it may also include metal bumps (Bumps), bare core layer (Silicon), thermal conductivity layer (TIM) and metal top cover (Lid).

Please refer to Figure 8. Figure 8 is a schematic cross-sectional view of an integrated circuit chip. It can be seen that one side of the substrate is a ball grid array composed of BGA solder balls, and a number of metal bumps are arranged on the other side of the substrate. There is a bare core layer covered with a thermally conductive layer covered with a metal top cover.

Wherein, the small balls under the bare core layer are metal bumps, and the metal bumps can be used to lead power, ground and signals on the bare core to external BGA solder balls through the packaging substrate.

In an optional example, the thermally conductive material used for the thermally conductive layer may be silicone grease or graphite material.

It can be understood that the structure shown in FIG. 8 is only for illustration, and the integrated circuit chip may include more or less components than those shown in FIG. 8 .

The present invention also provides a circuit board, which may include the above-mentioned integrated circuit chip.

The present invention also provides an electronic device, which may include the above-mentioned circuit board.

In summary, embodiments of the present invention provide an integrated circuit packaging substrate, an integrated circuit chip, a circuit board, and electronic equipment. One side of the packaging substrate is provided with a ball grid array BGA, and the ball grid array includes a first BGA area and at least one second BGA area; wherein, the solder balls in the first BGA area are arranged in a diamond shape along the first direction; the solder balls in the second BGA area are arranged in a diamond shape along the second direction; the first direction and the second Direction is vertical. The beneficial point is that the solder balls in the ball grid array are all arranged in a diamond shape, and under a uniform package size, the number of solder balls arranged in a diamond shape will be more than the number of solder balls arranged in a square shape. Moreover, in this solution, the BGA solder balls in the second BGA area are arranged in a rhombus in the second direction, which can reduce the size of the package substrate of the chip and meet the number of high-density solder balls required by the chip signal. The signal traces in the second BGA area are parallel to the second direction, so as to prove that the length of the actual signal traces can be the shortest, thereby reducing the insertion loss of high-speed signals.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (11)

1. A packaging substrate for an integrated circuit, characterized in that, one side of the packaging substrate is provided with a ball grid array BGA; the ball grid array includes a first BGA area and at least one second BGA area; Wherein, the BGA solder balls in the first BGA area are arranged in a diamond shape along a first direction; the BGA solder balls in the second BGA area are arranged in a diamond shape along a second direction; The two directions are vertical. 2 . The package substrate of an integrated circuit according to claim 1 , wherein the direction of the signal traces in the first BGA area is consistent with the first direction. 3 . 3 . The package substrate of an integrated circuit according to claim 1 , wherein, in the first BGA region, the distance between any two adjacent BGA solder balls is the same. 4 . 4 . The packaging substrate of an integrated circuit according to claim 1 , wherein the direction of the signal traces in the second BGA area is consistent with the second direction. 5. The packaging substrate of an integrated circuit according to claim 1 or 4, wherein one side of the substrate is rectangular, and the second BGA area is located on any side of the rectangle parallel to the first direction the edge area of In the second BGA region, the distance between any two adjacent BGA solder balls is the same. 6. The package substrate of integrated circuit as claimed in claim 1, wherein, in the second BGA region or in the second BGA region, the distance between any two adjacent BGA solder balls is first value. 7. The packaging substrate of an integrated circuit according to claim 1, wherein the diameter of the BGA solder ball is a second value. 8. An integrated circuit chip, characterized in that it comprises the packaging substrate of the integrated circuit according to any one of claims 1-7. 9. The integrated circuit chip according to claim 8, wherein a plurality of metal bumps are arranged on the other surface of the substrate, the metal bumps are covered with a bare core layer, and the bare core layer is covered with There is a thermally conductive layer covered with a metal top cover. 10. A circuit board, characterized in that it comprises the integrated circuit chip as claimed in claim 8 or 9. 11. An electronic device, comprising the circuit board according to claim 10.

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