CN117352373A - Preparation method of mask structure and preparation method of semiconductor device - Google Patents
Preparation method of mask structure and preparation method of semiconductor device Download PDFInfo
- Publication number
- CN117352373A CN117352373A CN202210761702.6A CN202210761702A CN117352373A CN 117352373 A CN117352373 A CN 117352373A CN 202210761702 A CN202210761702 A CN 202210761702A CN 117352373 A CN117352373 A CN 117352373A
- Authority
- CN
- China
- Prior art keywords
- layer
- region
- pattern
- mask
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 238000002360 preparation method Methods 0.000 title claims description 17
- 238000000034 method Methods 0.000 claims abstract description 104
- 238000005530 etching Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 15
- 230000000694 effects Effects 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000011068 loading method Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000000427 thin-film deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The embodiment of the disclosure provides a method for preparing a mask structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first area and a second area; forming a pattern transfer layer, a first mask layer and a second mask layer on a substrate; forming a plurality of first patterns in a second mask layer of the first region, wherein first grooves are formed between adjacent first patterns; forming a first sacrificial layer; forming a first backfill layer; removing the first backfill layer positioned on the top surface of the first pattern, and etching downwards along the first sacrificial layer positioned on the side wall of the first pattern to form a plurality of second patterns in the first mask layer of the first area, wherein second grooves are formed between adjacent second patterns; forming a second sacrificial layer; forming a second backfill layer; and removing the second backfill layer positioned on the top surface of the second pattern, etching downwards along the second sacrificial layer positioned on the side wall of the second pattern, and forming a plurality of third patterns in the pattern transfer layer on the first area.
Description
Technical Field
The embodiment of the disclosure relates to the field of semiconductor manufacturing, in particular to a preparation method of a mask structure and a preparation method of a semiconductor device.
Background
With the continuous development of semiconductor technology, the size of semiconductor devices is gradually reduced, and in order to improve the integration level of semiconductor devices, reverse Self-aligned quad pattern exposure (R-savp) process is generally used to form patterns on semiconductor devices.
The R-SAQP process can improve the process integration level of the semiconductor device and has obvious advantages in the aspect of reducing the size of the semiconductor device. However, in the implementation process, how to further improve the process reliability of the product becomes a bottleneck for restricting the development of the performance of the product.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a method for manufacturing a mask structure and a method for manufacturing a semiconductor device to solve at least one problem existing in the prior art.
In order to achieve the above object, the technical solution of the embodiments of the present disclosure is implemented as follows:
a first aspect of the present disclosure provides a method for preparing a mask structure, the method comprising:
providing a substrate comprising a first region and a second region;
forming a pattern transfer layer, a first mask layer and a second mask layer which are stacked in sequence from bottom to top on the substrate;
Patterning the second mask layer, forming a plurality of first patterns in the second mask layer on the first region, and forming first grooves between adjacent first patterns;
forming a first sacrificial layer, wherein the first sacrificial layer covers the first pattern, the surface of the first groove and the surface of the second mask layer on the second area;
forming a first backfill layer which fills the first groove and covers the top surface of the first sacrificial layer;
removing the first backfill layer positioned on the top surface of the first pattern, and etching downwards along the first sacrificial layer positioned on the side wall of the first pattern so as to form a plurality of second patterns in the first mask layer on the first area, wherein second grooves are formed between adjacent second patterns;
forming a second sacrificial layer, wherein the second sacrificial layer covers the surfaces of the second pattern and the second groove and the surface of the first mask layer on the second area;
forming a second backfill layer which fills the second groove and covers the top surface of the second sacrificial layer;
and removing the second backfill layer positioned on the top surface of the second pattern, and etching downwards along the second sacrificial layer positioned on the side wall of the second pattern so as to form a plurality of third patterns in the pattern transfer layer on the first region.
According to one embodiment of the present disclosure, the patterning the second mask layer includes: forming a photoresist layer in the first region and the second region; patterning the photoresist layer of the first region and leaving the photoresist layer of the second region to form a patterned photoresist layer in the first region; etching the second mask layer by using the patterned photoresist layer on the first region to form the first patterns in the second mask layer on the first region; the patterned photoresist layer of the first region and the photoresist layer of the second region are removed.
According to one embodiment of the present disclosure, the forming a first backfill layer includes: depositing a first backfill layer in the first region and the second region; the first backfill layer fills the first trench and covers the first sacrificial layer of the first region and the second region; the top of the first backfill layer of the first region is lower than the top of the first backfill layer of the second region.
According to one embodiment of the present disclosure, the removing the first backfill layer on the top surface of the first pattern includes: removing the first backfill layer of the first pattern top surface and the first backfill layer of the second region using a planarization process to make the first region and the second region flush; or removing the first sacrificial layer and the first backfill layer of the first pattern top surface and the first backfill layer and the first sacrificial layer of the second region by using a planarization process so as to make the first region and the second region flush.
According to one embodiment of the disclosure, the etching down along the first sacrificial layer located on the sidewall of the first pattern to form a plurality of second patterns in the first mask layer on the first region includes: removing the first sacrificial layer of the first pattern side wall to form a second initial groove exposing the first mask layer; and etching the first mask layer by utilizing the second initial groove so as to form a plurality of second patterns in the first mask layer on the first region.
According to one embodiment of the present disclosure, the first backfill layer and the second mask layer are of the same material, and the second mask layer and the first sacrificial layer are of different materials.
According to one embodiment of the present disclosure, the first mask layer includes a first sub-mask layer and a first stop layer, and the second mask layer includes a second sub-mask layer and a second stop layer; the first sub-mask layer and the second sub-mask layer have the same thickness.
According to one embodiment of the disclosure, the etching the first mask layer with the second initial trench to form a plurality of second patterns in the first mask layer on the first region includes: etching the second stop layer and the first stop layer exposed by the first region and the second stop layer of the second region; etching the second sub-mask layer, the first backfill layer and the first sub-mask layer exposed by the first region and the second sub-mask layer of the second region to form a plurality of second patterns in the first mask layer on the first region; the second trench exposes the pattern transfer layer.
According to one embodiment of the present disclosure, the first sacrificial layer, the second sacrificial layer, and the pattern transfer layer are the same material.
According to one embodiment of the present disclosure, the forming the second backfill layer includes: forming a second backfill layer in the first region and the second region, wherein the second backfill layer fills the second trench and covers the second sacrificial layer of the first region and the second region; the top of the second backfill layer of the first region is lower than the top of the second backfill layer of the second region.
According to one embodiment of the present disclosure, the second backfill layer and the first mask layer are the same material, and the first mask layer and the second sacrificial layer are different materials.
According to one embodiment of the present disclosure, the removing the second backfill layer on the top surface of the second pattern includes: removing the second backfill layer of the second pattern top surface and the second backfill layer of the second region using a planarization process to make the first region and the second region flush; or removing the second sacrificial layer and the second backfill layer on the top surface of the second pattern and the second sacrificial layer and the second backfill layer on the second region by using a planarization process so as to make the first region and the second region flush.
According to one embodiment of the present disclosure, the substrate includes a third stop layer, the pattern transfer layer being located on the third stop layer; the etching down along the second sacrificial layer located on the side wall of the second pattern to form a plurality of third patterns in the pattern transfer layer on the first area comprises the following steps: removing the second sacrificial layer of the second pattern sidewall to form a third initial trench exposing the pattern transfer layer; etching the pattern transfer layer by utilizing the third initial groove to form a plurality of third patterns in the pattern transfer layer on the first area; and a third groove is arranged between the adjacent third patterns, and the third groove exposes the third stop layer.
According to one embodiment of the present disclosure, the density of the plurality of second patterns is twice the density of the plurality of first patterns; the density of the third patterns is twice that of the second patterns.
A second aspect of the present disclosure provides a method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a layer to be etched;
Forming the plurality of third patterns on the layer to be etched by adopting the preparation method of the mask structure;
and etching the etching layer based on the third patterns so as to transfer the patterns of the third patterns into the layer to be etched.
According to one embodiment of the disclosure, the layer to be etched comprises a metal layer.
The embodiment of the disclosure provides a preparation method of a mask structure and a preparation method of a semiconductor device, wherein the method comprises the following steps: providing a substrate comprising a first region and a second region; forming a pattern transfer layer, a first mask layer and a second mask layer which are stacked in sequence from bottom to top on the substrate; patterning the second mask layer, forming a plurality of first patterns in the second mask layer on the first region, and forming first grooves between adjacent first patterns; forming a first sacrificial layer, wherein the first sacrificial layer covers the first pattern, the surface of the first groove and the surface of the second mask layer on the second area; forming a first backfill layer which fills the first groove and covers the top surface of the first sacrificial layer; removing the first backfill layer positioned on the top surface of the first pattern, and etching downwards along the first sacrificial layer positioned on the side wall of the first pattern so as to form a plurality of second patterns in the first mask layer on the first area, wherein second grooves are formed between adjacent second patterns; forming a second sacrificial layer, wherein the second sacrificial layer covers the surfaces of the second pattern and the second groove and the surface of the first mask layer on the second area; forming a second backfill layer which fills the second groove and covers the top surface of the second sacrificial layer; and removing the second backfill layer positioned on the top surface of the second pattern, and etching downwards along the second sacrificial layer positioned on the side wall of the second pattern so as to form a plurality of third patterns in the pattern transfer layer on the first region.
According to the embodiment of the disclosure, the first filling layer is formed to fill the first grooves between the adjacent first patterns and cover the first sacrificial layer, and after the first filling layer on the top surface of the first pattern is removed, the first sacrificial layer located on the side wall of the first pattern is etched downwards to form the second pattern in the first mask layer of the first region, so that the top of the first mask layer of the second region is basically flush with the top of the second pattern of the first region, namely, the heights of the first region forming a pattern with a certain density and the second region not forming the pattern after the R-SAQP process is performed are unified, and therefore the process effect difference between the two regions caused by the height difference between the first region and the second region in the subsequent process can be avoided.
Drawings
FIGS. 1 a-1 h are schematic views illustrating a process for fabricating a mask structure according to an embodiment of the present disclosure;
fig. 2 is a schematic flow chart of a method for manufacturing a mask structure according to an embodiment of the disclosure;
fig. 3 a-3 p are schematic views illustrating a preparation process of another mask structure according to an embodiment of the disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Fig. 1a to 1h are schematic views illustrating a preparation process of a mask structure according to an embodiment of the disclosure. As shown in fig. 1a, the structure includes a substrate 100, and a pattern transfer layer 140 and a first mask layer 150 sequentially stacked on the substrate 100. Wherein the substrate 100 includes a layer to be etched 110, a third mask layer 120 and a third stop layer 130 stacked in sequence from bottom to top, and the substrate 100 includes a first region 101 and a second region 102. The pattern to be formed is formed on the pattern transfer layer 140, and then the pattern is transferred from the pattern transfer layer 140 to the layer to be etched 110. Wherein, the pattern density of the pattern to be formed on the pattern transfer layer 140 of the first region 101 is greater than the pattern density of the pattern to be formed on the pattern transfer layer 140 of the second region 102.
Illustratively, dynamic random access memory (Dynamic Random Access Memory, DRAM) generally includes an array region and a peripheral region. Because of the requirement of product performance, a pattern with a larger density needs to be formed in an array area, and a pattern with a smaller density needs to be formed in a peripheral area, and this difference in pattern density may cause a loading effect (loading effect) on the process, so that the pattern at the boundary of the array area is abnormal or defective. Thus, the first area 101 may be an array area and a peripheral area of the DRAM where dummy is set, and the second area 102 may be an area of the DRAM where dummy cannot be set.
A number of first patterns 260 are provided on the first mask layer 150 of the first region 101. In some embodiments, the first graphic 260 may include a mandrel structure (mandril). The first graphic 260 includes a first portion 261 and a second portion 262. Here, the plurality of first patterns 260 constitute a patterned second mask layer. The adjacent first patterns 260 have first trenches 241 therebetween, and the first trenches 241 expose the first mask layer 150 of the first region 101. A second mask layer 160 is disposed on the first mask layer 150 of the second region 102, the second mask layer 160 including a second sub-mask layer 161 and a second stop layer 162. Wherein the first portion 261 of the first pattern 260 and the second sub-mask layer 161 are the same in material and thickness, and the second portion 262 and the second stop layer 162 are the same in material and thickness.
A Reverse Self-aligned quadruple pattern exposure (R-SAQP) process is used herein to form a pattern on the pattern transfer layer 140. The R-SAQP process includes a Self-aligned double pattern exposure (Self-Aligned Double Patterning, SADP) process and a Reverse Self-aligned double pattern exposure (Reverse Self-Aligned Double Patterning, R-SADP) process.
FIGS. 1 b-1 d are schematic diagrams illustrating the SADP process. As shown in fig. 1b, a first sacrificial layer 170 is formed. The first sacrificial layer 170 covers the surfaces of the first pattern 260 and the first trench 241, and the surface of the second mask layer 160 on the second region 102.
As shown in fig. 1c, the first sacrificial layer on top of the first pattern 260 is etched away. The first sacrificial layer on the first trench surface of the first region 101 and the first sacrificial layer on the second mask layer 160 of the second region 102 are removed at the same time as the first sacrificial layer on the top of the first pattern 260 is etched. The first pattern 260 is then removed. Since the material and thickness of the first pattern 260 and the second mask layer 160 are the same, the second mask layer 160 on the second region 102 is removed at the same time as the first pattern 260 is removed. In the first region 101, the first sacrificial layer of the sidewall of the first pattern 260 remains, and a sidewall structure 171 (spacer) is formed.
As shown in fig. c and fig. 1d, the first mask layer 150 is etched with the sidewall structure 171 as a mask, so as to form a plurality of second patterns 250. The second trenches 242 are provided between adjacent second patterns 250, and the second trenches 242 expose the pattern transfer layer 140 of the first region 101. The second pattern 250 includes a first portion 251 and a second portion 252, and the first mask layer 150 includes the first sub-mask layer 151 and the first stop layer 152. Wherein the first portion 251 and the first sub-mask layer 151 are the same material and thickness, and the second portion 252 and the first stop layer 152 are the same material and thickness. Therefore, the first mask layer 150 of the second region 102 is removed to expose the pattern transfer layer 140 of the second region 102 while the second pattern 250 is formed by etching the first mask layer 150 of the first region 101 through the sidewall structure 171. This results in the top of the pattern transfer layer 140 of the second region 102 being lower than the top of the second pattern 250. Therefore, in the subsequent process, the pattern transfer layer 140 of the second region 102 and the partial layer structure (such as the third mask layer 120 and the layer to be etched 110) below the pattern transfer layer 140 of the first region 101 may be damaged before the pattern transfer layer 140 is not patterned.
FIGS. 1 e-1 h are process diagrams of R-SADP process. As shown in fig. 1e, a second sacrificial layer 180 is formed. The second sacrificial layer 180 covers the surfaces of the second pattern 250 and the second trench 242, and the pattern transfer layer 140 of the second region 102. The second sacrificial layer 180 is the same material as the pattern transfer layer 140. In other embodiments, the second sacrificial layer 180 is a different material than the pattern transfer layer 140. At this time, there is a large difference in height between the first region and the second region.
As shown in fig. 1f, a backfill layer 190 is formed. The backfill layer 190 fills between the second patterns 250 and covers the pattern transfer layer 140 of the second region 102. As described above, since there is a large height difference between the first region 101 and the second region 102, the top of the backfill layer of the subsequently formed first region 101 is higher than the top of the backfill layer of the second region 102.
As shown in fig. 1g, the second sacrificial layer on the top and sidewalls of the second pattern 250 is etched to form a trench, and the pattern transfer layer is etched down along the trench on the sidewalls of the second pattern. During the etching process of the first region 101, a part of the layer structure of the second region 102 is also etched and removed, and since the top of the backfill layer of the second region 102 is lower than the top of the backfill layer of the first region 101, the third stop layer 130 and the third mask layer 120 of the second region 102 are damaged when the pattern transfer layer is continuously etched down along the trench of the second pattern sidewall.
As shown in fig. 1h, the backfill layer and the second pattern on the pattern transfer layer 140 of the first region 101 are removed. At the same time, part of the layer structure of the second region 102 is also removed. As described above, since the third stop layer 130 and the third mask layer 120 of the second region 102 have been damaged, the backfill layer and the second pattern on the pattern transfer layer 140 of the first region 101 may be removed at the same time, and the third mask layer with smaller thickness on the second region 102 may be directly removed, thereby damaging the layer 110 to be etched below.
For this reason, the embodiment of the disclosure provides a method for preparing a mask structure. Fig. 2 is a flow chart of a method for manufacturing a mask structure according to an embodiment of the disclosure. Fig. 3 a-3 p are schematic views illustrating a preparation process of another mask structure according to an embodiment of the disclosure. The method for preparing the mask structure according to the embodiments of the present disclosure will be described below with reference to fig. 3a to 3 p. The R-SAQP process provided by the embodiments of the present disclosure includes a twice R-SADP process. FIGS. 3 a-3 j are schematic diagrams illustrating the first R-SADP process. In step 201, a substrate is provided. As shown in fig. 3a, a substrate 100 is provided, the substrate 100 comprising a first region 101 and a second region 102. The first region 101 and the second region 102 may be adjacent or non-adjacent regions.
The substrate 100 includes a layer to be etched 110, a third mask layer 120, and a third stop layer 130, which are sequentially stacked from bottom to top. Wherein the layer to be etched may comprise a metal layer, the material of which includes, but is not limited to, tungsten (W). The material of the third mask layer 120 includes, but is not limited to, amorphous carbon (Amorphous Carbon Layer, ACL), silicon oxynitride (SiON), polysilicon (Poly), oxide (Oxide), or the like. Materials for the third stop layer 130 include, but are not limited to, silicon oxynitride, silicon oxide, silicon nitride, and polysilicon.
In step 202, a pattern transfer layer, a first mask layer, and a second mask layer, which are sequentially stacked from bottom to top, are formed on a substrate. As shown in fig. 3b, a pattern transfer layer 140, a first mask layer 150, and a second mask layer 160, which are sequentially stacked from bottom to top, are formed on the substrate 100. Wherein the material of the pattern transfer layer 140 includes, but is not limited to, oxide and polysilicon. The first mask layer 150 includes a first sub-mask layer 151 and a first stop layer 152, wherein materials of the first sub-mask layer 151 include, but are not limited to, spin On hard mask (SOH), which may be formed by a Spin On process. Materials for the first stop layer 152 include, but are not limited to, silicon oxynitride, silicon oxide, silicon nitride, and polysilicon. In some embodiments, the first stop layer 152 and the third stop layer 130 are the same material. In practice, the first sub-mask layer 151 may be formed by a spin-coating process, and then the first stop layer 152 may be deposited on the first sub-mask layer 151 to form the first mask layer 150, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), plasma-Enhanced CVD (PECVD), sputtering (sputtering), metal-organic chemical vapor deposition (Metal-Organic Chemical Vapor Deposition, MOCVD), or atomic layer deposition (Atomic Layer Deposition, ALD).
The second mask layer 160 includes a second sub-mask layer 161 and a second stop layer 162. In some embodiments, the second sub-mask layer 161 and the first sub-mask layer 151 are both the same material and thickness. The second stop layer 162 and the first stop layer 152 are the same material and thickness. In practical applications, the second mask layer 160 may be formed by a similar procedure to that of the first mask layer 150, which is not described herein.
In step 203, the second mask layer is patterned, and a plurality of first patterns are formed in the second mask layer over the first regions. As shown in fig. 3c, a photoresist layer 210 is formed in the first region 101 and the second region 102, and then the photoresist layer of the first region 101 is patterned and the photoresist layer of the second region remains to form a patterned photoresist layer 211 in the first region 101. The patterned photoresist layer 211 has an opening exposing the second mask layer 160.
As shown in fig. 3d, the second mask layer 160 is etched using the patterned photoresist layer 211 on the first region 101 to form a number of first patterns 260 in the second mask layer of the first region 101. Here, the plurality of first patterns 260 on the first region 101 constitute a patterned second mask layer. The adjacent first patterns 260 have first trenches 241 therebetween, and the first trenches 241 expose the first mask layer 150 of the first region 101. The first pattern 260 includes a first portion 261 and a second portion 262, the first portion 261 and the second sub-mask layer 161 are the same in material and thickness, and the second portion 262 and the second stop layer 162 are the same in material and thickness. Illustratively, the second mask layer 160 may be wet etched and/or dry etched (e.g., reactive ion etching (Reactive Ion Etching, RIE)) using the patterned photoresist layer 211 to form a number of first patterns 260. It should be noted that the number of the first patterns 260 in the drawing is merely used to describe the embodiment of the present disclosure, and is not used to limit the number of the first patterns 260, and the number of the first patterns 260 may be set according to actual requirements. After forming the plurality of first patterns 260, the patterned photoresist layer 211 of the first region 101 and the photoresist layer 210 of the second region 102 are removed.
In step 204, a first sacrificial layer is formed. As shown in fig. 3e, the first sacrificial layer 170 covers the surfaces of the first pattern 260 and the first trench 241, and the surface of the second mask layer 160 of the second region 102. The material of the first sacrificial layer 170 includes, but is not limited to, oxide. The materials of the first sacrificial layer 170 and the second mask layer 160 are different. The first sacrificial layer 170 may be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or a combination thereof.
In step 205, a first backfill layer is formed. As shown in fig. 3f, a first backfill layer 220 is deposited over the first region 101 and the second region 102. Wherein the first backfill layer 220 fills the first trench and covers the first sacrificial layer 170 of the first region 101 and the second region 102. The first patterns 260 exist in the first region 101, and the deposited first backfill layer fills the first trenches between the first patterns 260, so that the top of the first backfill layer of the finally formed first region 101 is lower than the top of the first backfill layer of the second region 102. The first backfill layer 220 and the second mask layer 160 are the same material. In some embodiments, the first backfill layer 220 and the second sub-mask layer 161 are the same material. In other embodiments, the first backfill layer 220 and the second stop layer 162 are the same material. The first backfill layer 220 can be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or a combination thereof.
In step 206, the first sacrificial layer on the top surface of the first pattern is removed and etched down along the first sacrificial layer on the sidewalls of the first pattern to form a plurality of second patterns in the first mask layer over the first region.
As shown in fig. 3f and 3g, the first backfill layer 220 and the first sacrificial layer 170 on the top surface of the first pattern 260, and the first backfill layer 220 and the first sacrificial layer 170 of the second region 102 are removed using a planarization process such that the first region 101 and the second region 102 are flush.
In some embodiments, the first region 101 and the second region 102 may be planarized by a chemical mechanical polishing (chemical mechanical polish, CMP) process to remove the first backfill layer 220 and the first sacrificial layer 170 on the top surface of the first pattern 260, and the first backfill layer 220 and the first sacrificial layer 170 of the second region 102, thereby forming the structure shown in fig. 3g, in which the planarized first backfill layer 220 'fills between the respective first trenches 241, and the planarized first backfill layer 220' is not higher than the first pattern 260. In other embodiments, the first backfill layer 220 and the first sacrificial layer 170 on the top surface of the first pattern 260, and the first backfill layer 220 and the first sacrificial layer 170 of the second region 102 may be removed by etching back.
In some embodiments, a planarization process may also be utilized to remove the first backfill layer 220 on top of the first pattern 260 and the second backfill layer 220 of the second region 102. And the first sacrificial layer 170 on the top surface of the first pattern 260 and the first sacrificial layer 170 of the second region 102 may be removed together in a subsequent step of removing the first sacrificial layer of the sidewall of the first pattern 260.
The first sacrificial layer located along the sidewalls of the first pattern 260 is etched down to form a number of second patterns in the first mask layer 150 over the first region 101. As shown in fig. 3h, the first sacrificial layer of the sidewalls of the first pattern 260 is removed to form a second initial trench 242' exposing the first mask layer 150 of the first region 101. And the first sacrificial layer at the bottom of the first backfill layer 220' after the planarization process is preserved. The second initial trench 242' exposes the first mask layer 150. Since the second preliminary trenches 242 'are formed by removing the first sacrificial layer of the sidewalls of the first patterns 260, the number of the second preliminary trenches 242' is twice the number of the first trenches 241 between adjacent first patterns 260. In some embodiments, the first sacrificial layer of the sidewalls of the first pattern 260 may be removed using, for example, wet etching and/or dry etching.
The first mask layer 150 is etched using the second initial trench 242' to form a number of second patterns 250 in the first mask layer 150 over the first region 101.
The second stop layer 162 and the first stop layer 152 exposed by the first region 101 and the second stop layer 162 of the second region 102 are etched to expose the first sub-mask layer 151 of the first region 101 and the second sub-mask layer 161 of the second region 102, as shown in fig. 3 i.
The exposed second sub-mask layer 261, the first backfill layer 220' and the first sub-mask layer 151 of the first region 101, and the second sub-mask layer 161 of the second region 102 are etched to form a number of second patterns 250 in the first mask layer over the first region 101, as shown in fig. 3 j. The second trenches 242 are provided between adjacent second patterns 250, and the second trenches 242 expose the pattern transfer layer 140 of the first region 101. In some embodiments, the materials of the second sub-mask layer 261, the first sub-mask layer 151, and the first backfill layer 220 'are the same, and thus, the exposed second sub-mask layer 261, the exposed first sub-mask layer 220', and the exposed first sub-mask layer 151 of the first region 101, and the exposed second sub-mask layer 161 of the second region 102 may be removed in the same etching process. Here, the plurality of second patterns 250 on the first region 101 constitute a patterned first mask layer. The second graphic 250 includes a first portion 251 and a second portion 252. The first portion 251 of the second pattern 250 and the first sub-mask layer 151 are the same material and thickness, and the second portion 252 of the second pattern 250 and the first stop layer 152 are the same material and thickness. The top of the second pattern 250 is substantially flush with the top of the first mask layer 150 of the second region 102. Since the second patterns 250 are formed by etching the second initial trenches 242', the number of second trenches 242 between adjacent second patterns 250 is the same as the number of second initial trenches 242'. As described above, the number of the second preliminary grooves 242' is twice the number of the first grooves 241, and thus the number of the second grooves 242 is twice the number of the first grooves 241, that is, the density of the plurality of second patterns 250 is twice the density of the plurality of first patterns 260. The number of second patterns 250 in the figures is used only to describe embodiments of the present disclosure and is not intended to limit the number of second patterns 250. It should be noted that, there may be a residual first sacrificial layer (not shown in the figure) on a portion of the second pattern 250.
Compared to the structure shown in fig. 1d, the first mask layer of the second region 102 is removed, exposing the pattern transfer layer 140, and a larger height difference exists between the first region 101 and the second region 102, i.e. the top of the second pattern 250 of the first region 101 is higher than the top of the pattern transfer layer of the second region 102. The top of the second pattern 250 of the first region 101 of the structure formed in fig. 3j is substantially flush with the top of the first mask layer 150 of the second region 102, that is, the heights of the first region and the second region in the structure formed by the first R-SADP process of the R-SADP process provided by the embodiments of the present disclosure are substantially uniform, so that it is avoided that the process effect of the first region 101 and the second region 102 is different during the subsequent process (e.g., the second R-SADP process of the R-SADP process) due to the large difference in height between the first region 101 and the second region 102, before the pattern transfer layer 140 of the first region 101 is not patterned.
In step 207, a second sacrificial layer is formed. FIGS. 3 k-3 p are schematic diagrams illustrating the second R-SADP process. As shown in fig. 3k, a second sacrificial layer 240 is deposited over the first region 101 and the second region 102. Wherein the second sacrificial layer 240 covers the surfaces of the second pattern 250 and the second trench 242, and the surface of the first mask layer 150 of the second region 102. The second sacrificial layer 240 and the first mask layer 150 are of different materials. In some embodiments, the materials of the second sacrificial layer 240, the first sacrificial layer 170, and the pattern transfer layer 140 are all the same. In other embodiments, the materials of the second sacrificial layer 240 and the pattern transfer layer 140 are different. The second sacrificial layer 240 may be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or a combination thereof.
In step 208, a second backfill layer is formed. The method of forming the second backfill layer is similar to the method of forming the first backfill layer, as illustrated in fig. 3l, with the second backfill layer 230 deposited over the first region 101 and the second region 102. Wherein the second backfill layer 230 fills the second trench and covers the second sacrificial layer 240 over the first region 101 and the second region 102. The second patterns 250 exist in the first region 101, and the deposited second backfill layer fills the second trenches between the second patterns 250, such that the top of the second backfill layer of the finally formed first region 101 is lower than the top of the second backfill layer of the second region 102. The second backfill layer 230 is the same material as the first mask layer 150. In some embodiments, the second backfill layer 230 and the first sub-mask layer 151 are the same material. In other embodiments, the material of the second backfill layer 230 is the same as the material of the first stop layer 152. The second backfill layer 230 can be deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, any other suitable process, or a combination thereof.
In step 209, the second backfill layer on top of the second pattern is removed and etched down along the second sacrificial layer on the sidewalls of the second pattern to form a number of third patterns in the pattern transfer layer over the first region.
As shown in fig. 3m, the second backfill layer 230 and the second sacrificial layer 240 on top of the second pattern 250, and the second backfill layer 230 and the second sacrificial layer 240 of the second region 102 are removed using a planarization process such that the first region 101 and the second region 102 are flush.
In some embodiments, the first region 101 and the second region 102 may be subjected to a planarization process by a CMP process to remove the second backfill layer 230 and the second sacrificial layer 240 on the top surface of the second pattern 250, and the second backfill layer 230 and the second sacrificial layer 240 of the second region 102, so as to form the structure shown in fig. 3m, in which the planarized second backfill layer 230 'fills each of the second trenches 242 in the first region of the structure, and the planarized second backfill layer 230' is not higher than the second pattern 250. In other embodiments, the second backfill layer 230 and the second sacrificial layer 240 on top of the second pattern 250, and the second backfill layer 230 and the second sacrificial layer 240 of the second region 102, may be removed by an etch back such that the first region 101 and the second region 102 are flush.
In some embodiments, the second backfill layer 230 on top of the second pattern 250 and the second backfill layer 230 of the second region 102 can also be removed using a planarization process to level the first region 101 and the second region 102. And the second sacrificial layer 240 on the top surface of the second pattern 250 and the second sacrificial layer 240 of the second region 102 may be removed together in a subsequent step of removing the second sacrificial layer on the sidewalls of the second pattern 250.
The second sacrificial layer located along the sidewalls of the second pattern 250 is etched down to form a number of third patterns in the pattern transfer layer 140 on the first region 101. As shown in fig. 3n, the second sacrificial layer of the sidewalls of the second pattern 250 is removed to form a third initial trench 243' exposing the pattern transfer layer 140 on the first region 101. Since the third preliminary trenches 243 'are formed by removing the second sacrificial layer of the sidewalls of the second patterns 250, the number of the third preliminary trenches 243' is twice the number of the second trenches 242 between adjacent second patterns 250. In some embodiments, the second sacrificial layer of the sidewalls of the second pattern 250 may be removed using, for example, wet etching and/or dry etching.
As shown in fig. 3o, the pattern transfer layer 140 is etched using the third preliminary trench 243' to form a number of third patterns 141 in the pattern transfer layer on the first region 101. The third trenches 243 are formed between the adjacent third patterns 141, and the third trenches 243 expose the third stop layer 130. Since the third patterns 141 are formed by the third preliminary trenches 243' etching, the number of third trenches 243 between adjacent third patterns 141 is the same as the number of third preliminary trenches 243', and as previously described, the number of third preliminary trenches 243' is twice the number of second trenches 242, so the number of third trenches 243 is twice the number of second trenches 242, that is, the density of the plurality of third patterns 141 is twice the density of the plurality of second patterns 250.
As shown in fig. 3p, the second pattern 250 and the second backfill layer 230' of the first region 101 and the first mask layer 150 of the second region 102 are removed. Illustratively, the first stop layer 152 exposed by the first region 101 and the first stop layer 152 of the second region 102 may be etched. The first and second sub-mask layers 151 and 230' exposed by the first region 101 and the first sub-mask layer 151 of the second region 102 are then removed. Since the second backfill layer 230 'and the first sub-mask layer 151 are the same material, the second backfill layer 230' and the first sub-mask layer 151 can be removed in the same step. In some embodiments, the second backfill layer 230' and the first sub-mask layer 151 may be removed by an ashing process (ASH).
In contrast to the structures shown in fig. 1g and 1h described above, the structure shown in fig. 3p does not damage the pattern transfer layer 140 of the second region 102 and the underlying layer structures (e.g., the third mask layer 120 and the layer to be etched 110) when forming the third pattern 141 in the pattern transfer layer 140 of the first region 101. The present disclosure forms a mask structure using an R-SADP process including two R-SADP processes such that the first region 101 of the structure formed by the first R-SADP process is substantially flush with the top of the second region 102, thereby avoiding damage to the pattern transfer layer 140 of the second region 102 and the underlying layer structure (e.g., the third mask layer 120 and the layer to be etched 110) thereof during subsequent processes, which may be caused by a large height difference between the first region 101 and the second region 102, before the third pattern is formed in the pattern transfer layer 140 of the first region 101.
According to the preparation method of the mask structure, whether the R-SADP process or the R-SAQP process is executed, the heights of the first area and the second area with different pattern densities can be unified, and no process effect difference exists, so that the process effect difference caused by a loading effect (loading effect) due to different pattern densities is not required to be compensated by adding a dummy, and defects caused by adding the dummy can be avoided based on the process effect difference.
In some embodiments, the layer to be etched 110 may be etched through the third pattern 141 to pattern the layer to be etched 110. Illustratively, the third stop layer 130 may be etched with the third trench 243 and the third mask layer 120 and the layer to be etched 110 may be continued to be etched down to form a fourth trench extending into the layer to be etched 110. The depth of the fourth trench may be controlled by controlling the etching time and/or the etching rate.
In some embodiments, the third pattern formed by the above method may be subsequently used to form an array pattern, such as a landing pad (landing pad), a Node Contact (NC), or a buried word line (BW), etc.
The embodiment of the disclosure also provides a method for preparing the semiconductor device, which comprises the following steps:
Providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a layer to be etched;
forming a plurality of third patterns on the layer to be etched by adopting the preparation method of the mask structure;
and etching the layer to be etched based on the third patterns so as to transfer the patterns of the third patterns into the layer to be etched.
Here, the plurality of third patterns are formed in the mask layer on the layer to be etched, in other words, the mask layer with the plurality of third patterns is formed on the layer to be etched by adopting the preparation method of the mask structure, so that the layer to be etched is etched based on the mask layer with the plurality of third patterns, and the plurality of third patterns are transferred into the layer to be etched.
In some embodiments, the method for preparing the mask structure may be used one or more times to form a plurality of third patterns distributed at intervals along different directions on the layer to be etched, so that the hole-shaped or columnar patterns are formed by overlapping the plurality of third patterns distributed at intervals along different directions.
In some embodiments, the layer to be etched comprises a metal layer, the material of which includes, but is not limited to, metallic tungsten (W).
The embodiment of the disclosure also provides a semiconductor device, which is manufactured by adopting the manufacturing method of the semiconductor device. The semiconductor device may be a memory chip, e.g. a DRAM chip, but of course other semiconductor devices are also possible, which are not listed here. The beneficial effects of the semiconductor device can refer to the beneficial effects of the preparation method of the mask structure, and are not described herein.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (16)
1. A method for manufacturing a mask structure, the method comprising:
providing a substrate comprising a first region and a second region;
forming a pattern transfer layer, a first mask layer and a second mask layer which are stacked in sequence from bottom to top on the substrate;
patterning the second mask layer, forming a plurality of first patterns in the second mask layer on the first region, and forming first grooves between adjacent first patterns;
forming a first sacrificial layer, wherein the first sacrificial layer covers the first pattern, the surface of the first groove and the surface of the second mask layer on the second area;
forming a first backfill layer which fills the first groove and covers the top surface of the first sacrificial layer;
removing the first backfill layer positioned on the top surface of the first pattern, and etching downwards along the first sacrificial layer positioned on the side wall of the first pattern so as to form a plurality of second patterns in the first mask layer on the first area, wherein second grooves are formed between adjacent second patterns;
forming a second sacrificial layer, wherein the second sacrificial layer covers the surfaces of the second pattern and the second groove and the surface of the first mask layer on the second area;
Forming a second backfill layer which fills the second groove and covers the top surface of the second sacrificial layer;
and removing the second backfill layer positioned on the top surface of the second pattern, and etching downwards along the second sacrificial layer positioned on the side wall of the second pattern so as to form a plurality of third patterns in the pattern transfer layer on the first region.
2. The method of claim 1, wherein patterning the second mask layer comprises:
forming a photoresist layer in the first region and the second region;
patterning the photoresist layer of the first region and leaving the photoresist layer of the second region to form a patterned photoresist layer in the first region;
etching the second mask layer by using the patterned photoresist layer on the first region to form the first patterns in the second mask layer on the first region;
the patterned photoresist layer of the first region and the photoresist layer of the second region are removed.
3. The method of claim 1, wherein forming the first backfill layer comprises:
Depositing a first backfill layer in the first region and the second region; the first backfill layer fills the first trench and covers the first sacrificial layer of the first region and the second region; the top of the first backfill layer of the first region is lower than the top of the first backfill layer of the second region.
4. The method for manufacturing a mask structure according to claim 1, wherein the removing the first backfill layer on the top surface of the first pattern comprises:
removing the first backfill layer of the first pattern top surface and the first backfill layer of the second region using a planarization process to make the first region and the second region flush; or (b)
And removing the first sacrificial layer and the first backfill layer of the first pattern top surface and the first backfill layer and the first sacrificial layer of the second region by using a planarization process so that the first region and the second region are flush.
5. The method of claim 1, wherein etching down the first sacrificial layer along the sidewall of the first pattern to form a plurality of second patterns in the first mask layer on the first region comprises:
Removing the first sacrificial layer of the first pattern side wall to form a second initial groove exposing the first mask layer;
and etching the first mask layer by utilizing the second initial groove so as to form a plurality of second patterns in the first mask layer on the first region.
6. The method of claim 5, wherein the first backfill layer and the second mask layer are of the same material and the second mask layer and the first sacrificial layer are of different materials.
7. The method of claim 6, wherein the first mask layer comprises a first sub-mask layer and a first stop layer, and the second mask layer comprises a second sub-mask layer and a second stop layer; the first sub-mask layer and the second sub-mask layer have the same thickness.
8. The method for preparing a mask structure according to claim 7, wherein etching the first mask layer by using the second initial trench to form a plurality of second patterns in the first mask layer on the first region comprises:
etching the second stop layer and the first stop layer exposed by the first region and the second stop layer of the second region;
Etching the second sub-mask layer, the first backfill layer and the first sub-mask layer exposed by the first region and the second sub-mask layer of the second region to form a plurality of second patterns in the first mask layer on the first region; the second trench exposes the pattern transfer layer.
9. The method of claim 1, wherein the first sacrificial layer, the second sacrificial layer, and the pattern transfer layer are the same material.
10. The method of claim 6, wherein forming the second backfill layer comprises:
forming a second backfill layer in the first region and the second region, wherein the second backfill layer fills the second trench and covers the second sacrificial layer of the first region and the second region; the top of the second backfill layer of the first region is lower than the top of the second backfill layer of the second region.
11. The method of claim 10, wherein the second backfill layer and the first mask layer are of the same material and the first mask layer and the second sacrificial layer are of different materials.
12. The method for manufacturing a mask structure according to claim 1, wherein the removing the second backfill layer on the top surface of the second pattern comprises:
removing the second backfill layer of the second pattern top surface and the second backfill layer of the second region using a planarization process to make the first region and the second region flush; or (b)
And removing the second sacrificial layer and the second backfill layer on the top surface of the second graph and the second sacrificial layer and the second backfill layer of the second region by using a planarization process so as to enable the first region and the second region to be flush.
13. The method of claim 1, wherein the substrate comprises a third stop layer, the pattern transfer layer being on the third stop layer; the etching down along the second sacrificial layer located on the side wall of the second pattern to form a plurality of third patterns in the pattern transfer layer on the first area comprises the following steps:
removing the second sacrificial layer of the second pattern sidewall to form a third initial trench exposing the pattern transfer layer;
Etching the pattern transfer layer by utilizing the third initial groove to form a plurality of third patterns in the pattern transfer layer on the first area; and a third groove is arranged between the adjacent third patterns, and the third groove exposes the third stop layer.
14. The method of claim 1, wherein the density of the plurality of second patterns is twice the density of the plurality of first patterns; the density of the third patterns is twice that of the second patterns.
15. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a layer to be etched;
forming the third patterns on the layer to be etched by adopting the preparation method of the mask structure according to any one of claims 1-14;
and etching the layer to be etched based on the third patterns so as to transfer the patterns of the third patterns into the layer to be etched.
16. The method of manufacturing a semiconductor device according to claim 15, wherein the layer to be etched comprises a metal layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210761702.6A CN117352373A (en) | 2022-06-29 | 2022-06-29 | Preparation method of mask structure and preparation method of semiconductor device |
| PCT/CN2022/124062 WO2024000912A1 (en) | 2022-06-29 | 2022-10-09 | Preparation method for mask structure and preparation method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210761702.6A CN117352373A (en) | 2022-06-29 | 2022-06-29 | Preparation method of mask structure and preparation method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117352373A true CN117352373A (en) | 2024-01-05 |
Family
ID=89354532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210761702.6A Pending CN117352373A (en) | 2022-06-29 | 2022-06-29 | Preparation method of mask structure and preparation method of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117352373A (en) |
| WO (1) | WO2024000912A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100877111B1 (en) * | 2007-10-04 | 2009-01-07 | 주식회사 하이닉스반도체 | How to form a fine pattern |
| US20090246706A1 (en) * | 2008-04-01 | 2009-10-01 | Applied Materials, Inc. | Patterning resolution enhancement combining interference lithography and self-aligned double patterning techniques |
| CN111508826B (en) * | 2019-01-31 | 2024-02-27 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method |
| CN111524793B (en) * | 2019-02-01 | 2023-12-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method |
| CN112017948B (en) * | 2019-05-28 | 2023-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2022
- 2022-06-29 CN CN202210761702.6A patent/CN117352373A/en active Pending
- 2022-10-09 WO PCT/CN2022/124062 patent/WO2024000912A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024000912A1 (en) | 2024-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI471981B (en) | Method for fabricating memory device with buried digit lines and buried word lines | |
| US5518948A (en) | Method of making cup-shaped DRAM capacitor having an inwardly overhanging lip | |
| TWI579230B (en) | Method for forming a pattern | |
| US20050070094A1 (en) | Semiconductor device having multilayer interconnection structure and manufacturing method thereof | |
| US7476613B2 (en) | Method of forming an electrical contact in a semiconductor device using an improved self-aligned contact (SAC) process | |
| US11217457B2 (en) | Method of fabricating a semiconductor device | |
| US20220028730A1 (en) | Semiconductor structure and method for manufacturing same | |
| KR100219483B1 (en) | Method for manufacturing capacitor of semiconductor device | |
| CN113097145A (en) | Preparation method of semiconductor structure and semiconductor structure | |
| KR102327667B1 (en) | Methods of manufacturing semiconductor devices | |
| US7560370B2 (en) | Method for manufacturing semiconductor device | |
| CN117352373A (en) | Preparation method of mask structure and preparation method of semiconductor device | |
| US11538811B2 (en) | Dynamic random access memory and method of manufacturing the same | |
| CN115513133A (en) | Semiconductor structure and manufacturing method thereof | |
| CN117939873A (en) | Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory | |
| WO2022236980A1 (en) | Method for manufacturing memory | |
| US6329255B1 (en) | Method of making self-aligned bit-lines | |
| US8361849B2 (en) | Method of fabricating semiconductor device | |
| US11462548B1 (en) | Semicondcutor device and manufacturing method thereof | |
| CN114446884B (en) | Semiconductor structure and forming method thereof | |
| US11791163B1 (en) | Manufacturing method of semiconductor structure and semiconductor structure | |
| CN113658955B (en) | Semiconductor structure and forming method thereof | |
| CN119069420B (en) | A semiconductor structure and a method for forming the same | |
| US12094720B2 (en) | Semiconductor structure and manufacturing method thereof | |
| US20240008267A1 (en) | Semiconductor structure and method for fabricating same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |