CN118259056A - Probe card with adjustable probe height, wafer testing device and method - Google Patents

Abstract

The application discloses a probe card with an adjustable probe height, a wafer testing device and a method, wherein the probe card comprises the following components: a probe; a printed circuit board; a probe controller; the probe card is used for testing the wafer placed on the probe station; the probe controller is connected with the probe and the printed circuit board and is used for receiving the needle outlet position information issued by the upper terminal; the probe controller is also used for adjusting the needle outlet gear of the probe according to the needle outlet position information and controlling a plurality of first probes at the needle outlet position to be kept at the height of the test gear; and controlling the second probes not to retract to the neutral position at the needle outlet position. According to the application, the micro controller is added between the test probe and the printed circuit board, so that the height of the probe is adjusted by taking the test site as a unit, and the user can set the needle insertion site in a self-defined manner.

Description

Probe card with adjustable probe height, wafer testing device and method

Technical Field

The application relates to the field of wafer testing, in particular to a probe card with an adjustable probe height, a wafer testing device and a wafer testing method.

Background

When the CP wafer is automatically tested, in order to improve the testing efficiency, a multi-site simultaneous testing mode is generally adopted, that is, a testing program of a tester runs a testing process once, and the probe card is simultaneously connected with a plurality of chips and simultaneously tests the plurality of chips.

However, after the conventional probe card is manufactured, since the probes are fixed on a Printed Circuit Board (PCB), the vertical distance between all probe tips and the PCB is fixed, so that the failed chip is detected by the probes during the test, and the chip passing the test must be pricked with new traces.

With the increase of technology, the requirements on the reliability of chips are higher and higher, and many wafers may need 3-4 or more CP flow tests before packaging, and if each flow is retested once, the total number of traces is doubled.

If the needle marks are too many, the subsequent packaging process is directly affected if the area is too large, and if the needle marks are too many, the chip can not be packaged subsequently and is scrapped if the needle marks are serious.

Disclosure of Invention

In order to solve the technical problems, the application provides a probe card with an adjustable probe height, a wafer testing device and a method, wherein a micro controller is added between a testing probe and a printed circuit board to realize the adjustment of the height of the probe by taking a testing place as a unit and the self definition of the place where a user wants to puncture.

Specifically, the technical scheme of the application is as follows:

In a first aspect, the present application discloses a probe card with an adjustable probe height, which is characterized by comprising:

a probe; a printed circuit board; a probe controller;

the probe card is used for testing the wafer placed on the probe station;

the probe controller is connected with the probe and the printed circuit board and is used for receiving the needle outlet position information issued by the upper terminal;

The probe controller is also used for adjusting the needle outlet gear of the probe according to the needle outlet position information and controlling a plurality of first probes at the needle outlet position to be kept at the height of the test gear; and controlling the second probes not to retract to the neutral position at the needle outlet position.

In some embodiments, the probe controller is further configured to push all of the probes out of neutral height to test level before the probe card is tested; the neutral height is lower than the test height.

In some embodiments, the probe controller is further configured to detect a gear height of the probe; if the gear height is abnormal, an abnormal alarm is sent to the upper terminal.

In some embodiments, the pin-out position information is determined by a test result of a current test of the wafer, and is issued to the probe controller by the probe card controller;

or the needle outlet position information is generated by the user-defined setting of the testing machine and is issued to the probe controller by the testing machine.

In a second aspect, the present application discloses a wafer testing apparatus, comprising:

The probe station is used for placing a wafer; the wafer is further used for conveying the wafer to a designated test position through a mechanical arm;

a testing machine on which the probe card of any of the above embodiments is mounted; the tester is used for testing the wafer for one or more times through the probe card;

The tester is connected with the probe station through a bus interface.

In some embodiments, the probe station is further configured to obtain a test result of the wafer after the current test is finished, where the test result includes location information of a qualified chip and a non-qualified chip on the wafer;

The probe card controller is arranged in the bus interface; the probe card is used for determining the needle outlet position information of the probe card in the next test according to the test result; so that the probe card adjusts the needle outlet gear of the probe according to the needle outlet position information;

the testing machine is also used for retesting the unqualified chips on the wafer through the probe card with the gear adjusted.

In some embodiments, the testing machine is further configured to receive a user-defined instruction issued by a user, and set a needle-out position of the probe card when testing next time, so that the probe card adjusts a needle-out gear of the probe according to the needle-out position information.

In a third aspect, the present application also discloses a wafer testing method, where the method is applied to the wafer testing apparatus described in any one of the foregoing embodiments, and the method includes:

Controlling the probe card arranged on the tester to test the wafer placed on the probe station;

After the current test is finished, a test result of the current test is obtained through the probe station, wherein the test result comprises position information of qualified chips and unqualified chips on the wafer;

According to the test result, performing needle outlet gear adjustment on the probe card;

and controlling the probe card with the gear adjusted, and retesting the unqualified chips on the wafer.

In some embodiments, the adjusting the pin-out gear of the probe card according to the test result specifically includes:

Determining the needle outlet position information of the probe card in the next test according to the test result, and setting the position of the unqualified chip in the test result as the needle outlet position of the probe card in the next test;

According to the needle outlet position information, adjusting the needle outlet gear of the probes, and controlling a plurality of first probes at the needle outlet position to be kept at the test gear height; and controlling the second probes not to retract to the neutral position at the needle outlet position.

In some embodiments, the wafer testing method further comprises: repeating the steps of the wafer testing method in the method embodiment until the preset test times are completed, or all chips on the wafer are tested to be qualified.

Compared with the prior art, the application has at least one of the following beneficial effects:

1. According to the application, the probe controller is added between the probe and the printed circuit board, and can adjust the distance between the probe tip and the printed circuit board by taking the place as a unit, so that the distance between the probe tip and the wafer is adjusted, and the place without testing can be retracted to a position without contact with the wafer to be tested during the reconfiguration, so that the position of the qualified chip detected by the probe again is reduced. The application solves the problem that the needle mark of the qualified chip is increased by retesting the failed chip under the condition of simultaneous testing at multiple sites during the CP test.

Drawings

The above features, technical features, advantages and implementation of the present application will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.

FIG. 1 is a schematic diagram of a probe card and a test apparatus according to the present application;

FIG. 2 is a schematic view of a probe gear when the probe card is not in operation in an embodiment of the application;

FIG. 3 is a schematic view of a probe gear of a probe card for one test in accordance with an embodiment of the present application;

FIG. 4 is a schematic view of a probe gear when the probe card is retested in an embodiment of the application;

FIG. 5 is a flow chart of the steps of one system embodiment of the method provided by the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

For simplicity of the drawing, only the parts relevant to the invention are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

In particular implementations, the terminal devices described in embodiments of the present application include, but are not limited to, other portable devices such as mobile phones, laptop computers, home teaching machines, or tablet computers having touch-sensitive surfaces (e.g., touch screen displays and/or touchpads). It should also be appreciated that in some embodiments, the terminal device is not a portable communication device, but rather a desktop computer having a touch-sensitive surface (e.g., a touch screen display and/or a touch pad).

In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will explain the specific embodiments of the present application with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the application, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.

The application belongs to the field of CP test, and relates to the field of CP test, namely English full-scale Circuit Probing and Chip Probing, which are also called wafer test, wherein the test object is for each Die (Die) in a whole wafer (wafer), so as to ensure that each Die in the whole wafer can basically meet the characteristics or design specifications of a device. The wafer tester works on the principle that by connecting the wafer to the tester, various electrical tests are performed using probes and instruments inside the tester, typically including verification of voltage, current, timing and function. The test process mainly uses three devices of an automatic test system (Automatic Test Equipment, ATE, also called a tester), a sorter and a probe station. During testing, the tested object is placed on the probe station, then the probe on the probe card is directly contacted with the welding pad or the convex block on the chip, the chip signal generated by the lead-out testing machine (ATE) is applied on the tested device, and the feedback signal in the tested device is transmitted back to the testing machine, thus completing the whole testing. After the bad wafers are detected and screened, packaging engineering is carried out, and the testing steps greatly influence the manufacturing cost of the chip. The probe card is a test interface composed of a probe (probe pin), an electronic component (component), a wire (wire) and a Printed Circuit Board (PCB), and according to different situations, there is a requirement for a reinforcing plate (STIFFENER) and the like.

When the CP wafer is automatically tested, in order to improve the testing efficiency, a multi-site simultaneous testing mode is generally adopted, that is, a testing program of a tester runs a testing process once, and the probe card is simultaneously connected with a plurality of chips and simultaneously tests the plurality of chips. With the growth of technology, the requirements on the reliability of chips are increasing, and many wafers may need 3-4 or more CP flow tests before packaging. In the prior art, probes are fixed on a Printed Circuit Board (PCB), so that the vertical distance between all probe tips and the PCB is fixed, and thus, when a failed chip is detected by the probes during the test, the chip that has passed the test must be pricked with a new trace of needles again. Once again for each flow, the number of traces on the Device Under Test (DUT) is doubled. If the needle marks are too many, the subsequent packaging process is directly affected if the area is too large, and if the needle marks are too many, the chip can not be packaged subsequently and is scrapped if the needle marks are serious.

In order to solve the technical problem of excessive needle marks caused by needle insertion of all tested devices during retesting during automatic testing of a CP wafer, the application provides a probe card with an adjustable probe height, which comprises the following components with reference to an attached figure 1 in the specification: probes (Needle); a Printed Circuit Board (PCB); and a probe controller.

The probe card is used for testing a wafer placed on a probe station.

The probe controller is connected with the probe and the printed circuit board and is used for receiving the needle outlet position information issued by the upper terminal.

And the probe controller is also used for adjusting the needle outlet gear of the probe according to the needle outlet position information and controlling a plurality of first probes at the needle outlet position to be kept at the test gear height. And controlling the second probes not to retract to the neutral position at the needle outlet position. Specifically, the probe controller is a micro controller.

In other implementations of this embodiment, the probe card with adjustable probe height further includes: electronic components, wires, etc.

In other implementations of this embodiment, the probe controller is further configured to push all of the probes out of a neutral height to a test level (testpos) before the probe card is tested. The neutral height (idle pos) is lower than the test gear height (testpos). Specifically, referring to fig. 2 and 3 of the specification, fig. 2 is a relative position of a probe and a printed circuit board when the probe card is not tested. FIG. 3 shows the relative positions of probes and a printed circuit board when the probe card is first tested. More preferably, when testing is performed currently, all chips need to be tested, all places are at test positions (testpos), and after each test is completed, the probe station records the positions of the falling pass and fail of the test. And after the whole wafer is recorded, retest scanning is carried out. Every time the probe station moves to a new descending position, the probe station can withdraw the probe corresponding to the position of the chip which is originally qualified to a neutral position (idle pos) according to the information of the qualified chip and the unqualified chip in the descending recorded by the probe station, only a place needing to be tested is left, and the probe is kept at a test position (test pos). Referring to fig. 4 of the specification, the chip which is already tested and qualified can be prevented from being repeatedly needled, and the number of times of needling marks is reduced.

In other implementations of this embodiment, the probe controller is further configured to detect a gear height of the probe. If the gear height is abnormal, an abnormal alarm is sent to the upper terminal. Specifically, the probe controller pushes the position of the small silicon chip from the neutral position to the test position when the probe station performs the probe alignment operation. After the needle is finished, the probe controller can appropriately adjust the probe height gripped by the probe station by taking the place as a unit, and record the position as a reference position of each place. If the difference between the heights of some probes and the heights of other probes at the local site is abnormal in the process of needle alignment, the machine station alarms and checks the probe level at the site.

In other implementations of this embodiment, the pin-out position information is determined by a test result of the wafer current test and issued by a probe card controller to the probe controller. Specifically, referring to fig. 1, it can be seen that the tester and the probe station communicate with each other through a GPIB bus, and the probe card controller is connected to the GPIB bus communication interface between the tester and the probe station. Before the probe station issues a start test instruction (i.e., an instruction to prick a probe onto a wafer), the probe card controller is configured to receive position information of a chip to be tested recorded by the probe station, and determine location information extending to a test site according to the received information.

In other implementations of this embodiment, the positional information of the chip under test is directly recorded by the probe controller. Specifically, the probe controller is further configured to directly generate the needle-out position information according to the position information of the chip to be tested, adjust a needle-out gear of the probe according to the needle-out position information, and control a plurality of first probes at the needle-out position to be kept at a test gear height; and controlling the second probes not to retract to the neutral position at the needle outlet position.

In other implementations of this embodiment, the needle-out position information is generated by a tester custom setting that is issued by the tester to the probe controller. Specifically, when relevant technicians perform engineering debugging, the test program can be used for customizing the required test place, the tester can transmit the information of the place to be tested to the probe card through the GPIB interface, and unnecessary needle insertion in the debugging process can be reduced.

By the embodiment, the problem that the needle mark of the qualified chip is increased in the repeated test of the failed chip under the condition of simultaneous test of multiple sites of the CP is solved.

Based on the same technical conception, the application also discloses a wafer testing device, which specifically comprises:

the probe station is used for placing a wafer; and the wafer is conveyed to a designated test position through a mechanical arm.

And the testing machine is provided with the probe card in any probe card embodiment. The tester is used for testing the wafer for one or more times through the probe card.

The tester is connected with the probe station through a bus interface.

Another embodiment of the wafer testing apparatus provided by the present application further includes, based on the above embodiment of the wafer testing apparatus: and a probe card controller.

And the probe station is also used for acquiring a test result of the wafer after the current test is finished, wherein the test result comprises position information of the qualified chips and the unqualified chips on the wafer.

And the probe card controller is arranged in the bus interface. And the probe card is used for determining the needle outlet position information of the probe card in the next test according to the test result. So that the probe card adjusts the needle outlet gear of the probe according to the needle outlet position information. Specifically, the probe card controller is specifically configured to: and setting the position of the unqualified chip as the needle outlet position of the probe card in the next test in the ending of the test.

The testing machine is also used for retesting the unqualified chips on the wafer through the probe card with the gear adjusted.

In other embodiments of the present embodiment, the testing machine is further configured to receive a user-defined instruction issued by a user, and set a needle-out position of the probe card when testing next time, so that the probe card adjusts a needle-out stop of the probe according to the needle-out position information.

Specifically, referring to fig. 1 of the specification, in this embodiment, by adding a probe controller between a test probe and a PCB, and accessing a probe card controller into a GPIB bus communication interface between a tester and a probe station, the height of the probe is adjusted by taking a test site as a unit, and a user can define a site where a user wants to puncture.

Based on the same technical concept, the application also discloses a wafer testing method, which is characterized in that the method is applied to the wafer testing device described in any one of the embodiments, and referring to fig. 5 in the specification, the method includes:

S100, controlling the probe card arranged on the testing machine to test the wafer placed on the probe station.

And S200, after the current test is finished, acquiring a test result of the current test through the probe station, wherein the test result comprises position information of the qualified chips and the unqualified chips on the wafer.

S300, according to the test result, the needle outlet gear of the probe card is adjusted.

S400, controlling the probe card with the gear adjusted, and retesting the unqualified chips on the wafer.

Wherein, the step S300: according to the test result, the probe card is subjected to needle outlet gear adjustment, and the method specifically comprises the following steps:

s310, determining the needle outlet position information of the probe card in the next test according to the test result, and setting the position of the unqualified chip in the test result as the needle outlet position of the probe card in the next test.

S320, adjusting the needle outlet gear of the probes according to the needle outlet position information, and controlling a plurality of first probes at the needle outlet position to be kept at the test gear height; and controlling the second probes not to retract to the neutral position at the needle outlet position.

In another embodiment of the wafer testing method provided by the present application, based on the system embodiment, the wafer testing method further includes repeating the steps of the wafer testing method in the method embodiment until the preset test times are completed, or all the chips on the wafer are tested to be qualified.

The probe card with the adjustable probe height, the wafer testing device and the method have the same technical conception, and the technical details of the three embodiments can be mutually applicable, so that repetition is reduced, and the description is omitted.

It will be apparent to those skilled in the art that the above-described program modules are only illustrated in the division of the above-described program modules for convenience and brevity, and that in practical applications, the above-described functional allocation may be performed by different program modules, i.e., the internal structure of the apparatus is divided into different program units or modules, to perform all or part of the above-described functions. The program modules in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one processing unit, where the integrated units may be implemented in a form of hardware or in a form of a software program unit. In addition, the specific names of the program modules are also only for distinguishing from each other, and are not used to limit the protection scope of the present application.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described embodiments of the apparatus are exemplary only, and exemplary, the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, exemplary, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. A probe card with an adjustable probe height, comprising:

a probe; a printed circuit board; a probe controller;

the probe card is used for testing the wafer placed on the probe station;

the probe controller is connected with the probe and the printed circuit board and is used for receiving the needle outlet position information issued by the upper terminal;

The probe controller is also used for adjusting the needle outlet gear of the probe according to the needle outlet position information and controlling a plurality of first probes at the needle outlet position to be kept at the height of the test gear; and controlling the second probes not to retract to the neutral position at the needle outlet position.

2. A probe card with an adjustable probe height as claimed in claim 1, wherein:

Before the probe card is tested, the probe controller is also used for pushing all the probes out from the neutral gear height to the test gear height; the neutral height is lower than the test height.

3. A probe card with an adjustable probe height as claimed in claim 2, wherein:

The probe controller is also used for detecting the gear height of the probe; if the gear height is abnormal, an abnormal alarm is sent to the upper terminal.

4. A probe card with an adjustable probe height as set forth in claim 1, comprising:

the needle outlet position information is determined by the test result of the current test of the wafer and is issued to the probe controller by the probe card controller;

or the needle outlet position information is generated by the user-defined setting of the testing machine and is issued to the probe controller by the testing machine.

5. A wafer testing apparatus, comprising:

The probe station is used for placing a wafer; the wafer is further used for conveying the wafer to a designated test position through a mechanical arm;

A testing machine on which the probe card of any one of claims 1-4 is mounted; the tester is used for testing the wafer for one or more times through the probe card;

The tester is connected with the probe station through a bus interface.

6. The wafer test apparatus of claim 5, wherein: further comprises: a probe card controller;

the probe station is further used for acquiring a test result of the wafer after the current test is finished, wherein the test result comprises position information of qualified chips and unqualified chips on the wafer;

The probe card controller is arranged in the bus interface; the probe card is used for determining the needle outlet position information of the probe card in the next test according to the test result; so that the probe card adjusts the needle outlet gear of the probe according to the needle outlet position information;

the testing machine is also used for retesting the unqualified chips on the wafer through the probe card with the gear adjusted.

7. The wafer test apparatus of claim 5, wherein:

The testing machine is also used for receiving a user-defined instruction issued by a user, and setting the needle outlet position of the probe card in the next test, so that the probe card can adjust the needle outlet gear of the probe according to the needle outlet position information.

8. A wafer testing method, wherein the method is applied to the wafer testing apparatus according to any one of claims 5 to 7, and comprises:

Controlling the probe card arranged on the tester to test the wafer placed on the probe station;

After the current test is finished, a test result of the current test is obtained through the probe station, wherein the test result comprises position information of qualified chips and unqualified chips on the wafer;

According to the test result, performing needle outlet gear adjustment on the probe card;

and controlling the probe card with the gear adjusted, and retesting the unqualified chips on the wafer.

9. The method for testing a wafer according to claim 8, wherein the step of adjusting the probe card according to the test result comprises:

Determining the needle outlet position information of the probe card in the next test according to the test result, and setting the position of the unqualified chip in the test result as the needle outlet position of the probe card in the next test;

According to the needle outlet position information, adjusting the needle outlet gear of the probes, and controlling a plurality of first probes at the needle outlet position to be kept at the test gear height; and controlling the second probes not to retract to the neutral position at the needle outlet position.

10. The wafer testing method of claim 8 or 9, further comprising:

Repeating the steps of the wafer testing method until the preset testing times are completed, or all chips on the wafer are tested to be qualified.