CN118412333A - Semiconductor structure and mask layout - Google Patents
Semiconductor structure and mask layout Download PDFInfo
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- CN118412333A CN118412333A CN202310087665.XA CN202310087665A CN118412333A CN 118412333 A CN118412333 A CN 118412333A CN 202310087665 A CN202310087665 A CN 202310087665A CN 118412333 A CN118412333 A CN 118412333A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 229910052751 metal Inorganic materials 0.000 claims abstract description 391
- 239000002184 metal Substances 0.000 claims abstract description 391
- 230000001154 acute effect Effects 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 9
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 182
- 238000000034 method Methods 0.000 description 25
- 230000002349 favourable effect Effects 0.000 description 17
- 239000000758 substrate Substances 0.000 description 15
- 239000003989 dielectric material Substances 0.000 description 8
- 238000003475 lamination Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003245 working effect Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A semiconductor structure and mask layout, the semiconductor structure includes: the metal layers are stacked from bottom to top, each metal layer comprises a plurality of metal wires which extend along a preset direction and are arranged in parallel along a direction perpendicular to the preset direction, and the preset direction of each metal wire in two adjacent metal layers has a preset angle which is an acute angle; and the through hole interconnection structures are positioned between the adjacent two metal layers, are positioned at the projection overlapping positions of the adjacent two metal lines on the horizontal plane, and are electrically connected with the corresponding adjacent two metal lines. The invention is beneficial to reducing the contact resistance between the through hole interconnection structure and the corresponding electrically connected metal wire, thereby being beneficial to improving the working performance of the semiconductor structure.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a mask layout.
Background
With the development of semiconductor process technology, the semiconductor device is becoming more integrated, the size of the semiconductor device is becoming smaller and smaller, and the critical dimension (CD, critical Dimension) of the semiconductor device is also becoming smaller and smaller, and the size of the metal Line interconnect is also further reduced in BEOL (Back End of Line).
The metal plugs (via) between metal lines have a large impact on the back end of line reliability (BEOL reliability), which can be affected if the metal plugs are not formed to the desired effect. With further shrinking of critical dimensions in the back-end process, the width dimensions and the gaps of the metal lines are further reduced, and in the current back-end process, a SAV (self-aligned via) process is generally used to form metal plugs, and the dimensions of the metal plugs are also reduced due to the reduced dimensions of the width dimensions and the gaps of the metal lines, so that adverse effects are generated on the reliability of the back-end.
Disclosure of Invention
The invention solves the problem of providing a semiconductor structure and a mask layout, and improves the working performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the metal layers are stacked from bottom to top, each metal layer comprises a plurality of metal wires which extend along a preset direction and are arranged in parallel along a direction perpendicular to the preset direction, and the preset direction of each metal wire in two adjacent metal layers has a preset angle which is an acute angle; and the through hole interconnection structures are positioned between the adjacent two metal layers, are positioned at the projection overlapping positions of the adjacent two metal lines on the horizontal plane, and are electrically connected with the corresponding adjacent two metal lines.
Optionally, among the plurality of metal layers stacked from bottom to top, the preset direction of the metal wire has a preset angle in any two adjacent metal layers.
Optionally, the preset angles of any two adjacent metal layers are equal, or the preset angles of any two adjacent metal layers are partially equal, or the preset angles of any two adjacent metal layers are unequal.
Optionally, the plurality of metal layers stacked from bottom to top comprises a plurality of metal stacks stacked in a cycle, the metal stacks comprising a plurality of adjacent metal layers, the number of metal layers in each metal stack being equal.
Optionally, in the metal stack, the plurality of metal wires from bottom to top sequentially rotate a preset angle along a specified direction, and the angle from the topmost metal wire to the bottommost metal wire along the specified direction is smaller than or equal to the preset angle, wherein the specified direction is a counterclockwise direction or a clockwise direction.
Alternatively, the number of metal layers in the metal stack is 3 or 4.
Optionally, the preset angle is 45 ° to 60 °.
Optionally, the material of the metal line comprises one or more of copper, aluminum and copper alloy.
Correspondingly, the embodiment of the invention also provides a mask layout, which comprises the following steps: the first layout layers comprise a plurality of metal wire patterns which extend along a preset direction and are arranged in parallel along a direction perpendicular to the preset direction, and in the two adjacent first layout layers, the preset direction of the metal wire patterns has a preset angle which is an acute angle; the second layout layer is positioned between the two adjacent layers of the first layout layers, and comprises through hole interconnection structure patterns positioned at the projection overlapping position of the two adjacent layers of metal line patterns on the horizontal plane.
Optionally, in the plurality of first layout layers from bottom to top, the preset direction of the metal line graph in any two adjacent first layout layers has a preset angle.
Optionally, the preset angles of any two adjacent first layout layers are equal, or the preset angles of any two adjacent first layout layers are partially equal, or the preset angles of any two adjacent first layout layers are unequal.
Optionally, the plurality of first layout layers from bottom to top include a plurality of layout stacks circularly arranged, the layout stacks include a plurality of adjacent first layout layers, and the number of the first layout layers in each layout stack is equal.
Optionally, in the layout lamination, the plurality of metal line patterns from bottom to top sequentially rotate by a preset angle along a designated direction, and the angle from the top metal line pattern to the bottom metal line pattern along the designated direction is smaller than or equal to the preset angle, wherein the designated direction is a counterclockwise direction or a clockwise direction.
Optionally, in the layout stack, the number of the first layout layers is 3 or 4.
Optionally, the preset angle is 45 ° to 60 °.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the semiconductor structure provided by the embodiment of the invention, the metal layer comprises a plurality of metal wires which extend along the preset direction and are arranged in parallel along the direction perpendicular to the preset direction, and the preset direction of the metal wires in two adjacent metal layers has a preset angle which is an acute angle; in two adjacent metal layers, the contained angle between the extending direction of metal wire is the acute angle, compares in two adjacent metal layers, and the contained angle between the extending direction of metal wire is the scheme of right angle, and this scheme is favorable to increasing the projection overlap area of two adjacent metal wires at the horizontal plane, and the through-hole interconnect structure is located the projection overlap department of two adjacent metal wires at the horizontal plane, then is favorable to increasing the process window of through-hole interconnect structure between two adjacent metal wires to be favorable to increasing the area of contact between through-hole interconnect structure and the metal wire that corresponds the electricity to be connected, be favorable to reducing the contact resistance between through-hole interconnect structure and the metal wire that corresponds the electricity to be connected, and then be favorable to improving semiconductor structure's working property.
In the mask layout provided by the embodiment of the invention, the first layout layer comprises a plurality of metal wire patterns which extend along the preset direction and are arranged in parallel along the direction perpendicular to the preset direction, and in the adjacent two layers of first layout layers, the preset direction of the metal wire patterns has a preset angle which is an acute angle; the first layout layer is used for forming metal layers, the metal line patterns are used for forming metal lines, in two adjacent layers of the first layout layer, the included angle between the extending directions of the metal line patterns is an acute angle, that is, in two adjacent layers of the metal layers, the included angle between the extending directions of the metal lines is an acute angle.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to a semiconductor structure;
fig. 4 to 7 are schematic structural views corresponding to an embodiment of the semiconductor structure of the present invention;
FIG. 8 is a schematic diagram of an embodiment of a reticle layout of the present invention.
Detailed Description
At present, with the ever shrinking technology nodes, how to improve the performance of semiconductor structures becomes a challenge. The reasons why the working performance of a semiconductor structure is to be improved are now analyzed in combination with a semiconductor structure.
Fig. 1 to 3 are schematic structural views corresponding to a semiconductor structure.
Referring to fig. 1 to 3 in combination, fig. 2 is a cross-sectional view of fig. 1 along AA direction, fig. 3 is a cross-sectional view of fig. 1 along BB direction, the semiconductor structure includes: the metal layers are stacked from bottom to top, each metal layer comprises a plurality of metal wires 10 which extend along a preset direction and are arranged in parallel along a direction perpendicular to the preset direction, and the preset directions of the metal wires 10 in two adjacent metal layers are perpendicular to each other; and a plurality of via interconnection structures 30 positioned between the adjacent two metal layers, wherein the via interconnection structures 30 are positioned at the projection overlapping positions of the adjacent two metal lines on the horizontal plane and are electrically connected with the corresponding adjacent two metal lines.
In the adjacent two metal layers, the preset direction of the metal line 10 is perpendicular, the projection area of the adjacent two metal lines on the horizontal plane is smaller, so that the cross-sectional area of the through hole interconnection structure 30 formed at the position where the projections of the adjacent two metal lines on the horizontal plane overlap is smaller, especially, in the trend that the size of the semiconductor device is gradually and proportionally shrinking, the width dimension of the rear metal line 10 is gradually reduced, the cross-sectional area of the through hole interconnection structure 30 is further reduced, the contact area between the through hole interconnection structure 30 and the lower metal line 10 is easily reduced, and thus the contact resistance is increased, in the rear process, the SAV (self-align) process is generally adopted to form the through hole interconnection structure 30, so that the width dimension of the through hole interconnection structure 30 is limited by the width of the upper metal line 10 in the SAV direction (shown in the combination of the dotted coil and the fig. 2 in the reference fig. 1), and the width dimension of the through hole interconnection structure 30 is limited by the width dimension of the lower metal line 10, meanwhile, in the formation of the through hole interconnection structure 30 is easily caused, the contact area between the through hole interconnection structure 30 and the lower metal line 10 is further reduced, and the corresponding contact resistance of the lower metal line is further reduced, and the corresponding contact resistance of the lower metal structure is further influenced by the corresponding opening dimension of the lower metal structure is formed, and the contact resistance of the lower opening structure is further reduced.
In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: the metal layers are stacked from bottom to top, each metal layer comprises a plurality of metal wires which extend along a preset direction and are arranged in parallel along a direction perpendicular to the preset direction, and the preset direction of each metal wire in two adjacent metal layers has a preset angle which is an acute angle; and the through hole interconnection structures are positioned between the adjacent two metal layers, are positioned at the projection overlapping positions of the adjacent two metal lines on the horizontal plane, and are electrically connected with the corresponding adjacent two metal lines.
In the semiconductor structure provided by the embodiment of the invention, the metal layer comprises a plurality of metal wires which extend along the preset direction and are arranged in parallel along the direction perpendicular to the preset direction, and the preset direction of the metal wires in two adjacent metal layers has a preset angle which is an acute angle; in two adjacent metal layers, the contained angle between the extending direction of metal wire is the acute angle, compares in two adjacent metal layers, and the contained angle between the extending direction of metal wire is the scheme of right angle, and this scheme is favorable to increasing the projection overlap area of two adjacent metal wires at the horizontal plane, and the through-hole interconnect structure is located the projection overlap department of two adjacent metal wires at the horizontal plane, then is favorable to increasing the process window of through-hole interconnect structure between two adjacent metal wires to be favorable to increasing the area of contact between through-hole interconnect structure and the metal wire that corresponds the electricity to be connected, be favorable to reducing the contact resistance between through-hole interconnect structure and the metal wire that corresponds the electricity to be connected, and then be favorable to improving semiconductor structure's working property.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 7 are schematic structural views of an embodiment of the semiconductor structure of the present invention, wherein fig. 5 is a cross-sectional view along AA in fig. 4, and fig. 6 is a cross-sectional view along BB in fig. 4.
The semiconductor structure includes: a plurality of metal layers stacked from bottom to top, wherein the metal layers include a plurality of metal lines 100 extending along a predetermined direction (as shown in an X direction in fig. 4) and arranged in parallel along a direction perpendicular to the predetermined direction, and the predetermined direction of the metal lines 100 has a predetermined angle α, which is an acute angle, in two adjacent metal layers; the via interconnect structures 400 are located between two adjacent metal layers, and the via interconnect structures 400 are located at the overlapping positions of projections of the two adjacent metal lines 100 on the horizontal plane and are electrically connected with the corresponding two adjacent metal lines 100.
In this embodiment, the semiconductor structure is used to form back end of line (BEOL) interconnect structures.
In this embodiment, the semiconductor structure includes a base (not shown), the base includes a base structure layer (not shown), and the base structure layer includes a substrate (not shown). Taking the semiconductor structure as a planar semiconductor structure as an example, the substrate is a planar substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. In other embodiments, when the semiconductor structure is a three-dimensional semiconductor structure, the substrate may also be a substrate having fins.
The base structure layer may also include other structures such as gate structures, doped regions, shallow trench isolation structures (shallow trench isolation, STI), dielectric layers, and the like, with devices (e.g., MOS transistors or SRAM devices, etc.) formed in the base structure layer. Specifically, the base structure layer further includes an interlayer dielectric layer (not shown) formed on the substrate and a Contact (CT) formed in the interlayer dielectric layer.
Correspondingly, in the embodiment, a plurality of metal layers stacked from bottom to top are located on the substrate.
The plurality of metal layers are used to form a back-end metal interconnect structure, wherein metal lines 100 are used as metal interconnect lines in the back-end interconnect structure.
In this embodiment, in two adjacent metal layers, the included angle between the extending directions of the metal wires 100 is an acute angle, compared with the scheme that in two adjacent metal layers, the included angle between the extending directions of the metal wires is a right angle, the scheme is favorable for increasing the projection overlapping area of two adjacent metal wires 100 on the horizontal plane, and the via interconnection structure 400 is located at the projection overlapping position of two adjacent metal wires 100 on the horizontal plane, so that the process window of the via interconnection structure 400 between two adjacent metal wires 100 is favorable for increasing the contact area between the via interconnection structure 400 and the metal wire 100 which is electrically connected correspondingly, and is favorable for reducing the contact resistance between the via interconnection structure 400 and the metal wire 100 which is electrically connected correspondingly, so as to further facilitate improving the working performance of the semiconductor structure.
Specifically, in the subsequent process, the via interconnection structure 400 is formed by using a SAV (self-align via) process, in which the width dimension of the via interconnection structure 400 is limited by the width of the upper metal line 100 (as shown in fig. 4 and by referring to the dash-dot line and fig. 6), but the projected overlapping area of the two adjacent metal lines 100 in the horizontal plane is increased, the width dimension of the via interconnection structure 400 in the SAV direction is correspondingly increased, correspondingly, the contact dimension d2 of the via interconnection structure 400 and the lower metal line 100 in the SAV direction is also increased, the width dimension of the via interconnection structure 400 in the non-SAV direction (as shown in fig. 4 and by referring to the dash-dot line and fig. 5) is limited by the width of the lower metal line 100, but the projected overlapping area of the two adjacent metal lines 100 in the horizontal plane is increased, correspondingly, the width dimension of the via interconnection structure 400 and the lower metal line 100 in the non-SAV direction is also increased, correspondingly, the contact dimension d2 of the via interconnection structure 400 and the lower metal line 100 in the non-SAV direction is also increased, thereby being beneficial to the increase of the contact resistance between the via interconnection structure and the lower metal line 100, and the contact resistance between the interconnection structure and the semiconductor structure is further increased.
In this embodiment, among the plurality of metal layers stacked from bottom to top, the preset direction of the metal line 100 has a preset angle α in any two adjacent metal layers.
Among the plurality of metal layers stacked from bottom to top, the preset direction of the metal wire 100 has a preset angle α in any two adjacent metal layers, so that the process window is increased for the formation of the via interconnection structure 400 between any two adjacent metal layers, and the contact area is increased for the via interconnection structure 400 between any two metal layers 100 and the metal wire 100 correspondingly electrically connected, so that the contact resistance between the via interconnection structure 400 between any two metal layers 100 and the metal wire 100 correspondingly electrically connected is reduced, and the overall resistance of the back-end interconnection structure is reduced.
In this embodiment, the preset angles α of any two adjacent metal layers are equal.
The preset angles alpha of any two adjacent metal layers are equal, so that the structural arrangement regularity of the semiconductor structure is good, the formation difficulty of the semiconductor structure is reduced, and the semiconductor structure is easy to form.
In other embodiments, any two adjacent metal layers may have a predetermined angle portion equal to each other.
In other embodiments, any two adjacent metal layers may have different preset angles.
In this embodiment, the plurality of metal layers stacked from bottom to top includes a plurality of metal stacks stacked in a circle, the metal stacks include a plurality of adjacent metal layers, and the number of metal layers in each metal stack is equal.
The plurality of metal laminations are circularly stacked to form the semiconductor structure, so that the arrangement regularity of the semiconductor structure is high, each metal lamination is formed by adopting the same steps in the process of forming the semiconductor structure, and then the step of forming each metal lamination is circularly operated, so that a plurality of metal layers stacked from bottom to top can be obtained, the semiconductor structure is easy to form, and the process difficulty is reduced.
In the present embodiment, in the metal stack, the plurality of metal wires 100 sequentially rotate from bottom to top by a preset angle α along a specified direction, and the angle from the top metal wire 100 to the bottom metal wire 100 along the specified direction is smaller than or equal to the preset angle α, wherein the specified direction is a counterclockwise direction or a clockwise direction.
In the metal stacks, the plurality of metal wires 100 from bottom to top sequentially rotate by a preset angle α along a designated direction, and the angle from the top metal wire 100 to the bottom metal wire 100 along the designated direction is smaller than or equal to the preset angle α, that is, the plurality of metal wires 100 in the metal stacks rotate to cover 360 ° along the designated direction as much as possible, so that in each metal stack, the extending direction of the metal wires 100 can cover a plurality of directions in a circle of 360 ° as much as possible, thereby the extending direction of the metal wires 100 can meet the wiring requirement of the electrical connection of the semiconductor structure in each direction as much as possible, which is beneficial to improving the application range of the semiconductor structure and further improving the applicability of the semiconductor structure.
As an example, in the present embodiment, the specified direction is a counterclockwise direction.
In the present embodiment, the number of metal layers in the metal stack is not too large or too small. If the number of metal layers is too large, unnecessary waste is easily caused, and the too large number of metal layers also easily causes too small a preset angle alpha between the extending directions of the metal wires of adjacent layers, which easily makes difficult the formation of the metal wires 100; if the number of metal layers is too small, in the metal stack, the extending direction of the multi-layer metal line 100 is difficult to cover multiple directions in a circle of 360 °, so that it is easy to cause that the extending direction of the metal line 100 can be difficult to meet the wiring requirement of the semiconductor structure for electrical connection in all directions, and thus the application of the semiconductor structure is affected. For this reason, in the present embodiment, the number of metal layers in the metal stack is 3 or 4.
In this embodiment, the preset angle α is not too large or too small. If the preset angle α is too large, in the metal stack, the extending direction of the multi-layer metal line 100 is difficult to cover multiple directions in a circle of 360 ° so as to easily cause that the extending direction of the metal line 100 can hardly meet the wiring requirement of the semiconductor structure for electrical connection in all directions, thereby affecting the application of the semiconductor structure; if the preset angle α is too small, the angle between the extending directions of the metal lines of the adjacent layers is too small, which is easy to cause difficulty in forming the metal line 100, and the number of metal layers in the metal stack is too large, resulting in unnecessary waste. For this reason, in the present embodiment, the preset angle α is 45 ° to 60 °.
As an example, as shown in fig. 7, fig. 7 shows a schematic structural view of the metal wires 100 in one metal laminate, in this embodiment, the preset angle α is 60 °, in the metal laminate, the number of metal layers is 3, that is, in the metal laminate, the metal wires 100 of the second metal layer are obtained by rotating the metal wires 100 of the first metal layer counterclockwise by 60 °, and the metal wires 100 of the third metal layer are obtained by rotating the metal wires 100 of the second metal layer counterclockwise by 60 °, so that in each metal laminate, fewer metal layers are used, that is, the extending direction of the metal wires 100 can be uniformly related to a plurality of directions covering 360 ° one week, and therefore, the preset angle α is 60 °, in the metal laminate, the number of metal layers is 3, which is a scheme with good regularity and good effect in this embodiment.
In this embodiment, the material of the metal line 100 includes one or more of copper, aluminum, and copper alloy, so that the metal line 100 is used to achieve better conductivity.
The via interconnect structure 400 is used to electrically connect the metal lines 100 of adjacent two metal layers to each other.
In this embodiment, the via interconnection structure 400 is located at the projection overlapping position of the two adjacent layers of metal lines 100 in the horizontal plane, which increases the projection overlapping area of the two adjacent layers of metal lines 100 in the horizontal plane, thereby being beneficial to increasing the process window of the via interconnection structure 400 between the two adjacent layers of metal lines 100, being beneficial to increasing the contact area between the via interconnection structure 400 and the metal line 100 correspondingly electrically connected, further being beneficial to reducing the contact resistance between the via interconnection structure 400 and the metal line 100 correspondingly electrically connected, and improving the working performance of the semiconductor structure.
In this embodiment, the material of the via interconnection structure 400 is a metal material. The metal material has better conductivity, which is beneficial to improving the electrical connection performance between the metal wires 100.
In this embodiment, the material of the via interconnect structure 400 includes one or more of copper, aluminum, and copper alloys.
In this embodiment, the step of forming the via interconnect structure 400 includes: forming a trench for forming the metal line 100; forming a via hole for forming the via interconnection structure 400 through the trench; the via and the trench are filled to form the via interconnection structure 400 and the metal line 100, so that the via interconnection structure 400 and the upper metal line 100 electrically connected thereto are formed in the same step, which is advantageous in simplifying the process steps and improving the process efficiency.
For this purpose, in the present embodiment, the via interconnection structure 400 and the upper metal line 100 electrically connected thereto are integrally formed.
In this embodiment, the semiconductor structure further includes: a dielectric layer (not shown) on the substrate.
In this embodiment, the dielectric layer is an inter-metal dielectric (INTER METAL DIELECTRIC, IMD) layer, and is used to electrically isolate the metal interconnect structures in the back-end-of-line process.
For this purpose, the material of the dielectric layer is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6). In this embodiment, the material of the dielectric layer includes one or more of SiOC, siOCH, siC, siCN, siO 2, siN, and SiON. In this embodiment, the material of the dielectric layer is an ultra-low k dielectric material, so as to reduce parasitic capacitance between the back-end metal interconnection structures, and further reduce back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.
Accordingly, in the present embodiment, the metal lines 100 are located in the dielectric layer, and the adjacent metal lines 100 are separated by the dielectric layer.
FIG. 8 is a schematic diagram of a mask layout according to an embodiment of the present invention.
Referring to fig. 8, a reticle layout includes: the first layout layers from bottom to top comprise a plurality of metal line patterns 101 extending along a preset direction (shown as an X direction in fig. 8) and arranged in parallel along a direction perpendicular to the preset direction, wherein the preset direction of the metal line patterns 101 in two adjacent first layout layers has a preset angle alpha, and the preset angle alpha is an acute angle; and the second layout layer is positioned between the adjacent two layers of the first layout layers, and comprises a through hole interconnection structure graph 401 positioned at the projection overlapping position of the adjacent two layers of metal line graphs 101 on the horizontal plane.
In this embodiment, a semiconductor structure formed by a mask layout is used to form a back end of line (BEOL) interconnect structure.
In this embodiment, the first layout layer is used to form a metal layer, and the metal line pattern 101 is used to form a metal line.
Correspondingly, in this embodiment, in the adjacent two first layout layers, the preset direction of the metal line pattern 101 has a preset angle α, and the preset angle α is an acute angle, and in the adjacent two metal layers, the preset direction of the metal line has a preset angle α, and the preset angle α is an acute angle.
In this embodiment, the via interconnect pattern 401 is used to form a via interconnect structure.
Correspondingly, in this embodiment, the second layout layer is located between the adjacent two first layout layers, the via interconnection structure pattern 401 is located at the overlapping position of the projections of the adjacent two metal line patterns 101 on the horizontal plane, and then the via interconnection structure is formed between the adjacent two metal layers, and the via interconnection structure is located at the overlapping position of the projections of the adjacent two metal lines on the horizontal plane and is electrically connected with the corresponding adjacent two metal lines.
The plurality of metal layers are used for forming a back-end metal interconnection structure, wherein the metal lines are used as metal interconnection lines in the back-end interconnection structure.
In this embodiment, in two adjacent metal layers, the included angle between the extending directions of the metal line patterns 101 is an acute angle, that is, in two adjacent metal layers, the included angle between the extending directions of the metal lines is an acute angle, compared with the scheme that in two adjacent metal layers, the included angle between the extending directions of the metal lines is a right angle, the scheme is favorable for increasing the projection overlapping area of two adjacent metal lines on the horizontal plane, and the through hole interconnection structure is located at the projection overlapping position of two adjacent metal lines on the horizontal plane, so that the process window of the through hole interconnection structure between two adjacent metal lines is favorable for increasing the contact area between the through hole interconnection structure and the metal line which is electrically connected correspondingly, and is favorable for reducing the contact resistance between the through hole interconnection structure and the metal line which is electrically connected correspondingly, thereby being favorable for improving the working performance of the semiconductor structure corresponding to the mask layout.
Specifically, in the back-end process, a via interconnection structure is generally formed by using an SAV (self-aligned via) process, and in the SAV direction (as shown in fig. 4, a stippling coil is combined with fig. 6), the width dimension of the via interconnection structure is limited by the width of the upper metal line, but the projected overlapping area of two adjacent metal lines in the horizontal plane is increased, so that the width dimension of the via interconnection structure in the SAV direction is correspondingly increased, correspondingly, the contact dimension d2 between the via interconnection structure and the lower metal line in the SAV direction is also increased, and in the non-SAV direction (as shown in fig. 4, a dotted coil is combined with fig. 5), the width dimension of the via interconnection structure is limited by the width of the lower metal line, but the projected overlapping area of two adjacent metal lines in the horizontal plane is increased, so that the width dimension of the via interconnection structure in the non-SAV direction is correspondingly increased, correspondingly, the contact dimension d1 between the via interconnection structure and the lower metal line in the non-SAV direction is also increased, so that the contact resistance between the via interconnection structure and the lower metal line is correspondingly increased, and the contact resistance between the via interconnection structure and the semiconductor structure is advantageously increased.
In this embodiment, among the plurality of first layout layers from bottom to top, the preset directions of the metal line patterns 101 in any two adjacent first layout layers have preset angles α.
That is, in the embodiment, among the plurality of metal layers stacked from bottom to top, the preset direction of the metal line has the preset angle α in any two adjacent metal layers.
Among the plurality of metal layers stacked from bottom to top, the preset direction of the metal wire has a preset angle alpha in any two adjacent metal layers, so that the process window is increased in favor of forming a through hole interconnection structure between any two adjacent metal layers, the contact area is increased in favor of increasing the contact area of the through hole interconnection structure between any two metal layers and the metal wire correspondingly electrically connected, and the contact resistance between the through hole interconnection structure between any two metal layers and the metal wire correspondingly electrically connected is reduced, and the overall resistance of the rear-section interconnection structure is reduced.
In this embodiment, the preset angles α of any two adjacent first layout layers are equal.
That is, in this embodiment, the preset angles α of any two adjacent metal layers are equal.
The preset angles alpha of any two adjacent metal layers are equal, so that the structural arrangement regularity of the semiconductor structure is good, the formation difficulty of the semiconductor structure is reduced, and the semiconductor structure is easy to form.
In other embodiments, the preset angle portions of any two adjacent first layout layers may be equal.
In other embodiments, the preset angles of any two adjacent first layout layers may be different.
In this embodiment, the plurality of first layout layers from bottom to top includes a plurality of layout stacks circularly arranged, and the layout stacks include a plurality of adjacent first layout layers, where the number of first layout layers in each layout stack is equal.
That is, in the present embodiment, the plurality of metal layers stacked from bottom to top include a plurality of metal stacks stacked in a circle, the metal stacks include a plurality of adjacent metal layers, and the number of metal layers in each metal stack is equal.
The plurality of metal laminations are circularly stacked to form the semiconductor structure, so that the arrangement regularity of the semiconductor structure is high, each metal lamination is formed by adopting the same steps in the process of forming the semiconductor structure, and then the step of forming each metal lamination is circularly operated, so that a plurality of metal layers stacked from bottom to top can be obtained, the semiconductor structure is easy to form, and the process difficulty is reduced.
In this embodiment, in the layout stacking, the plurality of metal line patterns 101 sequentially rotate from bottom to top by a preset angle along a specified direction, and the angle from the top metal line pattern 101 to the bottom metal line pattern 101 along the specified direction is smaller than or equal to the preset angle α, where the specified direction is a counterclockwise direction or a clockwise direction.
That is, in the metal stack, the plurality of metal lines sequentially rotate from bottom to top by a predetermined angle α along a predetermined direction, and the angle from the top metal line to the bottom metal line along the predetermined direction is less than or equal to the predetermined angle α, wherein the predetermined direction is a counterclockwise direction or a clockwise direction.
In the metal laminated layers, the metal wires from bottom to top sequentially rotate along the designated direction by a preset angle alpha, and the angle from the top metal wire to the bottom metal wire along the designated direction is smaller than or equal to the preset angle alpha, that is, the metal wires in the metal laminated layers rotate to cover 360 degrees as much as possible along the designated direction, so that the extending direction of the metal wires in each metal laminated layer can cover a plurality of directions in a circle of 360 degrees as much as possible, the extending direction of the metal wires can meet the wiring requirement of the semiconductor structure for electric connection in all directions as much as possible, the application range of the semiconductor structure is improved, and the applicability of the semiconductor structure is improved.
As an example, in the present embodiment, the specified direction is a counterclockwise direction.
In this embodiment, the number of the first layout layers in the layout stack is not too large, and is not too small, that is, the number of the metal layers in the metal stack is not too large, and is not too small. If the number of metal layers is too large, unnecessary waste is easily caused, and the too large number of metal layers also easily causes too small a preset angle alpha between the extending directions of the metal lines of adjacent layers, which easily makes difficult the formation of the metal line patterns 101; if the number of metal layers is too small, in the metal stack, the extending direction of the multi-layer metal line pattern 101 is difficult to cover multiple directions in a circle of 360 °, so that it is easy to cause that the extending direction of the metal line pattern 101 can be difficult to meet the wiring requirement of the semiconductor structure for electrical connection in all directions, and further the application of the semiconductor structure is affected. For this reason, in the present embodiment, the number of metal layers in the metal stack is 3 or 4, that is, in the present embodiment, the number of first layout layers in the layout stack is 3 or 4.
In this embodiment, the preset angle α is not too large or too small. If the preset angle alpha is too large, in the metal lamination, the extending direction of the multi-layer metal wire is difficult to cover a plurality of directions in a circle of 360 degrees, so that the extending direction of the metal wire is easy to cause that the wiring requirement of the semiconductor structure for electric connection in all directions can be difficult to be met, and the application of the semiconductor structure is influenced; if the preset angle α is too small, the included angle between the extending directions of the metal wires of the adjacent layers is too small, which is easy to cause difficulty in forming the metal wires, and the number of metal layers in the metal laminate is too large, which causes unnecessary waste. For this reason, in the present embodiment, the preset angle α is 45 ° to 60 °.
As an example, fig. 8 shows a schematic diagram of a first layout layer in one layout stack, in which the preset angle α is 60 °, in this embodiment, the number of first layout layers in the layout stack is 3, that is, in this embodiment, the preset angle α is 60 °, and the number of metal layers in the metal stack is 3, that is, in the metal stack, the metal wires of the second metal layer are obtained by rotating the metal wires of the first metal layer by 60 ° counterclockwise, and the metal wires of the third metal layer are obtained by rotating the metal wires of the second metal layer by 60 ° counterclockwise, so that in each metal stack, the extending direction of the metal wires can be uniformly related to multiple directions covering 360 ° one circle by using fewer metal layers, therefore, the preset angle α is 60 °, in the metal stack, the number of metal layers is 3, which is a scheme with good regularity and good effect in this embodiment.
The via interconnect structure is used to electrically connect metal lines of adjacent two metal layers to each other.
In this embodiment, the via interconnection structure pattern 401 is located at the projection overlapping position of the adjacent two-layer metal line patterns 101 on the horizontal plane, that is, the via interconnection structure is located at the projection overlapping position of the adjacent two-layer metal lines on the horizontal plane, which increases the projection overlapping area of the adjacent two-layer metal line patterns 101 on the horizontal plane, that is, the projection overlapping area of the adjacent two-layer metal lines on the horizontal plane, thereby being beneficial to increasing the process window of the via interconnection structure between the adjacent two-layer metal lines, being beneficial to increasing the contact area between the via interconnection structure and the metal line correspondingly electrically connected, further being beneficial to reducing the contact resistance between the via interconnection structure and the metal line correspondingly electrically connected, and improving the working performance of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (15)
1. A semiconductor structure, comprising:
the metal layers are stacked from bottom to top, each metal layer comprises a plurality of metal wires which extend along a preset direction and are arranged in parallel along a direction perpendicular to the preset direction, and in two adjacent metal layers, the preset direction of each metal wire has a preset angle which is an acute angle;
and the through hole interconnection structures are positioned between the adjacent two metal layers, are positioned at the projection overlapping positions of the adjacent two metal lines on the horizontal plane, and are electrically connected with the corresponding adjacent two metal lines.
2. The semiconductor structure of claim 1, wherein a predetermined direction of the metal lines in any two adjacent metal layers of the plurality of metal layers stacked from bottom to top has the predetermined angle.
3. The semiconductor structure of claim 2, wherein the predetermined angles of any two adjacent metal layers are equal, or the predetermined angles of any two adjacent metal layers are partially equal, or the predetermined angles of any two adjacent metal layers are not equal.
4. The semiconductor structure of claim 1, wherein the plurality of metal layers stacked from bottom to top comprises a plurality of metal stacks stacked in a cycle, the metal stacks comprising adjacent plurality of metal layers, the number of metal layers in each of the metal stacks being equal.
5. The semiconductor structure of claim 4, wherein the plurality of metal lines in the metal stack from bottom to top are sequentially rotated in a specified direction by a predetermined angle, and the angle from the topmost metal line to the bottommost metal line in the specified direction is less than or equal to the predetermined angle, wherein the specified direction is counter-clockwise or clockwise.
6. The semiconductor structure of claim 4 or 5, wherein the number of metal layers in the metal stack is 3 or 4.
7. The semiconductor structure of any one of claims 1 to 5, wherein the predetermined angle is 45 ° to 60 °.
8. The semiconductor structure of claim 1, wherein the material of the metal line comprises one or more of copper, aluminum, and copper alloy.
9. A reticle layout, comprising:
The first layout layers comprise a plurality of metal wire patterns which extend along a preset direction and are arranged in parallel along a direction perpendicular to the preset direction, and in two adjacent first layout layers, the preset direction of the metal wire patterns has a preset angle which is an acute angle;
The second layout layer is positioned between the adjacent two layers of the first layout layers, and comprises through hole interconnection structure patterns positioned at the projection overlapping position of the adjacent two layers of metal line patterns on the horizontal plane.
10. The reticle layout of claim 9, wherein the predetermined direction of the metal line pattern has the predetermined angle in any two adjacent first layout layers among the plurality of first layout layers from bottom to top.
11. The reticle layout of claim 10, wherein the preset angles of any two adjacent first layout layers are equal, or the preset angles of any two adjacent first layout layers are partially equal, or the preset angles of any two adjacent first layout layers are unequal.
12. The reticle layout of claim 9, wherein the bottom-up plurality of first layout layers comprises a plurality of layout stacks arranged in a loop, the layout stacks comprising adjacent first layout layers, the first layout layers in each of the layout stacks being equal in number.
13. The reticle layout of claim 12, wherein in the layout stack, the plurality of metal line patterns from bottom to top are sequentially rotated by a predetermined angle in a specified direction, and the angle from the topmost metal line pattern to the bottommost metal line pattern in the specified direction is less than or equal to the predetermined angle, wherein the specified direction is counter-clockwise or clockwise.
14. The reticle layout of claim 12 or 13, wherein the number of first layout layers in the layout stack is 3 or 4.
15. The reticle layout of any one of claims 9 to 13, wherein the predetermined angle is 45 ° to 60 °.
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| CN202310087665.XA CN118412333A (en) | 2023-01-30 | 2023-01-30 | Semiconductor structure and mask layout |
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| CN202310087665.XA CN118412333A (en) | 2023-01-30 | 2023-01-30 | Semiconductor structure and mask layout |
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