CN118782586A - Internal power supply structure, semiconductor device and internal power supply monitoring method - Google Patents

Abstract

The present disclosure relates to the field of semiconductors, and discloses an internal power supply structure, a semiconductor device, and an internal power supply monitoring method, wherein the internal power supply structure includes: the power supply circuit includes a power supply generating circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitor wiring, and a pad. A power supply generating circuit having an output terminal coupled to the internal power supply wiring for generating an internal voltage; an internal power supply wiring coupled to the internal power supply monitoring wiring through the first switching circuit for transmitting an internal voltage; and an internal power supply monitoring wiring coupled to the pad for transmitting an internal voltage to the pad when the first switching circuit is turned on. Thus, when the first switch circuit is turned on, the internal voltage is led out to the pad so as to monitor the internal voltage generated by the power supply generating circuit. Under the condition that the first switch circuit is not conducted, internal voltage is prevented from being transmitted to the internal power supply monitoring wiring, interference possibly brought by the internal power supply monitoring wiring is eliminated, and inaccuracy of the internal voltage is avoided.

Description

Internal power supply structure, semiconductor device and internal power supply monitoring method

Technical Field

The present disclosure relates to the semiconductor field, and in particular to an internal power supply structure, a semiconductor device and an internal power supply monitoring method.

Background Art

In an integrated circuit, a fault or load may cause the power supply voltage to be abnormal, causing the voltage received by the electronic device to be abnormal, and thus the electronic device cannot work properly. Therefore, a voltage monitoring circuit that monitors the power supply voltage is usually added to the integrated circuit to determine whether the voltage output by the power supply is abnormal. Generally, the coupling effect between the wiring (wire) that transmits the internal power supply signal and other wiring (coupling effect) will cause the power supply signal to be damaged, which affects the accuracy of the monitoring result to a certain extent.

Summary of the invention

In view of this, the embodiments of the present disclosure provide an internal power supply structure, a semiconductor device, and an internal power supply monitoring method to prevent the coupling effect of wiring from interfering with the process of monitoring the power supply signal.

The technical solution of the present invention is achieved in this way:

An embodiment of the present disclosure provides an internal power supply structure, including: a power generation circuit, an internal power supply wiring, a first switching circuit, an internal power supply monitoring wiring and a pad; the power generation circuit, whose output end is coupled to the internal power supply wiring for generating an internal voltage; the internal power supply wiring, coupled to the internal power supply monitoring wiring through the first switching circuit, for transmitting the internal voltage; the internal power supply monitoring wiring, coupled to the pad, for transmitting the internal voltage to the pad when the first switching circuit is turned on.

In the above solution, the internal power supply wiring and the internal power supply monitoring wiring are arranged on the same layer.

In the above solution, the internal power supply structure also includes a second switch circuit; the second switch circuit is coupled to the internal power supply monitoring wiring and the pad respectively, and is used to transmit the internal voltage to the pad when it is turned on.

In the above solution, the first switch circuit and the second switch circuit are both transmission gate circuits.

An embodiment of the present disclosure also provides a semiconductor device, including an internal power supply structure as in the above solution.

In the above scheme, the semiconductor device includes: a substrate and a signal wiring arranged in a different layer from the internal power monitoring wiring; the projection of the signal wiring in a direction perpendicular to the substrate at least partially overlaps with the projection of the internal power monitoring wiring in a direction perpendicular to the substrate.

In the above scheme, the semiconductor device also includes: an internal power supply monitoring control circuit; an internal power supply monitoring control circuit, which is used to turn on the first switch circuit when the semiconductor device is in an internal power supply monitoring mode; or to turn off the first switch circuit when the semiconductor device is in a non-internal power supply monitoring mode.

In the above solution, the semiconductor device is a semiconductor memory.

In the above solution, the signal wiring is an address signal line, and the pad is a data input/output pad.

An embodiment of the present disclosure provides an internal power supply monitoring method, including: providing an internal power supply structure; the internal power supply structure includes: a power supply generating circuit, an internal power supply wiring, a first switching circuit, an internal power supply monitoring wiring and a pad; the output end of the power supply generating circuit is coupled to the internal power supply wiring; the internal power supply wiring is coupled to the internal power supply monitoring wiring through the first switching circuit; the internal power supply monitoring wiring is coupled to the pad; an internal voltage is generated by the power supply generating circuit; the first switching circuit is turned on, and the internal voltage is transmitted to the pad through the internal power supply monitoring wiring.

In the above scheme, the internal power supply structure also includes a second switching circuit; the second switching circuit is respectively coupled to the internal power supply monitoring wiring and the pad; after the first switching circuit is turned on, the internal power supply monitoring method also includes: turning on the second switching circuit to transmit the internal voltage to the pad.

In the disclosed embodiment, the internal power supply structure includes: a power supply generating circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring and a pad. The power supply generating circuit, whose output end is coupled to the internal power supply wiring, is used to generate an internal voltage; the internal power supply wiring is coupled to the internal power supply monitoring wiring through the first switch circuit, and is used to transmit the internal voltage; the internal power supply monitoring wiring is coupled to the pad, and is used to transmit the internal voltage to the pad when the first switch circuit is turned on. In this way, the transmission process of the internal voltage can be controlled based on the conduction state of the first switch circuit; when the first switch circuit is turned on, the internal voltage is led out to the pad through the internal power supply monitoring wiring, so as to monitor the internal voltage generated by the power supply generating circuit. When the first switch circuit is not turned on, the internal voltage can be prevented from being transmitted to the internal power supply monitoring wiring, thereby eliminating the interference that may be caused by the internal power supply monitoring wiring and avoiding inaccurate internal voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a structural schematic diagram 1 of an internal power supply structure provided by an embodiment of the present disclosure;

FIG2 is a second structural diagram of an internal power supply structure provided in an embodiment of the present disclosure;

FIG3 is a schematic diagram of a circuit principle of an internal power supply structure provided by an embodiment of the present disclosure;

FIG4 is a schematic diagram 1 of a semiconductor device provided in an embodiment of the present disclosure;

FIG5 is a schematic diagram of a layout of a semiconductor device provided in an embodiment of the present disclosure;

FIG6 is a second schematic diagram of a semiconductor device provided in an embodiment of the present disclosure;

FIG7 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present disclosure;

FIG8 is a flow chart of an internal power supply detection method provided in an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

If similar descriptions of "first/second" appear in the application documents, the following description is added. In the following description, the terms "first/second/third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first/second/third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

FIG1 is a schematic diagram of an optional internal power supply structure provided by an embodiment of the present disclosure, wherein the internal power supply structure 100 includes: a power supply generating circuit 10, an internal power supply wiring 20, a first switch circuit 30, an internal power supply monitoring wiring 40, and a pad 50. The power supply generating circuit 10, whose output end is coupled to the internal power supply wiring 20, is used to generate an internal voltage. The internal power supply wiring 20 is coupled to the internal power supply monitoring wiring 40 through the first switch circuit 30, and is used to transmit the internal voltage. The internal power supply monitoring wiring 40 is coupled to the pad 50, and is used to transmit the internal voltage to the pad 50 when the first switch circuit 30 is turned on.

It should be noted that the internal voltage may be any voltage in the integrated circuit that needs to be monitored. For example, the internal voltage may be one or more of voltages such as voltage VBB and voltage VKK.

It should also be noted that, referring to FIG. 1 , the internal power monitoring wiring 40 coupled to the pad 50 means that the internal power monitoring wiring 40 is directly connected to the pad 50 or is indirectly connected to the pad 50 through other structures.

In the embodiment of the present disclosure, with continued reference to FIG. 1, when the first switch circuit 30 is turned on, the internal voltage generated by the power generation circuit 10 can be transmitted to the internal power monitoring wiring 40 through the internal power wiring 20, and then transmitted to the pad 50. That is, when the first switch circuit 30 is turned on, the internal voltage is led to the pad 50. Thus, the internal voltage generated by the power generation circuit 10 can be monitored by monitoring the parameter changes of the pad 50.

In the embodiment of the present disclosure, with continued reference to FIG. 1, the internal power supply structure 100 can be arranged in a semiconductor device such as a memory; the internal power supply monitoring wiring 40 can be arranged in the conductor layer of the semiconductor device. The length of the internal power supply monitoring wiring 40 is usually very long. In the extension direction of the internal power supply monitoring wiring 40, some sections of the internal power supply monitoring wiring 40 are likely to be parallel to other wirings, so that the internal power supply monitoring wiring 40 is likely to produce a coupling effect with other wirings in the conductor layer of the semiconductor device. In other words, if the signal transmitted on other wirings in the semiconductor device changes, the signal transmitted on the internal power supply monitoring wiring 40 will be distorted. For example, if the internal voltage is transmitted to the internal power supply detection wiring 40, if the signal transmitted on other wirings in the semiconductor device jumps, the internal voltage will be inaccurate. Therefore, the embodiment of the present disclosure introduces a first switching circuit 30 between the internal power supply wiring 20 and the internal power supply monitoring wiring 40; furthermore, the internal power supply wiring 20 and the internal power supply monitoring wiring 40 can be disconnected by controlling the first switching circuit 30, so that the internal voltage generated by the power supply generating circuit 10 cannot be transmitted to the internal power supply monitoring wiring 40, and the internal voltage will not be interfered by other wirings in the semiconductor device, thereby avoiding inaccurate internal voltage.

It can be understood that the embodiment of the present disclosure couples the internal power supply wiring with the internal power supply monitoring wiring through the first switch circuit. In this way, the transmission process of the internal voltage can be controlled based on the conduction state of the first switch circuit; when the first switch circuit is turned on, the internal voltage is led out to the pad through the internal power supply monitoring wiring to facilitate monitoring of the internal voltage generated by the power supply generating circuit. When the first switch circuit is not turned on, the internal voltage can be prevented from being transmitted to the internal power supply monitoring wiring, thereby eliminating the interference that may be caused by the internal power supply monitoring wiring and avoiding inaccurate internal voltage.

FIG. 2 is a schematic diagram of another optional internal power supply structure provided in an embodiment of the present disclosure.

In some other embodiments of the present disclosure, referring to FIG. 2 , the internal power supply structure 100 further includes a second switch circuit 60 ; the second switch circuit 60 is respectively coupled to the internal power supply monitoring wiring 40 and the pad 50 , and is used to transmit the internal voltage to the pad 50 when the second switch circuit 60 is turned on.

In the embodiment of the present disclosure, referring to FIG. 2, the pad 50 is usually connected to multiple wires, corresponding to receiving multiple signals. For example, the pad 50 can be a data input/output pad (DQ PAD); the input/output pad receives signals such as data signals (DQ) in addition to the internal voltage. In this way, when the internal power monitoring wiring 40 is directly connected to the pad 50, other signals (such as data signals DQ) received by the pad 50 will be transmitted to the internal power monitoring wiring 40; thus, the signals transmitted by other wirings coupled to the internal power monitoring wiring 40 will be interfered by the data signal (DQ). Therefore, the embodiment of the present disclosure introduces a second switch circuit 60 between the internal power monitoring wiring 40 and the pad 50; furthermore, the internal power monitoring wiring 40 and the pad 50 can be disconnected by controlling the second switch circuit 60, so that other signals received by the pad 50 cannot be transmitted to the internal power monitoring wiring 40. Thus, it is possible to avoid mutual interference between the internal power monitoring wiring 40 and the wiring having a coupling effect therewith.

FIG3 is a schematic diagram of a circuit principle of an optional internal power supply structure provided in an embodiment of the present disclosure. It should be noted that the first transistor MP1 and the third transistor MP2 may be PMOS transistors (Positive channel Metal Oxide Semiconductor, PMOS); the second transistor MN1 and the fourth transistor MN2 may be NMOS transistors (Negative channel Metal Oxide Semiconductor, NMOS).

In some embodiments of the present disclosure, referring to FIG. 3 , the first switch circuit 30 and the second switch circuit 60 are both transmission gate circuits.

In the embodiment of the present disclosure, referring to FIG. 3 , the transmission gate circuit forming the first switch circuit 30 includes a first transistor MP1 and a second transistor MN1. The source of the first transistor MP1 and the source of the second transistor MN1 are both connected to the internal power supply wiring 20, and the drain of the first transistor MP1 and the drain of the second transistor are both connected to the internal power supply monitoring wiring 40. The gate of the first transistor MP1 is connected to the first control signal terminal C', and the gate of the second transistor MN1 is connected to the second control signal terminal C. In this way, the conduction or disconnection of the first switch circuit 30 can be controlled by controlling the level state of the signal input to the first control signal terminal C' and the second control signal terminal C. For example, a low-level control signal is transmitted to the first control signal terminal C' of the first transistor MP1, and a high-level control signal is transmitted to the second control signal terminal C of the second transistor MN1, and the first switch circuit 30 is disconnected. A high-level control signal is transmitted to the first control signal terminal C' of the first transistor MP1, and a low-level control signal is transmitted to the second control signal terminal C of the second transistor MN1, and the first switch circuit 30 is turned on.

In the embodiment of the present disclosure, referring to FIG. 3 , the transmission gate circuit forming the second switch circuit 60 includes a first transistor MP2 and a fourth transistor MN2. The source of the third transistor MP2 and the source of the fourth transistor MN2 are both connected to the internal power supply monitoring wiring 40. The drain of the third transistor MP2 and the drain of the fourth transistor MN2 are both connected to the pad 50. The gate of the third transistor MP2 is connected to the third control signal terminal D', and the gate of the fourth transistor MN2 is connected to the fourth control signal terminal D. In this way, the conduction state of the second switch circuit 60 can be controlled by controlling the level state of the signal input to the third control signal terminal D' and the fourth control signal terminal D of the second switch circuit 60. For example, a low-level control signal is transmitted to the third control signal terminal D' of the third transistor MP2, and a high-level control signal is transmitted to the fourth control signal terminal D of the fourth transistor MN2, and the second switch circuit 60 is disconnected. A high-level control signal is transmitted to the third control signal terminal D' of the third transistor MP2, and a low-level control signal is transmitted to the second control signal terminal D of the fourth transistor MN2, and the second switch circuit 60 is turned on.

In some embodiments of the present disclosure, referring to FIG. 2 , the internal power supply wiring 20 and the internal power supply monitoring wiring 40 are arranged on the same layer.

Figure 4 specifically illustrates the positional relationship of the metal layers, and Figures 5 and 6 specifically illustrate the positional relationship of the signal wiring and the internal power monitoring wiring. Figure 4 is a side view, Figure 5 is a top view, and the cross-sectional view of Figure 6 is at AA' in Figure 5.

It should be noted that in the direction Z perpendicular to the substrate, the metal layers M0, M1 and M2 are arranged in sequence. In Figures 5 and 6, VKKR and VBBR are both internal power monitoring wiring, where VKKR is the wiring for monitoring the internal voltage VKK, and VBBR is the wiring for monitoring the internal voltage VBB. In Figure 6, A6 and BA0 are both signal wirings; A6 is a row and column common address line; BA0 is the wiring for transmitting the bank selection signal. In Figure 6, the signal wiring A6 is connected to the A6 PAD, and the signal wiring BA0 is connected to the BA0PAD.

In the disclosed embodiment, in combination with FIG. 4 and FIG. 6, the internal power supply structure can be provided in a semiconductor device such as a semiconductor memory. A semiconductor device generally includes a plurality of metal layers; for example, a semiconductor device includes metal layers M0, M1, and M2. The internal power supply wiring and the internal power supply monitoring wiring can be provided in the same metal layer. For example, the internal power supply monitoring wiring VKKR and the internal power supply monitoring wiring VBBR are both provided in the first metal layer M1, and the internal power supply wiring can also be provided in the first metal layer M1. Both the internal power supply wiring and the internal power supply monitoring wiring can be connected to the first switching circuit through components such as contact structures.

The embodiment of the present disclosure further provides a semiconductor device 200 . Referring to FIG. 7 , the semiconductor device 200 includes the internal power structure 100 of the present disclosure.

In some embodiments of the present disclosure, a semiconductor device includes: a substrate and a signal wiring arranged in a different layer from an internal power monitoring wiring; a projection of the signal wiring along a direction perpendicular to the substrate at least partially overlaps with a projection of the internal power monitoring wiring along a direction perpendicular to the substrate.

In the embodiment of the present disclosure, in conjunction with Figures 5 and 6, the signal wiring and the internal power monitoring wiring are arranged in different layers. For example, the internal power monitoring wiring (VKKR and VBBR) are both located in the first metal layer M1, and the signal wiring (A6 and BA0) are both located in the second metal layer M2.

In the embodiment of the present disclosure, in combination with Figures 5 and 6, the projection of the signal wiring along the direction Z perpendicular to the substrate at least partially overlaps with the projection of the internal power monitoring wiring along the direction Z perpendicular to the substrate. For example, in the direction Z perpendicular to the substrate, the projection of the signal wiring A6 and the projection of the internal power monitoring wiring VBBR have an overlapping area S.

It should be noted that, in combination with FIG. 5 and FIG. 6 , the positional relationship between the signal wiring BA0 and the internal power monitoring wiring (VKKR and VBBR) can be understood by referring to the signal wiring A6 in FIG. 6 .

In the disclosed embodiment, in combination with FIG. 5 and FIG. 6 , the length of the internal power monitoring wiring is longer than that of some wirings in the semiconductor device; for example, the length of the internal power monitoring wiring VKKR is 6829um, and the length of the signal wiring A6 is 850um. In the wiring structure of the semiconductor memory, the internal power monitoring wiring is likely to have a parallel section with the signal wiring, so that the internal power monitoring wiring will have a coupling effect with some signal wirings.

It should be noted that the signal wiring and the internal power monitoring wiring can also be located on the same metal layer.

It should also be noted that during the operation of the semiconductor memory, the signal wiring will switch signals; the signal wiring A6 and the signal wiring BA0 are only used as examples for illustration and are not limited to these two signal wirings.

In the disclosed embodiment, in combination with Figures 5 and 6, in the extension direction of the internal power monitoring wiring (VKKR and VBBR), some sections of the internal power monitoring wiring will be parallel to the signal wiring (A6 and BA0), so that the internal power monitoring wiring will produce a coupling effect with the signal wiring. In other words, the internal power monitoring wiring will produce parasitic capacitance with the signal wiring. Furthermore, in the case where the internal voltage is transmitted to the internal power detection wiring, if the signal transmitted on the signal wiring jumps and the parasitic capacitance discharges, the internal voltage will be inaccurate. Therefore, it is necessary to introduce a first switching circuit and a second switching circuit to disconnect the signal connected to the internal power monitoring wiring to avoid mutual interference between the internal power monitoring wiring and the signal wiring.

It should be noted that, referring to FIG5 , in general, shielding wires are added on both sides of the signal wiring to perform electrostatic shielding on the signal wiring; thereby, the coupling effect between the signal wiring and other wirings is reduced, and the mutual interference between the signal wiring and other wirings is reduced. For example, shielding wires VSS are provided on both sides of the signal wiring (A6 and BA0); the shielding wires VSS are grounded; thereby, the mutual interference between adjacent signal wirings (A6 and BA0) is reduced.

It should also be noted that the metal layer M0 in FIG. 4 is not shown in FIG. 6 ; the metal layer M0 is also provided with wiring.

In the disclosed embodiment, referring to FIG6 , the shielding wires VSS arranged on both sides of the signal wiring A6 weaken the mutual interference between the signal wiring A6 and other wirings to a certain extent. However, the signal wiring A6 and the wiring arranged on different layers will also interfere with each other to a certain extent; for example, the signal wiring A6 may interfere with the wiring arranged on the metal layers M0 and M1. When the semiconductor device is in a non-internal power monitoring mode, it is not necessary to monitor the internal voltage at this time. Therefore, the first switch circuit and the second switch circuit can be disconnected, and the internal power monitoring wiring is not connected to any signal. In other words, when the semiconductor device is in a non-internal power monitoring mode, since the internal power monitoring wiring is not connected to any signal, the internal power monitoring wiring can be used as a shielding wire for the signal wiring. Thereby, the coupling effect between the signal wiring and other wirings is further weakened, and the signal wiring is prevented from interfering with the wiring arranged on other different layers.

In some embodiments of the present disclosure, referring to FIG7 , the semiconductor device 200 further includes an internal power monitoring control circuit 201. The internal power monitoring control circuit 201 is used to turn on the first switch circuit 30 when the semiconductor device 200 is in the internal power monitoring mode; or to turn off the first switch circuit 30 when the semiconductor device 200 is not in the internal power monitoring mode.

In the disclosed embodiment, in combination with FIG. 5 and FIG. 7 , the semiconductor device 200 may be a semiconductor memory. When the semiconductor device 200 is in the internal power monitoring mode, the signal transmitted by the signal wiring (A6 and BA0) is not activated, and the internal power monitoring wiring (VBBR and VKKR) does not produce a coupling effect with the signal wiring (A6 and BA0). By turning on the first switch circuit 30 and the second switch circuit 60, the internal voltage generated by the power generation circuit can be transmitted to the pad along the internal power wiring and the internal power monitoring wiring, so that the internal voltage of the semiconductor device 200 can be monitored by detecting the parameter changes of the pad.

In the disclosed embodiment, in combination with Figures 5 and 7, when the semiconductor device 200 is in a non-internal power monitoring mode, the signal wiring (A6 and BA0) of the semiconductor device 200 will transmit signals, and the pads will transmit other signals, such as DQ signals. At this time, if the internal voltage is also transmitted to the internal power monitoring wiring (VBBR and VKKR), the signal transmitted by the signal wiring will affect the accuracy of the internal voltage. Therefore, the internal power structure 100 needs to introduce a first switching circuit 30 to disconnect the internal power wiring and the internal power monitoring wiring to prevent the internal voltage from being transmitted to the internal power monitoring wiring; introduce a second switching circuit 60 to disconnect the internal power monitoring wiring and the pads to prevent the pads from receiving other signals and transmitting them to the internal power monitoring wiring. Thereby, mutual interference between the internal power monitoring wiring and the signal wiring is avoided.

In the embodiment of the present disclosure, in combination with FIG. 3 and FIG. 7 , when the semiconductor device 200 is in a non-internal power monitoring mode, the internal power monitoring control circuit 201 can input a low-level control signal to the first control signal terminal C' of the first switch circuit 30, and input a high-level control signal to the second control signal terminal C of the first switch circuit 30, so as to turn off the first switch circuit 30; thereby, preventing the internal voltage generated by the power generation circuit 10 from being transmitted to the internal power monitoring wiring 40. Alternatively, when the semiconductor device 200 is in an internal power monitoring mode, the internal power monitoring control circuit 201 can input a high-level control signal to the first control signal terminal C' of the first switch circuit 30, and input a low-level control signal to the second control signal terminal C of the first switch circuit 30, so as to turn on the first switch circuit 30, thereby transmitting the internal voltage generated by the power generation circuit 10 to the internal power monitoring wiring 40.

In the embodiment of the present disclosure, in combination with FIG. 3 and FIG. 7 , when the semiconductor device 200 is in a non-internal power monitoring mode, the internal power monitoring control circuit 201 can input a low-level control signal to the third control signal terminal D’ of the second switch circuit 60, and input a high-level control signal to the fourth control signal terminal D of the second switch circuit 60, to turn off the second switch circuit 60; thereby, preventing other signals received by the pad 50 from being transmitted to the internal power monitoring wiring 40. Alternatively, when the semiconductor device 200 is in an internal power monitoring mode, the internal power monitoring control circuit 201 can input a high-level control signal to the third control signal terminal D’ of the second switch circuit 60, and input a low-level control signal to the fourth control signal terminal D of the second switch circuit 60, to turn on the second switch circuit 60, thereby transmitting the internal voltage of the internal power monitoring wiring 40 to the pad 50.

In some embodiments of the present disclosure, referring to FIG. 7 , the semiconductor device 200 is a semiconductor memory.

In the disclosed embodiment, the semiconductor device 200 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like.

In some embodiments of the present disclosure, the signal wiring may be an address signal line, and the pad may be a data input/output pad.

In the embodiment of the present disclosure, referring to FIG5, when the semiconductor device is a semiconductor memory, the signal wiring may be an address signal line. The address signal line may be one or more of the row-column common address lines in the semiconductor memory; for example, the address signal line is the row-column common address line A6. The row-column common address line A6 may be used to transmit signals such as a row selection signal RAS and a column selection signal CAS. The address signal line may also be a selection signal wiring; for example, the address signal line is a selection signal wiring BA0. The selection signal wiring BA0 may be used to transmit a storage body selection signal.

In the embodiment of the present disclosure, referring to Fig. 2, pad 50 may be a data input/output pad. When the semiconductor device is in the internal power monitoring mode, pad 50 is used to transmit the internal voltage; when the semiconductor device is in the non-internal power monitoring mode, pad 50 is used to transmit the data signal.

FIG8 is a schematic flow chart of an optional internal power supply monitoring method provided in an embodiment of the present disclosure, which will be described in conjunction with the steps shown in FIG8 .

It should be noted that the internal power supply monitoring method shown in FIG. 8 can be implemented through the internal power supply structure shown in FIG. 1 .

S101. Provide an internal power supply structure; the internal power supply structure includes: a power supply generating circuit, an internal power supply wiring, a first switching circuit, an internal power supply monitoring wiring and a pad; the output end of the power supply generating circuit is coupled to the internal power supply wiring; the internal power supply wiring is coupled to the internal power supply monitoring wiring through the first switching circuit; the internal power supply monitoring wiring is coupled to the pad.

In the disclosed embodiment, the internal power supply wiring is coupled to the internal power supply monitoring wiring via the first switch circuit, so that the conduction state of the first switch circuit can control the transmission process of the internal voltage.

S102 , generating an internal voltage by a power generation circuit.

S103, turning on the first switch circuit, and transmitting the internal voltage to the pad through the internal power monitoring wiring.

In the embodiment of the present disclosure, when the first switch circuit is turned on, the internal voltage can be led out to the pad, so as to monitor the internal voltage generated by the power generation circuit. When the first switch circuit is not turned on, the internal voltage can be prevented from being transmitted to the internal power monitoring wiring, thereby eliminating the interference that may be caused by the internal power monitoring wiring. In this way, regardless of whether the internal power monitoring wiring and the internal power wiring are located in the same metal layer; as long as there is a coupling effect between the internal power monitoring wiring and the internal power wiring, which causes interference to the internal voltage, the method in the embodiment of the present disclosure can be used to introduce the first switch circuit between the internal power monitoring wiring and the internal power wiring, disconnect the internal power monitoring wiring and the internal power wiring; thereby eliminating the interference of the jump signal on the internal voltage and avoiding inaccurate internal voltage.

In some embodiments of the present disclosure, S103 shown in FIG. 8 may be implemented by S1031, and will be described in conjunction with S1031.

S1031, turning on the second switch circuit to transmit the internal voltage to the pad.

It should be noted that S1031 can be implemented by the internal power supply structure shown in FIG. 2 .

In the disclosed embodiment, the internal power supply structure also includes a second switch circuit; the second switch circuit couples the internal power supply monitoring wiring and the pad, respectively. Therefore, after the first switch circuit is turned on, the second switch circuit also needs to be turned on, so that the internal voltage can be transmitted to the pad. In this way, the second switch circuit is introduced between the internal power supply monitoring wiring and the pad; then, the internal power supply monitoring wiring and the pad can be disconnected by controlling the second switch circuit, so that other signals received by the pad cannot be transmitted to the internal power supply monitoring wiring. Thus, mutual interference between the internal power supply monitoring wiring and the wiring with a coupling effect can be avoided.

In some embodiments of the present disclosure, the internal power supply wiring and the internal power supply monitoring wiring are arranged on the same layer.

In some embodiments of the present disclosure, the first switch circuit and the second switch circuit are both transmission gate circuits.

In some embodiments of the present disclosure, an internal power supply structure is arranged in a semiconductor device; the semiconductor device includes: a substrate and a signal wiring arranged in a different layer from the internal power supply monitoring wiring; the projection of the signal wiring along a direction perpendicular to the substrate at least partially overlaps with the projection of the internal power supply monitoring wiring along a direction perpendicular to the substrate.

In some embodiments of the present disclosure, the semiconductor device also includes: an internal power supply monitoring control circuit; an internal power supply monitoring control circuit, used to turn on the first switching circuit when the semiconductor device is in an internal power supply monitoring mode; or to turn off the first switching circuit when the semiconductor device is in a non-internal power supply monitoring mode.

In some embodiments of the present disclosure, the semiconductor device is a semiconductor memory.

In some embodiments of the present disclosure, the signal wiring is an address signal line, and the pad is a data input/output pad.

It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (11)

1. An internal power supply structure, characterized in that it comprises: a power generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring and a pad; The power generation circuit has an output terminal coupled to the internal power wiring for generating an internal voltage; The internal power supply wiring is coupled to the internal power supply monitoring wiring through the first switch circuit and is used to transmit the internal voltage; The internal power monitoring wiring is coupled to the pad and is used to transmit the internal voltage to the pad when the first switch circuit is turned on. 2 . The internal power supply structure according to claim 1 , wherein the internal power supply wiring and the internal power supply monitoring wiring are arranged on the same layer. 3 . 3. The internal power supply structure according to claim 2, characterized in that the internal power supply structure further comprises a second switch circuit; The second switch circuit is coupled to the internal power monitoring wiring and the pad, respectively, and is used to transmit the internal voltage to the pad when the second switch circuit is turned on. 4 . The internal power supply structure according to claim 3 , wherein the first switch circuit and the second switch circuit are both transmission gate circuits. 5. A semiconductor device, characterized in that it comprises the internal power supply structure according to any one of claims 1 to 4. 6. The semiconductor device according to claim 5 is characterized in that the semiconductor device comprises: a substrate and a signal wiring arranged in a different layer from the internal power monitoring wiring; the projection of the signal wiring along a direction perpendicular to the substrate at least partially overlaps with the projection of the internal power monitoring wiring along a direction perpendicular to the substrate. 7. The semiconductor device according to claim 6, characterized in that the semiconductor device further comprises: an internal power supply monitoring control circuit; The internal power monitoring control circuit is used to turn on the first switch circuit when the semiconductor device is in the internal power monitoring mode; or to turn off the first switch circuit when the semiconductor device is in the non-internal power monitoring mode. 8 . The semiconductor device according to claim 7 , wherein the semiconductor device is a semiconductor memory. 9 . The semiconductor device according to claim 8 , wherein the signal wiring is an address signal line, and the pad is a data input/output pad. 10. A method for monitoring an internal power supply, comprising: An internal power supply structure is provided; the internal power supply structure comprises: a power supply generating circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring and a pad; the output end of the power supply generating circuit is coupled to the internal power supply wiring; the internal power supply wiring is coupled to the internal power supply monitoring wiring through the first switch circuit; the internal power supply monitoring wiring is coupled to the pad; generating an internal voltage by the power generation circuit; The first switch circuit is turned on to transmit the internal voltage to the pad through the internal power monitoring wiring. 11. The internal power monitoring method according to claim 10, wherein the internal power structure further comprises a second switch circuit; the second switch circuit is respectively coupled to the internal power monitoring wiring and the pad; After the first switch circuit is turned on, the internal power supply monitoring method further includes: The second switch circuit is turned on to transmit the internal voltage to the pad.