CN119447118A - Semiconductor structure and method for forming the same - Google Patents
Semiconductor structure and method for forming the same Download PDFInfo
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- CN119447118A CN119447118A CN202310945583.4A CN202310945583A CN119447118A CN 119447118 A CN119447118 A CN 119447118A CN 202310945583 A CN202310945583 A CN 202310945583A CN 119447118 A CN119447118 A CN 119447118A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims description 50
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 8
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 8
- 239000007772 electrode material Substances 0.000 claims description 8
- 229910004541 SiN Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 229910015801 BaSrTiO Inorganic materials 0.000 claims description 4
- 229910004129 HfSiO Inorganic materials 0.000 claims description 4
- 229910002370 SrTiO3 Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 229910052593 corundum Inorganic materials 0.000 claims description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 3
- 230000016507 interphase Effects 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 349
- 239000003990 capacitor Substances 0.000 description 41
- 230000009286 beneficial effect Effects 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Abstract
一种半导体结构及其形成方法，结构包括：基底；多个立柱，凸立于基底，立柱的俯视形貌为多边形，相邻立柱的边相对排布；多个沟槽，每个沟槽包围立柱，多个沟槽相连通；多层堆叠的电极层，多层电极层中，最底层的电极层覆盖沟槽的各个表面、以及立柱的表面，其余电极层在最底层的电极层上依次堆叠，多层电极层填充沟槽；介质层，位于相邻电极层之间。本发明有利于节约占用面积，提高半导体结构的集成度。
A semiconductor structure and a method for forming the same, the structure comprising: a substrate; a plurality of columns protruding from the substrate, the columns having a polygonal top view, and the sides of adjacent columns arranged relative to each other; a plurality of grooves, each of which surrounds a column, and the plurality of grooves are connected; a plurality of stacked electrode layers, wherein the bottom electrode layer covers the surfaces of the grooves and the surfaces of the columns, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, and the plurality of electrode layers fill the grooves; and a dielectric layer located between adjacent electrode layers. The present invention is conducive to saving occupied area and improving the integration of semiconductor structures.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Deep trench capacitors (DEEP TRENCH Capacitor, DTC) are widely used for antenna matching, radio frequency filtering and IC decoupling, especially in applications with high and volume limitations, yet have very high stability at high bias voltages, very low leakage currents, and play a vital role in some industrial fields.
Silicon-based capacitors are comprehensively replacing the ceramic capacitors in the markets of smart phones AP and PMIC terminals by their irreplaceable advantages of miniaturization, high stability, low ESR/ESL, etc. The high-density DTC increases the effective area of the capacitor through the three-dimensional structural design, thereby improving the capacitor density.
A common design at present is a parallel or vertical planar structure of vertical slots, the area of a capacitor cell (unit cell) is changed by changing the length of the vertical slots, and then structures with different requirements of customers are built by parallel connection of the unit cells. Such structural design interconnect plugs (CTs) are typically used to extract the CTs at the periphery of the cell by etching the plates to expose the underlying plates.
As the number of DTCs increases, the number of plates increases, and it becomes difficult to design a multi-layer plate extraction CT.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to saving occupied area and improving the integration level of the semiconductor structure.
In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a plurality of upright posts, a plurality of grooves, a plurality of stacked electrode layers, a plurality of dielectric layers and a dielectric layer, wherein the upright posts are convexly arranged on the substrate, the top view of the upright posts is polygonal, the edges of the adjacent upright posts are oppositely arranged, each groove surrounds the upright posts, the grooves are communicated, the electrode layers of the plurality of stacked electrode layers cover all surfaces of the grooves and the surfaces of the upright posts, the rest electrode layers are sequentially stacked on the electrode layer of the bottommost layer, the grooves are filled with the plurality of electrode layers, and the dielectric layer is positioned between the adjacent electrode layers.
Optionally, the plurality of stand columns extending and arranging along the first direction form a stand column group, the plurality of stand columns comprise a plurality of stand column groups arranged in parallel along the second direction, the number of layers of the electrode layers is n, in the adjacent n stand column groups, the stand column of each stand column group is respectively exposed out of the surfaces of each electrode layer in the n electrode layers, and the first direction is perpendicular to the second direction.
Optionally, the surfaces of the 1 st to n th electrode layers are sequentially exposed on the column groups sequentially arranged along the second direction in the adjacent n column groups.
Optionally, the semiconductor structure further comprises a plurality of interconnection plugs, a plurality of interconnection wires and a plurality of interconnection wires, wherein the interconnection plugs are positioned on the electrode layers exposed on the upright posts and are electrically connected with the corresponding electrode layers, the interconnection wires extend along the first direction and are positioned at the tops of the interconnection plugs on the corresponding upright post groups, and the interconnection wires positioned at the tops of the interconnection plugs of the electrode layers on the same layer are connected in parallel.
Optionally, among the plurality of interconnect lines, the interconnect line located on top of the interconnect plug of the electrode layer of the inter-layer is connected in parallel.
Optionally, the top-view polygonal shape of the upright post is a hexagon.
Optionally, the semiconductor structure further comprises a through hole interconnection structure, wherein the plurality of upright posts form hexagonal honeycomb upright post units, and the plurality of upright post units enclose an annular structure surrounding the through hole interconnection structure.
Optionally, the dielectric layer comprises one or more of HfO2, hfSiO, tiO2, hfZrO, hfSiON, hfTaO, hfTiO, ta O5, zrO2, zrSiO2, al2O3, srTiO3, baSrTiO and SiN, and the material of the electrode layer comprises one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate and a material layer positioned on the substrate, forming a plurality of grooves penetrating through the material layer, forming a plurality of columns protruding from the substrate by the residual material layer, arranging the edges of the adjacent columns oppositely in a overlooking mode, surrounding the columns by each groove, communicating the grooves, forming a plurality of stacked electrode layers and dielectric layers, wherein the electrode layer at the bottommost layer covers each surface of the grooves and the surface of the columns in the plurality of electrode layers, the other electrode layers are sequentially stacked on the electrode layer at the bottommost layer, the grooves are filled by the plurality of electrode layers, and the dielectric layers are positioned between the adjacent electrode layers.
Optionally, in the step of forming the electrode layer, the number of layers of the electrode layer is n, and the surface of each electrode layer in the n electrode layers is exposed on the upright post of each upright post group respectively.
Optionally, in the step of forming the electrode layer, the surfaces of the 1 st to n th electrode layers are sequentially exposed on the pillar groups sequentially arranged along the second direction in the adjacent n pillar groups.
Optionally, the step of forming the multi-layer stacked electrode layers includes forming n electrode material layers stacked in sequence, and etching back portions of the electrode material layers so that the surface of each of the n electrode layers is exposed on the pillar of each pillar group of the adjacent n pillar groups.
Optionally, after forming the electrode layers and the dielectric layers of the multi-layer stack, the forming method further comprises forming a plurality of interconnection plugs on the exposed electrode layers on the pillars and electrically connected with the corresponding electrode layers, forming a plurality of interconnection lines on top of the interconnection plugs, the interconnection lines extending along the first direction and on top of the interconnection plugs on the corresponding pillar groups, and connecting the interconnection lines on top of the interconnection plugs on the same electrode layer in parallel.
Optionally, in the step of forming the plurality of interconnect lines, the interconnect lines on top of the interconnect plugs of the electrode layers of the inter-layer are connected in parallel.
Optionally, in the step of forming the plurality of pillars, the top-view polygonal pillars are hexagons.
Optionally, in the step of providing the substrate, a through hole interconnection structure penetrating through the material layer is formed in the material layer, and in the step of forming the plurality of stand columns, the plurality of stand columns form hexagonal honeycomb stand column units, and the plurality of stand column units enclose an annular structure surrounding the through hole interconnection structure.
Optionally, in the step of forming the electrode layers and the dielectric layers of the multi-layer stack, an atomic layer deposition process is used to form each electrode layer and each dielectric layer.
Optionally, in the step of forming the electrode layer and the dielectric layer of the multi-layer stack, the dielectric layer includes one or more of HfO2, hfSiO, tiO2, hfZrO, hfSiON, hfTaO, hfTiO, ta O5, zrO2, zrSiO2, al2O3, srTiO3, baSrTiO, and SiN, and the material of the electrode layer includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the semiconductor structure provided by the embodiment of the invention, a plurality of upright posts are raised on a substrate, the top view of each upright post is polygonal, the edges of adjacent upright posts are oppositely arranged, each upright post is surrounded by a plurality of grooves, the grooves are communicated, the electrode layer at the bottommost layer covers the surfaces of the grooves and the surfaces of the upright posts, the rest electrode layers are sequentially stacked on the electrode layer at the bottommost layer, and the grooves are filled with the electrode layers at the bottommost layer; in the embodiment of the invention, the top view appearance of the upright posts is polygonal, the edges of the adjacent upright posts are oppositely arranged, each of the plurality of grooves surrounds the upright post, the plurality of grooves are communicated, the plurality of upright posts are closely arranged, the grooves can be formed between the adjacent upright posts to provide space positions for the capacitor formed by the electrode layers, the flexibility of arrangement of the capacitor structure is improved, and a deep groove capacitor (DEEP TRENCH capacitor, DTC) structure is formed between the closely arranged adjacent upright posts, so that the occupied area is saved, and the integration level of the semiconductor structure is improved.
In the method for forming the semiconductor structure, a plurality of grooves penetrating through a material layer are formed, a plurality of stand columns protruding from a substrate are formed on the residual material layer, the stand columns are in a polygonal shape in overlook, the sides of the adjacent stand columns are arranged oppositely, each groove surrounds the stand columns, the plurality of grooves are communicated, a plurality of stacked electrode layers and dielectric layers are formed, the electrode layers at the bottommost layer among the plurality of electrode layers cover the surfaces of the grooves and the surfaces of the stand columns, the rest electrode layers are stacked on the electrode layers at the bottommost layer in sequence, the grooves are filled with the plurality of electrode layers, the dielectric layers are arranged between the adjacent electrode layers, the stand columns are in a polygonal shape in overlook, the sides of the adjacent stand columns are arranged oppositely, each groove surrounds the stand columns, the plurality of grooves are communicated, the stand columns are closely arranged, the grooves can be formed between the adjacent stand columns to provide space positions for capacitors formed by the electrode layers, the flexibility of the arrangement of the capacitor structure is improved, and the occupied area of the deep groove capacitor structure is formed between the adjacent stand columns closely arranged, in addition, the integration of the semiconductor structure is improved.
Drawings
FIGS. 1-2 are schematic diagrams of a semiconductor structure;
FIGS. 3-6 are schematic diagrams illustrating an embodiment of a semiconductor structure according to the present invention;
fig. 7 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The integration level of the semiconductor structure is required to be improved. The reason why the integration level is to be improved is now analyzed in conjunction with a semiconductor structure.
Fig. 1 to 2 are schematic structural views of a semiconductor structure.
Referring to fig. 1 to 2 in combination, fig. 2 is a cross-sectional view of one of the trenches of fig. 1, the semiconductor structure includes a substrate (not shown) including a device region and lead regions located at both sides of the device region in a first direction (as shown in Y-direction in fig. 1), a plurality of trenches 20 located in the substrate of the device region, a portion of the trenches extending in the first direction and being arranged in parallel in a second direction, a remaining portion of the trenches extending in the second direction and being arranged in parallel in the first direction, the first direction being perpendicular to the second direction, electrode layers 11 stacked in layers, the electrode layers 11 at the bottom layer covering respective surfaces of the trenches 20 and the substrate surface, the remaining electrode layers 11 stacked in sequence on the electrode layers 11 at the bottom layer, the electrode layers 11 filling the trenches 20 in layers at the bottom layer, exposing the electrode layer 11 surfaces adjacent to each other at intervals on the substrate in any one of the lead regions, dielectric layers (not shown) located between the adjacent electrode layers 11 on the substrate, interconnect plugs 30 extending on the electrode layers 11 exposed in the regions and electrically connecting the electrode layers 11.
Each electrode layer 11 in the trench 20 is used to form a Deep Trench Capacitor (DTC) structure, in order to load the electrode layers 11 with an electrical signal, an interconnection plug 30 needs to be formed on each electrode layer 11 to electrically connect the electrode layers 11 with the outside, and in order to form the interconnection plug 30 on each electrode layer 11, lead regions need to be formed on both sides of a device region additionally, each electrode layer 11 is etched in the lead regions so that each electrode layer 11 can be exposed, and thus the interconnection plug 30 needs to be formed on each electrode layer 11, resulting in that the DTC structure occupies too much area and affects the integration level of the semiconductor structure.
In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a plurality of upright posts, a plurality of grooves, a plurality of electrode layers stacked in multiple layers, a plurality of electrode layers, a plurality of dielectric layers and a dielectric layer, wherein the upright posts are convexly arranged on the substrate, the top view of the upright posts is polygonal, the edges of the adjacent upright posts are oppositely arranged, each groove surrounds the upright posts, the grooves are communicated, the electrode layers stacked in multiple layers cover the surfaces of the grooves and the surfaces of the upright posts, the rest electrode layers are stacked on the electrode layer at the bottommost layer in sequence, the grooves are filled with the multiple layers of electrode layers, and the dielectric layer is positioned between the adjacent electrode layers.
In the embodiment of the invention, the top view appearance of the upright posts is polygonal, the edges of the adjacent upright posts are oppositely arranged, each of the plurality of grooves surrounds the upright post, the plurality of grooves are communicated, the plurality of upright posts are closely arranged, the grooves can be formed between the adjacent upright posts to provide space positions for the capacitor formed by the electrode layers, the flexibility of arrangement of the capacitor structure is improved, and a deep groove capacitor (DEEP TRENCH capacitor, DTC) structure is formed between the closely arranged adjacent upright posts, so that the occupied area is saved, and the integration level of the semiconductor structure is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 3-6, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown.
Referring to fig. 3 to 6 in combination, the semiconductor structure includes a substrate 100, a plurality of pillars 110 protruding from the substrate 100, the pillars 110 having a polygonal shape in a top view, sides of adjacent pillars 110 being arranged opposite to each other, a plurality of trenches 200 each surrounding the pillars 110, the plurality of trenches 200 being in communication, a plurality of stacked electrode layers 201, wherein a lowermost electrode layer 201 covers each surface of the trenches 200 and a surface of the pillars 110, the remaining electrode layers 201 are stacked in sequence on the lowermost electrode layer 201, the plurality of electrode layers 201 filling the trenches 200, and a dielectric layer 260 between the adjacent electrode layers 201.
Fig. 4 is a cross-sectional view along AA of fig. 3, and for clarity of illustration, the interconnection lines in fig. 3 and 5 are illustrated only by wire frames.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures.
In this embodiment, the material of the substrate 100 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
The pillars 110 are configured to enclose a trench 200 with the substrate 100.
In this embodiment, the top view of the pillars 110 is polygonal, and the sides of the adjacent pillars 110 are arranged oppositely, so that the opposite sides of the adjacent pillars 110 form the grooves 200, and the sidewalls of the pillars 110 at the outermost periphery form the grooves 200, that is, the grooves 200 surround the pillars 110 to form the communicated grooves 200, so that the arrangement of the grooves 200 is dense and compact, the occupied area is saved, and the capacitor density of a Deep Trench Capacitor (DTC) structure formed in the grooves 200 is improved correspondingly, thereby improving the performance of the semiconductor structure.
In this embodiment, the top-view polygon of the pillar 110 is a hexagon.
The polygonal shape of the pillars 110 in the top view is a hexagon, and each corner of the pillars 110 is an obtuse angle, so that the pillars 110 are easy to form, and the electrode layer 201 formed in the trench 200 surrounding the hexagon is easy to form, and the edges of the adjacent pillars 110 are arranged relatively, so that each hexagonal pillar 110 can be closely adjacent one by one to form a compact honeycomb shape, and almost no extra unused area is formed between each hexagonal pillar 110, thereby being beneficial to further enabling the trench 200 to be densely and compactly arranged, further saving the occupied area, and further being beneficial to improving the integration level of the semiconductor structure.
Referring to fig. 6, in this embodiment, the semiconductor structure further includes a via interconnect structure 600.
The Via interconnect structure 600 is used to realize electrical connection in the longitudinal direction of the wafer and to realize the longitudinal stacking of the wafer, and in this embodiment, the Via interconnect structure 600 is a Through-Silicon-Via (TSV) structure.
In this embodiment, the plurality of pillars 110 form hexagonal honeycomb pillar cells, and the plurality of pillar cells enclose a ring structure surrounding the via interconnection structure 600.
Compared with a square structure with a plurality of square grooves forming a surrounding through hole interconnection structure, in this embodiment, the plurality of pillars 110 form hexagonal honeycomb pillar units, the plurality of pillar units enclose a ring structure surrounding the through hole interconnection structure 600, the honeycomb pillar units are more compactly arranged, the ring structure formed by the plurality of pillar units saves more occupied area, and the integration level of the semiconductor structure is improved.
Trench 200 is used to provide a spatial location for the formation of electrode layer 201 and dielectric layer 260.
In this embodiment, the trench 200 is a deep trench structure with a relatively large depth-to-width ratio, and the electrode layer 201 and the dielectric layer 260 formed in the trench 200 form a Deep Trench Capacitor (DTC) structure.
The electrode layer 201 serves as an electrode plate constituting a capacitor structure.
In this embodiment, among the electrode layers 201, the electrode layer 201 at the bottommost layer covers the surfaces of the trenches 200 and the surface of the pillars 110, and the remaining electrode layers 201 are stacked sequentially on the electrode layer 201 at the bottommost layer, and the electrode layers 201 fill the trenches 200, that is, in the trenches 200, the electrode layers 201 are stacked in a direction perpendicular to the sidewalls of the trenches 200, to form a DTC structure.
In this embodiment, the material of the electrode layer 201 is a conductive material. As one example, the material of the electrode layer 201 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
Dielectric layer 260 serves as an insulating layer in forming the capacitor structure for isolating adjacent electrode layers 201.
In this embodiment, the material of the dielectric layer 260 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The high-k dielectric material is selected, so that the capacitance value of the capacitor structure is improved, and the capacitance density is correspondingly improved.
Specifically, the dielectric layer 260 is a high-k dielectric layer formed by stacking, i.e., the dielectric layer 260 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easily deteriorated, and therefore, the thickness of the dielectric layer 260 can meet the process requirement and has better formation quality. To this end, the high-k dielectric material includes one or more of HfO2、HfSiO、TiO2、HfZrO、HfSiON、HfTaO、HfTiO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3、BaSrTiO and SiN.
In this embodiment, the dielectric layer 260 is ZAZ layers. Wherein, ZAZ layers include a first ZrO 2 layer, an Al 2O3 layer and a second ZrO 2 layer formed in a stacked manner. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.
In this embodiment, the top view of the pillars 110 is polygonal, the sides of the adjacent pillars 110 are arranged oppositely, each trench 200 surrounds the pillar 110 in the plurality of trenches 200, the plurality of trenches 200 are communicated, so that the plurality of pillars 110 are closely arranged, the trenches 200 can be formed between the adjacent pillars 110 to provide space positions for the capacitor formed by the electrode layer 201, flexibility of arrangement of the capacitor structure is increased, and deep trench capacitor structures are formed between the closely arranged adjacent pillars 110, which is beneficial to saving occupied area and improving the integration level of the semiconductor structure.
In this embodiment, the plurality of pillars 110 extending in the first direction (as shown in the Y direction in fig. 3) form a pillar group 111, the plurality of pillars 110 includes a plurality of pillar groups 111 arranged in parallel in the second direction (as shown in the X direction in fig. 3), the number of layers of the electrode layers 201 is n, surfaces of each of the n electrode layers 201 are exposed on the pillars 110 of each pillar group 111 in the adjacent n pillar groups 111, and the first direction is perpendicular to the second direction.
In the adjacent n pillar groups 111, the pillar 110 of each pillar group 111 exposes the surface of each electrode layer 201 in the n electrode layers 201, and the exposed surface of the electrode layer 201 is used for contacting with the interconnection plug, so that the electric signal is loaded to the corresponding electrode layer 201 through the interconnection plug.
In this embodiment, the pillars 110 enclose the trench 200, and the surface of the corresponding electrode layer 201 is exposed on each pillar 110, that is, the electrical signal loading of each electrode layer 201 can be realized above the pillar 110, without additional area for electrical connection of the electrode layers 201, which is beneficial to saving the occupied area, and the pillars 110 are regularly arranged into a plurality of pillar groups 111, the pillars 110 of each pillar group 111 expose the same electrode layer 201, and the pillars in each pillar group 111 are arranged along the first direction, so that the electrode layer 201 on the pillar 110 of each pillar group 111 is easy to be electrically connected with the interconnection line extending along the first direction, and the connection manner is simple, which is beneficial to realizing the capacitor structure.
In this embodiment, the surfaces of the 1 st to n th electrode layers 201 are sequentially exposed on the pillar groups 111 sequentially arranged in the second direction among the n pillar groups 111.
Among the n adjacent pillar groups 111, the pillar groups 111 sequentially arranged along the second direction sequentially expose the surfaces of the 1 st to n th electrode layers 201, so that the arrangement of the electrode layers 201 exposed on the pillar groups 111 has regularity, which is beneficial to the regular arrangement of the interconnection lines formed above the pillar groups 111 and the electrode layers 201, so that the semiconductor structure has a regular structure, and the structural design and formation are easy to realize.
Specifically, in this embodiment, fig. 3 shows an example in which the number of layers of the electrode layer 201 is 2, the first electrode layer 210 surface and the second electrode layer 220 surface in 2 layers of the electrode layer 201 are respectively exposed on the pillars 110 of each pillar group 111 among the adjacent 2 pillar groups 111, and fig. 5 shows an example in which the number of layers of the electrode layer 201 is 4, the 1 st to 4 th electrode layer 201 surfaces are sequentially exposed on the pillar groups 111 sequentially arranged along the second direction among the adjacent 4 pillar groups 111, and specifically the first electrode layer 210, the second electrode layer 220, the third electrode layer 230, and the fourth electrode layer 240 surfaces are sequentially exposed.
In this embodiment, the semiconductor structure further includes a plurality of interconnection plugs 300 disposed on the exposed electrode layers 201 on the pillars 110 and electrically connected to the corresponding electrode layers 201.
Interconnect plugs 300 are used to load electrical signals to corresponding electrode layers 201.
In this embodiment, the plurality of interconnection plugs 300 are located on the exposed electrode layer 201 on the pillar 110, so that no additional etching region is required to etch the electrode layer 201 to form the interconnection plugs 300, which is beneficial to saving the occupied area of the semiconductor structure.
In this embodiment, the material of the interconnect plug 300 is tungsten. In other embodiments, the material of the interconnect plug may also be cobalt or ruthenium.
In this embodiment, the semiconductor structure further includes a plurality of interconnect lines 400, wherein the interconnect lines 400 extend along the first direction and are located on top of the interconnect plugs 300 on the corresponding pillar groups 111, and the interconnect lines 400 located on top of the interconnect plugs 300 of the same electrode layer 201 are connected in parallel.
The interconnect line 400 is used to electrically connect with the interconnect plug 300 so as to load an electrical signal to the corresponding electrode layer 201 through the interconnect plug 300.
In this embodiment, the interconnection lines 400 extend along the first direction and are located at the top of the interconnection plugs 300 on the corresponding pillar groups 111, and the pillars 110 of the same pillar group 111 expose the same electrode layer 201, so that the same interconnection lines 400 load the same electrode layer 201 with an electrical signal, and the interconnection lines 400 located at the top of the interconnection plugs 300 of the same electrode layer 201 are connected in parallel, so that the same electrical signal is loaded on the same electrode layer 201 in the multi-layer electrode layer 201, thereby realizing the basic function of the deep trench capacitor structure.
In this embodiment, the material of the interconnection line 400 is tungsten. In other embodiments, the material of the interconnect lines may also be cobalt or ruthenium.
In this embodiment, among the plurality of interconnect lines 400, the interconnect lines 400 on top of the interconnect plugs 300 of the electrode layer 201 of the inter-layer are connected in parallel.
The interconnection lines 400 at the top of the interconnection plugs 300 of the electrode layers 201 at the spaced apart layers are connected in parallel, so that the same electric signal is loaded to the electrode layers 201 adjacent to each other at intervals, and thus, the electric connection lines of the multi-layer electrode layers 201 are simplified while the potential difference between the adjacent electrode layers 201 can be realized, the electric connection structure of the multi-layer electrode layers 201 is simple and easy to realize, and the formation cost of the semiconductor structure is saved.
Specifically, referring to fig. 3 and 5 in combination, in the present embodiment, by electrically connecting the interconnect line 400 on top of the interconnect plug 300 of the electrode layer 201 of the inter-layer by using the metal line 500 extending in the second direction, the interconnect line 400 on top of the interconnect plug 300 of the electrode layer 201 of the inter-layer is realized in parallel.
Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 7 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.
The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 7, a substrate 100, and a material layer 180 on the substrate 100 are provided.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures.
In this embodiment, the material of the substrate 100 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
The material layer 180 is used to provide a process platform for forming the capacitor structure.
In this embodiment, the material layer 180 and the substrate 100 are integrally formed, and the material of the material layer 108 is also silicon.
In the present embodiment, in the step of providing the substrate 100, a via interconnection structure 600 (shown in fig. 10) penetrating the material layer 180 is formed in the material layer 180.
The Via interconnect structure 600 is used to realize electrical connection in the longitudinal direction of the wafer and to realize the longitudinal stacking of the wafer, and in this embodiment, the Via interconnect structure 600 is a Through-Silicon-Via (TSV) structure.
Referring to fig. 8 to 10 in combination, fig. 9 is a cross-sectional view taken along the AA direction of fig. 8, a plurality of trenches 200 are formed through the material layer 180, the remaining material layer 180 forms a plurality of pillars 110 protruding from the substrate 100, the pillars 110 have a polygonal top view, sides of adjacent pillars 110 are arranged opposite to each other, each trench 200 surrounds a pillar 110, and the plurality of trenches 200 are in communication.
The pillars 110 are configured to enclose a trench 200 with the substrate 100.
In this embodiment, the top view of the pillars 110 is polygonal, and the sides of the adjacent pillars 110 are arranged oppositely, so that the opposite sides of the adjacent pillars 110 form the grooves 200, and the sidewalls of the pillars 110 at the outermost periphery form the grooves 200, that is, the grooves 200 surround the pillars 110 to form the communicated grooves 200, so that the arrangement of the grooves 200 is dense and compact, the occupied area is saved, and the capacitor density of a Deep Trench Capacitor (DTC) structure formed in the grooves 200 is improved correspondingly, thereby improving the performance of the semiconductor structure.
In the step of forming the pillars 110, in this embodiment, a plurality of pillars 110 extending in a first direction (as shown in the Y direction in fig. 8) form a pillar group 111, and the plurality of pillars 110 include a plurality of pillar groups 111 arranged in parallel in a second direction (as shown in the X direction in fig. 8), the first direction being perpendicular to the second direction.
The plurality of columns 110 extending and arranged along the first direction form the column group 111, and the plurality of columns 110 comprise the plurality of column groups 111 arranged in parallel along the second direction, so that the arrangement regularity of the plurality of columns 110 is good, the arrangement of the plurality of columns 110 is compact, and the occupied area is saved.
In this embodiment, in the step of forming the plurality of pillars 110, the polygonal shape of the pillars 110 in a plan view is a hexagon.
The polygon of the top view appearance of the upright posts 110 is a hexagon, and then each angle of the upright posts 110 is an obtuse angle, so that the upright posts 110 are easy to form, electrode layers formed in the grooves 200 surrounding the hexagon are easy to form, and moreover, the edges of the adjacent upright posts 110 are oppositely arranged, each hexagonal upright post 110 can be closely adjacent one by one to form a compact honeycomb appearance, and an area which is hardly used is hardly left between each hexagonal upright post 110, so that the arrangement of the grooves 200 is compact, the occupied area is further saved, and the integration level of the semiconductor structure is further improved.
Referring to fig. 10, in the step of forming the plurality of pillars 110 in this embodiment, the plurality of pillars 110 form hexagonal honeycomb-shaped pillar cells, and the plurality of pillar cells enclose a ring-shaped structure surrounding the via interconnection structure 600.
Compared with a square structure with a plurality of square grooves forming a surrounding through hole interconnection structure, in this embodiment, the plurality of pillars 110 form hexagonal honeycomb pillar units, the plurality of pillar units enclose a ring structure surrounding the through hole interconnection structure 600, the honeycomb pillar units are more compactly arranged, the ring structure formed by the plurality of pillar units saves more occupied area, and the integration level of the semiconductor structure is improved.
Trench 200 is used to provide a spatial location for the formation of subsequent electrode layers and dielectric layer 26.
In this embodiment, the trench 200 is a deep trench structure with a relatively large depth-to-width ratio, and the electrode layer and the dielectric layer formed in the trench 200 later form a Deep Trench Capacitor (DTC) structure.
Referring to fig. 11 to 13 in combination, fig. 12 is a cross-sectional view along the AA direction of fig. 11, a multi-layered stacked electrode layer 201 and a dielectric layer 260 are formed, wherein among the multi-layered electrode layers 201, the lowermost electrode layer 201 covers each surface of the trench 200 and the surface of the pillar 110, the remaining electrode layers 201 are sequentially stacked on the lowermost electrode layer 201, the multi-layered electrode layer 201 fills the trench 200, and the dielectric layer 260 is located between adjacent electrode layers 201.
The electrode layer 201 serves as an electrode plate constituting a capacitor structure.
In this embodiment, among the electrode layers 201, the electrode layer 201 at the bottommost layer covers the surfaces of the trenches 200 and the surface of the pillars 110, and the remaining electrode layers 201 are stacked sequentially on the electrode layer 201 at the bottommost layer, and the electrode layers 201 fill the trenches 200, that is, in the trenches 200, the electrode layers 201 are stacked in a direction perpendicular to the sidewalls of the trenches 200, to form a DTC structure.
In this embodiment, the material of the electrode layer 201 is a conductive material. As one example, the material of the electrode layer 201 includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
Dielectric layer 260 serves as an insulating layer in forming the capacitor structure for isolating adjacent electrode layers 201.
In this embodiment, the material of the dielectric layer 260 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The high-k dielectric material is selected, so that the capacitance value of the capacitor structure is improved, and the capacitance density is correspondingly improved.
Specifically, the dielectric layer 260 is a high-k dielectric layer formed by stacking, i.e., the dielectric layer 260 is a high-k composite dielectric layer. After the thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easily deteriorated, and therefore, the thickness of the dielectric layer 260 can meet the process requirement and has better formation quality. To this end, the high-k dielectric material includes one or more of HfO2、HfSiO、TiO2、HfZrO、HfSiON、HfTaO、HfTiO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3、BaSrTiO and SiN.
In this embodiment, the dielectric layer 260 is ZAZ layers. Wherein, ZAZ layers include a first ZrO 2 layer, an Al 2O3 layer and a second ZrO 2 layer formed in a stacked manner. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.
In this embodiment, the top view of the pillars 110 is polygonal, the sides of the adjacent pillars 110 are arranged oppositely, each trench 200 surrounds the pillar 110 in the plurality of trenches 200, the plurality of trenches 200 are communicated, so that the plurality of pillars 110 are closely arranged, the trenches 200 can be formed between the adjacent pillars 110 to provide space positions for the capacitor formed by the electrode layer 201, flexibility of arrangement of the capacitor structure is increased, and deep trench capacitor structures are formed between the closely arranged adjacent pillars 110, which is beneficial to saving occupied area and improving the integration level of the semiconductor structure.
In the step of forming the electrode layer 201 in this embodiment, the number of layers of the electrode layer 201 is n, and the surface of each electrode layer 201 in the n electrode layers 201 is exposed on the pillar 110 of each pillar group 111 in the adjacent n pillar groups 111.
In the adjacent n pillar groups 111, the pillar 110 of each pillar group 111 exposes the surface of each electrode layer 201 in the n electrode layers 201, and the exposed surface of the electrode layer 201 is used for contacting with the interconnection plug, so that the electric signal is loaded to the corresponding electrode layer 201 through the interconnection plug.
In this embodiment, the pillars 110 enclose the trench 200, and the surface of the corresponding electrode layer 201 is exposed on each pillar 110, that is, the electrical signal loading of each electrode layer 201 can be realized above the pillar 110, without additional area for electrical connection of the electrode layers 201, which is beneficial to saving the occupied area, and the pillars 110 are regularly arranged into a plurality of pillar groups 111, the pillars 110 of each pillar group 111 expose the same electrode layer 201, and the pillars in each pillar group 111 are arranged along the first direction, so that the electrode layer 201 on the pillar 110 of each pillar group 111 is easy to be electrically connected with the interconnection line extending along the first direction, and the connection manner is simple, which is beneficial to realizing the capacitor structure.
In the step of forming the electrode layer 201 in this embodiment, the surfaces of the 1 st to n th electrode layers 201 are sequentially exposed on the pillar groups 111 sequentially arranged along the second direction among the n pillar groups 111 adjacent to each other.
Among the n adjacent pillar groups 111, the pillar groups 111 sequentially arranged along the second direction sequentially expose the surfaces of the 1 st to n th electrode layers 201, so that the arrangement of the electrode layers 201 exposed on the pillar groups 111 has regularity, which is beneficial to the regular arrangement of the interconnection lines formed above the pillar groups 111 and the electrode layers 201, so that the semiconductor structure has a regular structure, and the structural design and formation are easy to realize.
Specifically, in this embodiment, fig. 11 shows an example in which the number of layers of the electrode layer 201 is 2, the first electrode layer 210 surface and the second electrode layer 220 surface in 2 layers of the electrode layer 201 are respectively exposed on the pillars 110 of each of the adjacent 2 pillar groups 111, and fig. 13 shows an example in which the number of layers of the electrode layer 201 is 4, the 1 st to 4 th electrode layer 201 surfaces are sequentially exposed on the pillar groups 111 sequentially arranged in the second direction, and the first electrode layer 210, the second electrode layer 220, the third electrode layer 230, and the fourth electrode layer 240 surfaces are sequentially exposed on the pillar groups 111 sequentially arranged in the second direction.
Specifically, in the present embodiment, the step of forming the multi-layered stacked electrode layers 201 includes forming n electrode material layers stacked in sequence, and etching back portions of the electrode material layers so that the surface of each of the n electrode layers 201 is exposed on the pillar 110 of each pillar group 111 of the adjacent n pillar groups 111.
After n electrode material layers stacked in sequence are formed, part of the electrode material layers are etched back, so that the formed electrode layer 201 is more accurate in appearance.
In this embodiment, in the step of forming the electrode layer 201 and the dielectric layer 260 stacked in multiple layers, an atomic layer deposition process is used to form each electrode layer 201 and each dielectric layer 260.
The electrode layer 201 and the dielectric layer 260 formed by adopting the atomic layer deposition process have good thickness uniformity and good step coverage (step coverage) capability, so that the electrode layer 201 and the dielectric layer 260 can well cover the bottom and the side wall of the trench 200 in a conformal manner, and the thickness uniformity of the electrode layer 201 and the dielectric layer 260 is good.
With continued reference to fig. 11-13, after forming the multi-layered stacked electrode layer 201 and the dielectric layer 260, the forming method further includes forming a plurality of interconnect plugs 300 on the exposed electrode layer 201 on the pillars 110 and electrically connected to the corresponding electrode layer 201.
Interconnect plugs 300 are used to load electrical signals to corresponding electrode layers 201.
In this embodiment, the plurality of interconnection plugs 300 are located on the exposed electrode layer 201 on the pillar 110, so that no additional etching region is required to etch the electrode layer 201 to form the interconnection plugs 300, which is beneficial to saving the occupied area of the semiconductor structure.
In this embodiment, the material of the interconnect plug 300 is tungsten. In other embodiments, the material of the interconnect plug may also be cobalt or ruthenium.
In this embodiment, a plurality of interconnect lines 400 are formed on top of the interconnect plugs 300, the interconnect lines 400 extend along the first direction and are located on top of the interconnect plugs 300 on the corresponding pillar groups 111, and the interconnect lines 400 located on top of the interconnect plugs 300 of the same electrode layer 201 are connected in parallel.
The interconnect line 400 is used to electrically connect with the interconnect plug 300 so as to load an electrical signal to the corresponding electrode layer 201 through the interconnect plug 300.
In this embodiment, the interconnection lines 400 extend along the first direction and are located at the top of the interconnection plugs 300 on the corresponding pillar groups 111, and the pillars 110 of the same pillar group 111 expose the same electrode layer 201, so that the same interconnection lines 400 load the same electrode layer 201 with an electrical signal, and the interconnection lines 400 located at the top of the interconnection plugs 300 of the same electrode layer 201 are connected in parallel, so that the same electrical signal is loaded on the same electrode layer 201 in the multi-layer electrode layer 201, thereby realizing the basic function of the deep trench capacitor structure.
In this embodiment, the material of the interconnection line 400 is tungsten. In other embodiments, the material of the interconnect lines may also be cobalt or ruthenium.
In the present embodiment, in the step of forming the plurality of interconnection lines 400, the interconnection lines 400 on top of the interconnection plugs 300 of the electrode layers 201 of the separation layer are connected in parallel.
The interconnection lines 400 at the top of the interconnection plugs 300 of the electrode layers 201 at the spaced apart layers are connected in parallel, so that the same electric signal is loaded to the electrode layers 201 adjacent to each other at intervals, and thus, the electric connection lines of the multi-layer electrode layers 201 are simplified while the potential difference between the adjacent electrode layers 201 can be realized, the electric connection structure of the multi-layer electrode layers 201 is simple and easy to realize, and the formation cost of the semiconductor structure is saved.
Specifically, referring to fig. 11 and 13 in combination, in the present embodiment, by forming the metal line 500 extending in the second direction such that the metal line 500 is electrically connected to the interconnect line 400 on top of the interconnect plug 300 of the electrode layer 201 of the inter-layer, the interconnect line 400 on top of the interconnect plug 300 of the electrode layer 201 of the inter-layer is implemented in parallel.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
A substrate;
The upright posts are convexly erected on the substrate, the top view appearance of each upright post is polygonal, and the edges of the adjacent upright posts are oppositely arranged;
a plurality of grooves, each of which surrounds the column, the grooves being in communication;
The electrode layers are stacked in multiple layers, wherein the electrode layer at the bottommost layer covers each surface of the groove and the surface of the upright post, the rest electrode layers are stacked on the electrode layer at the bottommost layer in sequence, and the grooves are filled with the multiple layers of electrode layers;
And the dielectric layer is positioned between the adjacent electrode layers.
2. The semiconductor structure of claim 1, wherein a plurality of the pillars extending in a first direction form a pillar group, the plurality of pillars include a plurality of pillar groups arranged side by side in a second direction, the number of the electrode layers is n, surfaces of each of the n electrode layers are exposed on pillars of each pillar group among the adjacent n pillar groups, and the first direction is perpendicular to the second direction.
3. The semiconductor structure of claim 2, wherein the surfaces of the 1 st to n th electrode layers are sequentially exposed on groups of pillars sequentially arranged along the second direction among adjacent n groups of pillars.
4. The semiconductor structure of claim 2, further comprising a plurality of interconnect plugs on the exposed electrode layers on the pillars and electrically connected to corresponding electrode layers;
And the interconnection lines extend along the first direction, are positioned at the tops of the interconnection plugs on the corresponding column groups, and are connected in parallel.
5. The semiconductor structure of claim 4, wherein, of the plurality of interconnect lines, interconnect lines on top of interconnect plugs of electrode layers of the spacer layer are connected in parallel.
6. The semiconductor structure of claim 1, wherein the top-down topographical polygon of the pillars is a hexagon.
7. The semiconductor structure of claim 6, further comprising a via interconnect structure;
And the upright posts form hexagonal honeycomb upright post units, and the upright post units enclose an annular structure surrounding the through hole interconnection structure.
8. The semiconductor structure of claim 1, wherein the dielectric layer comprises one or more of HfO2、HfSiO、TiO2、HfZrO、HfSiON、HfTaO、HfTiO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3、BaSrTiO and SiN;
The material of the electrode layer includes one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
9. A method of forming a semiconductor structure, comprising:
providing a substrate and a material layer on the substrate;
Forming a plurality of grooves penetrating through the material layer, forming a plurality of stand columns protruding out of the substrate by the residual material layer, wherein the stand columns are polygonal in overlook appearance, the sides of the adjacent stand columns are oppositely arranged, each groove surrounds the stand column, and the plurality of grooves are communicated;
And forming a plurality of stacked electrode layers and dielectric layers, wherein in the plurality of electrode layers, the electrode layer at the bottommost layer covers each surface of the groove and the surface of the upright post, the rest electrode layers are sequentially stacked on the electrode layer at the bottommost layer, the grooves are filled with the plurality of electrode layers, and the dielectric layers are positioned between the adjacent electrode layers.
10. The method of forming a semiconductor structure of claim 9, wherein in the step of forming the pillars, a plurality of the pillars arranged to extend in a first direction form a pillar group, the plurality of the pillars including a plurality of pillar groups arranged in parallel in a second direction, the first direction being perpendicular to the second direction;
In the step of forming the electrode layers, the number of the electrode layers is n, and the surface of each electrode layer in the n electrode layers is exposed on the upright post of each upright post group in the adjacent n upright post groups.
11. The method of forming a semiconductor structure according to claim 10, wherein in the step of forming the electrode layer, surfaces of the 1 st to n th electrode layers are sequentially exposed on the pillar groups sequentially arranged in the second direction among the adjacent n pillar groups.
12. The method of forming a semiconductor structure of claim 10, wherein the step of forming a multi-layered stack of electrode layers comprises forming n electrode material layers stacked in sequence;
and etching back part of the electrode material layers so that the surface of each electrode layer in the n electrode layers is exposed on the upright post of each upright post group in the adjacent n upright post groups.
13. The method of forming a semiconductor structure as claimed in claim 10, wherein after forming the electrode layers and the dielectric layers of the multi-layer stack, the method further comprises forming a plurality of interconnect plugs on the electrode layers exposed on the pillars and electrically connected to the corresponding electrode layers;
And forming a plurality of interconnection lines on the top of the interconnection plugs, wherein the interconnection lines extend along the first direction and are positioned on the top of the interconnection plugs on the corresponding column groups, and the interconnection lines on the top of the interconnection plugs of the same electrode layer are connected in parallel.
14. The method of forming a semiconductor structure according to claim 13, wherein in the step of forming a plurality of the interconnect lines, the interconnect lines on top of the interconnect plugs of the electrode layers of the inter-phase layers are connected in parallel.
15. The method of forming a semiconductor structure of claim 9, wherein in the step of forming a plurality of said pillars, the top-down topographical polygon of said pillars is a hexagon.
16. The method of forming a semiconductor structure of claim 15, wherein in the step of providing the substrate, a via interconnect structure is formed through the material layer;
in the step of forming a plurality of upright posts, the upright posts form hexagonal honeycomb upright post units, and the upright post units enclose an annular structure surrounding the through hole interconnection structure.
17. The method of claim 9, wherein in the step of forming the electrode layers and the dielectric layers of the multi-layer stack, each electrode layer and each dielectric layer are formed by an atomic layer deposition process.
18. The method of forming a semiconductor structure of claim 9, wherein in the step of forming the electrode layer and the dielectric layer of the multi-layer stack, the dielectric layer comprises one or more of HfO2、HfSiO、TiO2、HfZrO、HfSiON、HfTaO、HfTiO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3、BaSrTiO and SiN, and the material of the electrode layer comprises one or more of W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.
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