CN119447119A

CN119447119A - Semiconductor structure and method for forming the same

Info

Publication number: CN119447119A
Application number: CN202310946852.9A
Authority: CN
Inventors: 游洋
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2023-07-28
Filing date: 2023-07-28
Publication date: 2025-02-14

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate; a groove located in the substrate; a plurality of columns protruding from the bottom of the groove, and the plurality of columns being separated from each other; a plurality of stacked electrode layers, the bottom electrode layer covering each surface of the groove and each surface of the column, and the remaining electrode layers being stacked in sequence on the bottom electrode layer, wherein the portion of the top electrode layer located on the side wall of the column serves as a side wall electrode; a dielectric layer located between adjacent electrode layers; and a gap located between any adjacent side wall electrodes. The present invention is conducive to the stability of the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Deep trench capacitors (DEEP TRENCH Capacitor, DTC) are widely used for antenna matching, radio frequency filtering and IC decoupling, especially in applications with high and volume limitations, yet have very high stability at high bias voltages, very low leakage currents, and play a vital role in some industrial fields.

Silicon-based capacitors are comprehensively replacing the ceramic capacitors in the markets of smart phones AP and PMIC terminals by their irreplaceable advantages of miniaturization, high stability, low ESR/ESL, etc. The high-density DTC increases the effective area of the capacitor through the three-dimensional structural design, thereby improving the capacitor density.

A common design at present is a parallel or vertical planar structure of vertical slots, the area of a capacitor cell (unit cell) is changed by changing the length of the vertical slots, and then structures with different requirements of customers are built by parallel connection of the unit cells. Such structural design interconnect plugs (CTs) are typically used to extract the CTs at the periphery of the cell by etching the plates to expose the underlying plates.

As the number of DTCs increases, the number of plates increases, and it becomes difficult to design a multi-layer plate extraction CT.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to the stable performance of the semiconductor structure.

In order to solve the problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a groove, a plurality of stand columns, a plurality of electrode layers, a rest of electrode layers, a dielectric layer and a gap, wherein the groove is arranged in the substrate, the stand columns are convexly arranged at the bottom of the groove, the stand columns are mutually separated, the electrode layers stacked in multiple layers cover all surfaces of the groove and all surfaces of the stand columns, the rest of electrode layers are sequentially stacked on the electrode layers at the bottommost layer, the part of the electrode layer at the topmost layer on the side wall of the stand columns is used as a side wall electrode, the dielectric layer is arranged between the adjacent electrode layers, and the gap is arranged between any adjacent side wall electrodes.

Optionally, the bottom of the upright is connected to the base to form an integral structure.

Optionally, the top surface of the pillar is flush with the top of the groove.

Alternatively, the shape of the post comprises a cylinder.

Optionally, a plurality of columns extending and arranged along the first direction form column groups, the number of the column groups is a plurality of columns and the column groups are arranged in parallel along the second direction, in the adjacent column groups, the columns are distributed in a staggered manner along the second direction, the first direction is perpendicular to the second direction, and sidewall electrodes on sidewalls of the three adjacent columns which are arranged in a triangle form gaps.

Optionally, the total thickness of the electrode layer and the dielectric layer of the multi-layer stack satisfies the formula Wherein T represents the total thickness of the electrode layers and the dielectric layers stacked in multiple layers, L represents the distance between circle centers of adjacent upright posts arranged in a triangle shape, and r represents the radius of each upright post.

Optionally, the semiconductor structure further includes a sealing layer on top of the gap and sealing the top of the gap.

Optionally, the material of the sealing layer comprises silicon oxide.

Optionally, the substrate comprises a device region and a lead region adjacent to the device region, the groove is positioned in the device region, the electrode layers are also positioned on the top of the substrate of the lead region, and in the lead region, any electrode layer exposes an adjacent other electrode layer positioned below the electrode layer.

Alternatively, the lead regions are located on both sides of the device region, and the multi-layered electrode layer includes alternately stacked first electrode layers and second electrode layers, the first electrode layer exposing a surface of the second electrode layer in any one of the lead regions and the second electrode layer exposing a surface of the first electrode layer in the other of the lead regions.

Optionally, the semiconductor structure further comprises a plurality of first interconnection plugs, wherein the first interconnection plugs are located in the lead area, are located on each exposed electrode layer and are electrically connected with the corresponding electrode layer, the first interconnection plugs on each electrode layer are distributed in a plurality along the extending direction of the lead area, the extending direction is perpendicular to the direction of the lead area pointing to the device area, and the first interconnection lines are located on the first interconnection plugs on the same electrode layer and are electrically connected with the corresponding first interconnection plugs.

Optionally, the semiconductor structure further comprises electrode openings respectively positioned in the rest electrode layers except the bottommost electrode layer and penetrating through the electrode layers, wherein the electrode openings of the electrode layers are positioned at the tops of different upright posts.

Optionally, a plurality of columns extending and arranged along the first direction form column groups, the number of the column groups is a plurality of columns and the column groups are arranged in parallel along the second direction, the number of the electrode layers is n, the electrode openings of the same electrode layer are positioned at the tops of the columns of the same column group and correspond to the columns one by one, the electrode openings of each electrode layer are sequentially distributed at the tops of the columns of different column groups along the second direction according to preset periods, and each preset period is provided with n adjacent column groups, wherein the first direction is perpendicular to the second direction.

Optionally, the semiconductor structure further comprises a plurality of second interconnection plugs, a plurality of second interconnection lines and a plurality of second interconnection lines, wherein the second interconnection plugs are respectively positioned on the electrode layers exposed at the bottoms of the electrode openings and are electrically connected with the corresponding electrode layers, the second interconnection lines extend along the first direction and are positioned at the tops of the second interconnection plugs on the corresponding column groups, and the second interconnection lines positioned at the tops of the second interconnection plugs of the electrode layers of the same layer are connected in parallel.

Optionally, among the plurality of second interconnect lines, the second interconnect lines on top of the second interconnect plugs of the electrode layers of the odd-numbered layers are connected in parallel, and the second interconnect lines on top of the second interconnect plugs of the electrode layers of the even-numbered layers are connected in parallel.

Optionally, the semiconductor structure further comprises a through hole interconnection structure penetrating through the substrate, wherein the grooves encircle the through hole interconnection structure and comprise a plurality of sub-grooves which are communicated in sequence along the circumferential direction, and in each sub-groove, a plurality of upright posts form hexagonal upright post units.

Optionally, the material of the electrode layer comprises one or more of Si, W, cu, co, tiN, ti, ta, taN, ru, ruN and Al, and the material of the dielectric layer comprises one or more of HfO₂、HfSiO、TiO₂、HfZrO、HfSiON、HfTaO、HfTiO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃、BaSrTiO and SiN.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, forming a groove in the substrate, forming a plurality of stand columns protruding from the bottom of the groove, mutually separating the stand columns, forming a plurality of stacked electrode layers and dielectric layers, wherein the electrode layers at the bottommost layer cover all surfaces of the groove and all surfaces of the stand columns in the plurality of electrode layers, and the rest electrode layers are sequentially stacked on the electrode layers at the bottommost layer, wherein the part of the electrode layer at the side wall of the stand column at the topmost layer is used as a side wall electrode, and a gap is reserved between any two adjacent side wall electrodes.

Optionally, the step of forming a recess in the substrate and forming a stud protruding from the bottom of the recess includes patterning the substrate, forming a recess in the substrate, and forming a plurality of studs protruding from the bottom of the recess.

Optionally, in the step of forming the pillar protruding from the bottom of the groove, the pillar may have a cylindrical shape.

Optionally, in the step of forming the stand column, a plurality of stand columns extending and arranged along the first direction form a stand column group, the number of the stand column groups is a plurality of stand columns and arranged in parallel along the second direction, in the adjacent stand column groups, the plurality of stand columns are distributed in a staggered manner along the second direction, the first direction is perpendicular to the second direction, and in the step of forming the electrode layer, side wall electrodes on the side walls of the three adjacent stand columns which are arranged in a triangle form enclose gaps.

Optionally, in the step of forming the electrode layer, the total thickness of the electrode layer and the dielectric layer of the multi-layer stack satisfies the formulaWherein T represents the total thickness of the electrode layers and the dielectric layers stacked in multiple layers, L represents the distance between circle centers of adjacent upright posts arranged in a triangle shape, and r represents the radius of each upright post.

Optionally, after forming the electrode layer and the dielectric layer, the forming method further comprises forming a sealing layer sealing the top of the gap.

Optionally, the step of providing a substrate comprises a device region and a lead region adjacent to the device region, the step of forming a groove, wherein the groove is positioned in the device region, the step of forming an electrode layer, wherein the electrode layer is also positioned on the top of the substrate of the lead region, and any electrode layer exposes another adjacent electrode layer positioned below the electrode layer in the lead region.

Optionally, in the step of providing a substrate, the lead regions are located at both sides of the device region, and in the step of forming the electrode layers, the multi-layered electrode layer includes first electrode layers and second electrode layers alternately stacked, the first electrode layer exposing a surface of the second electrode layer in any one of the lead regions, and the second electrode layer exposing a surface of the first electrode layer in another of the lead regions.

Optionally, after forming the electrode layers and the dielectric layers of the multi-layer stack, the forming method further includes forming a plurality of first interconnection plugs electrically connected to the corresponding electrode layers on each of the exposed electrode layers in the lead region, the plurality of first interconnection plugs being arranged along an extending direction of the lead region, the extending direction being perpendicular to a direction of the lead region toward the device region, and forming a plurality of first interconnection lines, each of the first interconnection lines being located on the corresponding first interconnection plugs on the same electrode layer and being electrically connected to the corresponding plurality of first interconnection plugs.

Optionally, in the step of forming the electrode layer, electrode openings are formed in the electrode layers of the rest layers except for the electrode layer at the bottommost layer, and the electrode openings penetrate through the electrode layer where the electrode openings are located, wherein the electrode openings of the electrode layers are located at the tops of different upright posts.

Optionally, in the step of forming the stand columns, a plurality of stand columns extending and arranged along the first direction form stand column groups, the number of the stand column groups is a plurality of the stand column groups and the stand column groups are arranged in parallel along the second direction, in the step of forming the electrode layers, the number of the electrode layers is n, the electrode openings of the same electrode layer are positioned at the top of the stand column of the same stand column group and correspond to the stand columns one by one, in the step of forming the electrode layers, the electrode openings of each electrode layer are sequentially distributed at the top of the stand column of different stand column groups along the second direction and according to preset periods, and each preset period is provided with n adjacent stand column groups, wherein the first direction is perpendicular to the second direction.

Optionally, after forming the electrode layers and the dielectric layers of the multi-layer stack, the forming method further comprises forming second interconnection plugs on the electrode layers exposed at the bottoms of the electrode openings, wherein the second interconnection plugs are electrically connected with the corresponding electrode layers, forming a plurality of second interconnection lines on the tops of the second interconnection plugs, wherein the second interconnection lines extend along the first direction and are positioned on the tops of the second interconnection plugs on the corresponding upright post groups, and the interconnection lines on the tops of the second interconnection plugs on the electrode layers of the same layer are connected in parallel.

Optionally, in the step of forming the plurality of second interconnection lines, the second interconnection lines on top of the second interconnection plugs of the electrode layers of the odd-numbered layers are connected in parallel, and the second interconnection lines on top of the second interconnection plugs of the electrode layers of the even-numbered layers are connected in parallel.

Optionally, in the step of providing the substrate, a through hole interconnection structure penetrating through the substrate is formed in the substrate, in the step of forming the groove, the groove surrounds the through hole interconnection structure and comprises a plurality of sub-grooves which are sequentially communicated in the circumferential direction, and in the step of forming the stand column, in each sub-groove, a plurality of stand columns form a hexagonal stand column unit.

Optionally, in the step of forming the electrode layers and the dielectric layers stacked in multiple layers, a furnace tube process is used to form each electrode layer and each dielectric layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

In the semiconductor structure provided by the embodiment of the invention, a plurality of stand columns are raised at the bottom of the groove, the stand columns are mutually separated, electrode layers are stacked in a plurality of layers, the electrode layer at the bottommost layer covers each surface of the groove and each surface of the stand column, and other electrode layers are sequentially stacked on the electrode layer at the bottommost layer, wherein the part of the electrode layer at the topmost layer on the side wall of the stand column is used as a side wall electrode, and a gap is positioned between any two adjacent side wall electrodes; in the embodiment of the invention, the mutually separated upright posts are adopted, so that each side face of each upright post is exposed in the groove, the stress direction generated by the multi-layer stacked electrode layers in the groove is in the direction vertical to each side face of the upright post, namely the stress distribution is more dispersed, the problem of stress concentration is solved, the influence of stress on a semiconductor structure is reduced, gaps are arranged between any adjacent side wall electrodes, the stress can be released in the gaps, in the process of a subsequent thermal process, a certain space is provided for expansion of the film layer, the performance stability of a semiconductor structure is facilitated, meanwhile, the space of the rest part in the groove is used for accommodating the electrode layers and the dielectric layers to form a capacitor, compared with the space for forming the capacitor by adopting the separated vertical grooves, the structural design of the scheme is more flexible and compact, and the integration degree of the semiconductor structure is improved.

In the method for forming the semiconductor structure, grooves are formed in a substrate, the stand columns protruding from the bottoms of the grooves are formed, the stand columns are separated from each other, a plurality of stacked electrode layers and dielectric layers are formed, the bottommost electrode layer among the plurality of electrode layers covers all surfaces of the grooves and all surfaces of the stand columns, other electrode layers are sequentially stacked on the bottommost electrode layer, the portion of the topmost electrode layer on the side wall of the stand columns serves as a side wall electrode, gaps are reserved between any adjacent side wall electrodes, in the embodiment of the invention, all sides of the stand columns are exposed in the grooves by adopting the stand columns which are separated from each other, so that stress directions generated by the electrode layers stacked in the plurality of layers in the grooves are in directions perpendicular to all sides of the stand columns, namely stress distribution is more dispersed, the problem of stress concentration is solved, the influence on the semiconductor structure is reduced, gaps are reserved among any adjacent side wall electrodes, the gaps can be released in the gaps in the process of subsequent thermal manufacturing, a certain expansion of the film layers can be provided, the gaps can be used for expanding the side wall electrodes, the space of the semiconductor structure is more compact, the capacitor structure is formed by adopting the conventional structure, and the capacitor structure is more stable, and the capacitor structure is formed by adopting the capacitor structure.

Drawings

FIGS. 1-2 are schematic diagrams of a semiconductor structure;

FIGS. 3-6 are schematic diagrams illustrating an embodiment of a semiconductor structure according to the present invention;

FIG. 7 is a schematic diagram of another embodiment of a semiconductor structure of the present invention;

Fig. 8 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;

Fig. 15 is a schematic view of a semiconductor structure according to another embodiment of the present invention.

Detailed Description

The performance robustness of current semiconductor structures is to be improved. The reasons why the performance robustness is to be improved are now analyzed in connection with a semiconductor structure.

Fig. 1 to 2 are schematic structural views of a semiconductor structure.

Referring to fig. 1 and 2 in combination, fig. 2 is a cross-sectional view of one of the grooves in fig. 1, the semiconductor structure includes a substrate 10, a plurality of discrete square grooves 20 in the substrate 10, a plurality of stacked electrode layers 11, a lowermost electrode layer 11 covering respective surfaces of the grooves 20, remaining electrode layers 11 being stacked in sequence on the lowermost electrode layer 11, and a dielectric layer between adjacent electrode layers 11.

In the step of forming the plurality of stacked electrode layers 11 and the dielectric layers between the adjacent electrode layers 11 in the square groove 20, the plurality of stacked film layers in the groove 20 are liable to generate larger stress due to factors such as different expansion coefficients of different film layers in the process, the stress direction is perpendicular to the direction of the side wall of the groove 20, as shown by the dotted arrow in fig. 2 including tensile stress and compressive stress, the side wall of the square groove 20 is liable to receive larger stress, and moreover, as shown in fig. 1, the arrangement of the grooves 20 in the substrate 10 is parallel in the X direction and parallel in the Y direction, and the stress direction is mainly in the X direction and the Y direction due to the arrangement rule of the grooves 20, thereby easily causing larger warpage of the substrate 10, affecting the subsequent process of the semiconductor structure, and causing unstable performance of the semiconductor structure.

In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, which comprises a substrate, a groove, a plurality of stand columns, a plurality of electrode layers, a rest of electrode layers, a dielectric layer and a gap, wherein the groove is arranged in the substrate, the stand columns are convexly arranged at the bottom of the groove, the stand columns are mutually separated, the electrode layers stacked in multiple layers cover all surfaces of the groove and all surfaces of the stand columns, the rest of electrode layers are sequentially stacked on the electrode layers at the bottommost layer, the part of the electrode layer at the topmost layer on the side wall of the stand columns is used as a side wall electrode, the dielectric layer is arranged between the adjacent electrode layers, and the gap is arranged between any adjacent side wall electrodes.

In the embodiment of the invention, the mutually separated upright posts are adopted, so that each side face of each upright post is exposed in the groove, the stress direction generated by the multi-layer stacked electrode layers in the groove is in the direction vertical to each side face of the upright post, namely the stress distribution is more dispersed, the problem of stress concentration is solved, the influence of stress on a semiconductor structure is reduced, gaps are arranged between any adjacent side wall electrodes, the stress can be released in the gaps, in the process of a subsequent thermal process, a certain space is provided for expansion of the film layer, the performance stability of a semiconductor structure is facilitated, meanwhile, the space of the rest part in the groove is used for accommodating the electrode layers and the dielectric layers to form a capacitor, compared with the space for forming the capacitor by adopting the separated vertical grooves, the structural design of the scheme is more flexible and compact, and the integration degree of the semiconductor structure is improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 3-6, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown.

Referring to fig. 3 to 6 in combination, the semiconductor structure includes a substrate 100, a recess 200 in the substrate 100, a plurality of pillars 110 protruding from the bottom of the recess 200 and separated from each other, a plurality of stacked electrode layers 201, a lowermost electrode layer 201 covering the respective surfaces of the recess 200 and the respective surfaces of the pillars 110, and remaining electrode layers 210 stacked in sequence on the lowermost electrode layer 210, wherein a portion of the uppermost electrode layer 210 located on the sidewall of the pillar 110 serves as a sidewall electrode 101, a dielectric layer (not shown) located between adjacent electrode layers 201, and a gap 200s located between any adjacent sidewall electrodes 202.

The substrate 100 is used to provide a process platform for forming semiconductor structures.

In this embodiment, the material of the substrate 100 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, the substrate 100 includes a device region 100A, and a lead region 100B adjacent to the device region 100A.

The device region 100A is used to form a capacitor structure, and the lead region 100B is used to electrically lead out the electrode layer 201.

Specifically, in the present embodiment, the lead regions 100B are located at both sides of the device region 100A, so that the multi-layered electrode layer 201 can be electrically connected from the lead regions 100B at both sides by distribution in the lead regions 100B at both sides, respectively, so that the electrical connection line of the electrode layer 201 is simplified and easy to realize.

In this embodiment, the semiconductor structure further includes a via interconnect structure (not shown) extending through the substrate 100.

The Via interconnection structure is used for realizing the longitudinal electrical connection of the wafer and the longitudinal stacking of the wafer, and in this embodiment, the Via interconnection structure is a Through-Silicon-Via (TSV) structure.

In this embodiment, the recess 200 is used to provide a spatial location for the formation of the electrode layer 210 and the dielectric layer.

Accordingly, in this embodiment, the recess 200 is located in the device region 100A.

In this embodiment, the recess 200 surrounds the via interconnection structure and includes a plurality of sub-recesses (not shown) sequentially communicating in the circumferential direction, and in each sub-recess, a plurality of pillars 110 constitute a hexagonal pillar unit.

Compared with a square structure with a plurality of square grooves forming a surrounding through hole interconnection structure, in this embodiment, the plurality of columns 110 form hexagonal honeycomb column units, the plurality of column units enclose a ring structure surrounding the through hole interconnection structure, the honeycomb column units are more compactly arranged, the ring structure formed by the plurality of column units saves occupied area, and the integration level of the semiconductor structure is improved.

In this embodiment, the pillars 110 are used to form the electrode layer 210 on the sidewalls thereof, and support the formation of the sidewall electrode 202.

In this embodiment, the pillar 110 is obtained by patterning the substrate 100, so that the bottom of the pillar 110 is connected to the substrate 100 to form an integral structure, so that the pillar is simpler to obtain.

Moreover, in the present embodiment, the substrate 100 is patterned to obtain the recess 200 and the pillar 110 protruding from the bottom of the recess 200, so that the top surface of the pillar 110 is flush with the top of the recess 200, which is correspondingly beneficial to the formation of the electrode layer 210.

In this embodiment, the shape of the post 110 includes a cylindrical shape.

Referring to fig. 4, the pillar 110 is cylindrical, and the sidewall electrode 202 located on the sidewall of the pillar 110 also encloses a cylinder, so that the tangential surfaces of the sidewall electrodes 202 on the sidewalls of adjacent pillars 110 are in contact, and a corresponding plurality of contact surfaces can enclose a gap 200s.

Referring to fig. 4 and 5 in combination, fig. 5 is a cross-sectional view along AA direction of fig. 4, and the pillar 110 is cylindrical, which is advantageous in that a stress generated in the groove 200 by the multi-layered stacked electrode layer 201 is directed along a diameter direction of the pillar 110 (as shown by dotted arrows in fig. 5), so that stress distribution is more dispersed, thereby improving a problem of stress concentration and reducing an influence of stress on a semiconductor structure.

In this embodiment, a plurality of columns 110 extending in a first direction (as shown in an X direction in fig. 3) form a column group 111, the columns 111 are plural and are arranged in parallel in a second direction (as shown in a Y direction in fig. 3), and the columns 110 are staggered in the second direction in the adjacent column group 111, and the first direction is perpendicular to the second direction.

The plurality of columns 110 extending and arranged along the first direction form the column group 111, and the number of the column groups 111 is a plurality of columns and the columns are arranged in parallel along the second direction, that is, the arrangement regularity of the columns 110 is better, so that the remaining spaces except for the columns 110 in the grooves 200 are more regular, which is favorable for forming the electrode layer 210, so that the electrical property of the capacitor structure formed by the electrode layer 210 is more stable.

In the adjacent column groups 111, the columns 110 are staggered in the second direction, that is, the columns 110 in one column group 111 are located at intervals of the adjacent columns 110 in the other column group 111 in the second direction in the adjacent column groups 111, so that the columns 110 and the adjacent columns 110 at the corresponding intervals can enclose a gap 200s.

The multi-layered electrode layer 201 is used to form a capacitor structure, and in particular, the multi-layered electrode layer 201 stacked in the recess 200 is used to form a Deep Trench Capacitor (DTC) structure.

In this embodiment, the material of the electrode layer 201 includes one or more of Si, W, cu, co, tiN, ti, ta, taN, ru, ruN and Al.

As an example, in this embodiment, the material of the electrode layer 201 is polysilicon, and the use of polysilicon to form the electrode layer 201 facilitates the operation of the patterning process of the electrode layer 201.

The dielectric layer serves as an insulating layer in the formed capacitor structure for isolating the adjacent electrode layers 201.

In this embodiment, the material of the dielectric layer is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The high-k dielectric material is selected, so that the capacitance value of the capacitor structure is improved, and the capacitance density is correspondingly improved.

Specifically, the dielectric layer is a high-k dielectric layer formed by stacking, i.e., the dielectric layer is a high-k composite dielectric layer. After the formation thickness of the high-k dielectric layer reaches a certain value, the formation quality of the high-k dielectric layer is easy to deteriorate, and therefore, the high-k composite dielectric layer can enable the thickness of the dielectric layer to meet the process requirement and has good formation quality. To this end, the high-k dielectric material includes one or more of HfO₂、HfSiO、TiO₂、HfZrO、HfSiON、HfTaO、HfTiO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃、BaSrTiO and SiN.

In this embodiment, the dielectric layer is ZAZ layers. Wherein, ZAZ layers include a first ZrO ₂ layer, an Al ₂O₃ layer and a second ZrO ₂ layer formed in a stacked manner. In other embodiments, the material of the dielectric layer may be one or more of silicon oxide, silicon oxynitride, and silicon nitride, depending on the process requirements.

In this embodiment, the gap 200s surrounded by the sidewall electrode 202 is used to release the stress generated by the stacked layers in the recess 200, and also is used to provide space for expansion of the layers in the subsequent thermal process.

Referring to fig. 3,4 and 6 in combination, fig. 4 is a partial enlarged view of the triangular region 100t in fig. 3, and fig. 6 is a sectional view of fig. 4 along the BB direction, and sidewall electrodes 202 on sidewalls of adjacent three pillars 110 arranged in a triangle form enclose a gap 200s.

In this embodiment, in the adjacent column groups 111, the plurality of columns 110 are staggered in the second direction, and the sidewall electrodes 202 of the sidewalls of the three adjacent columns 110 arranged in a triangle form are in contact with each other, so that a gap 200s is defined at the center of the triangular region 100t correspondingly, and meanwhile, the sidewall electrodes 202 of the sidewalls of the three adjacent columns 110 arranged in this way can define a gap 200s, which is favorable for obtaining more gaps 200s, and is more favorable for relieving the stress generated by the stacked film layers in the groove 200, and more space is provided for expansion of the film layers in the subsequent thermal process.

In this embodiment, the total thickness of the electrode layer 201 and the dielectric layer of the multi-layer stack satisfies the formula Where T represents the total thickness of the electrode layers 201 and the dielectric layers of the multi-layer stack, L represents the distance between the centers of circles of adjacent pillars 110 arranged in a triangle, and r represents the radius of the pillar 110.

When the minimum distance between the sidewalls of the adjacent columns 110 arranged in a triangle is L-2r and the total thickness of the electrode layer 201 and the dielectric layer at the sidewalls of the columns 110 is (L-2 r)/2, the electrode layer 201 at the sidewall of the adjacent columns 110 is just contacted with the film layer formed by the dielectric layer, the sidewall electrodes 202 on the sidewalls of the adjacent three columns 110 are just surrounded into gaps 200s and just surrounded into gaps 200s, and the distance from the center of each column 110 to the center point of the triangle formed by the centers of the three columns 110 isThat is, when the thickness of the electrode layer 201 and the dielectric layer on the sidewall of the pillar 110 isIn this embodiment, the electrode layers 201 on the side walls of the three pillars 110 are just in contact with the dielectric layer at the center point of the triangle, and the gap 200s is eliminated, so that the total thickness of the electrode layers 201 and the dielectric layers of the multi-layer stack satisfies the formula

Referring to fig. 3, the electrode layers 201 are also located on top of the substrate 100 of the lead region 100B, and in the lead region 100B, any one electrode layer 201 exposes another adjacent electrode layer 201 thereunder.

The exposed electrode layers 201 are used for electrical connection with the outside, thereby loading the respective electrode layers 201 with corresponding electrical signals.

Specifically, in the present embodiment, the multi-layered electrode layer 201 includes the first electrode layer 210 and the second electrode layer 220 stacked alternately, the first electrode layer 210 exposing the surface of the second electrode layer 220 in any one of the lead regions 100B, and the second electrode layer 220 exposing the surface of the first electrode layer 210 in the other lead region 100B.

In any lead area 100B, the first electrode layer 210 exposes the surface of the second electrode layer 220, the corresponding second electrode layer 220 is electrically connected from the lead area 100B, in the other lead area 100B, the second electrode layer 220 exposes the surface of the first electrode layer 210, the corresponding first electrode layer 210 is electrically connected from the lead area 100B, so that the electrical connection lines of the first electrode layer 210 and the second electrode layer 220 are regularly arranged, and the electrical connection between the first electrode layer 210 and the second electrode layer 220 is easy to be realized.

In this embodiment, the semiconductor structure further includes a sealing layer 700 on top of the gap 200s and sealing the top of the gap 200 s.

The sealing layer 700 is used to seal the gap 200s, so that the film layer in the subsequent process will not fill in the gap 200s, and provides a relatively flat process platform for the subsequent process.

In this embodiment, the material of the sealing layer 700 includes silicon oxide.

The silicon oxide can seal the gap 200s well and does not fill the gap 200s as much as possible.

In this embodiment, the semiconductor structure further includes a first interconnection plug 300 disposed in the lead region 100B and disposed on each of the exposed electrode layers 201 and electrically connected to the corresponding electrode layer, wherein the number of the first interconnection plugs 300 on each of the electrode layers 201 is plural and arranged along an extending direction of the lead region 100B, and the extending direction is perpendicular to a direction in which the lead region 100B points to the device region 100A.

The first interconnection plugs 300 are used for realizing electrical connection between the electrode layers 201 and the outside, so as to load electrical signals to the electrode layers 201, and the number of the first interconnection plugs 300 on each electrode layer 201 is plural and distributed along the extending direction of the lead area 100B, which is beneficial to making the loading of electrical signals to each electrode layer 201 more uniform.

In this embodiment, the material of the first interconnect plug 300 includes Cu, co, or W.

In this embodiment, the semiconductor structure further includes a plurality of first interconnect lines 400, where each first interconnect line 400 is correspondingly located on the first interconnect plugs 300 on the same electrode layer 201 and is electrically connected to the corresponding plurality of first interconnect plugs 300.

The first interconnect lines 400 serve to electrically connect the corresponding plurality of first interconnect plugs 300, thereby loading the corresponding electrode layers 201 with electrical signals.

In this embodiment, the material of the first interconnect line 400 includes Cu, co, or W.

Fig. 7 is a schematic diagram of another embodiment of a semiconductor structure of the present invention.

The present embodiment is the same as the previous embodiment, and will not be described again here. The present embodiment is different from the foregoing embodiments in that the circuit structure for loading the electrode layer with an electrical signal is different.

Referring to fig. 7, the semiconductor structure further includes electrode openings 204 respectively located in the remaining electrode layers 203 except the electrode layer 203 at the bottom layer and penetrating the electrode layer 203 where the electrode openings 204 of the electrode layers 203 are located at the top of different pillars 112.

The electrode openings 204 serve to expose the corresponding electrode layers 203, so that electrical connection of the exposed electrode layers 203 is achieved through the electrode openings 204.

In this embodiment, the electrode openings 204 of each electrode layer 203 are located at the top of different pillars 112, i.e. the loading of the electrical signals of each electrode layer 203 can be realized above the pillars 112, without requiring additional area for electrical connection of the electrode layers 203, which is beneficial to saving the occupied area.

In this embodiment, the number of layers of the electrode layer 203 is n, and the electrode openings 204 of the same electrode layer 203 are located on top of the pillars 112 of the same pillar group 113 and are in one-to-one correspondence with the pillars 112.

The plurality of upright posts 112 are regularly arranged into a plurality of upright post groups 113, the electrode openings 204 above the upright posts 112 of each upright post group 113 expose the same electrode layer 203, and the upright posts 112 in each upright post group 113 are arranged in an extending manner along the same direction, so that the electrode layers 203 on the upright posts 112 of each upright post group 113 are easy to be electrically connected with the interconnection lines extending along the same direction at the same time, the connection mode is simple, and the realization of a capacitor structure is facilitated.

In this embodiment, the electrode openings 204 of each electrode layer 203 are sequentially distributed on top of the pillars 112 of different pillar groups 113 along the second direction and according to a preset period, and each preset period has n adjacent pillar groups 113, where the first direction is perpendicular to the second direction.

Among the n adjacent pillar groups 113, the pillar groups 113 sequentially arranged along the second direction sequentially expose the surfaces of the 1 st to n th electrode layers 203, so that the arrangement of the electrode layers 203 exposed on the pillar groups 113 has regularity, which is beneficial to the regular arrangement of the interconnection lines formed above the pillar groups 113 and the electrode layers 203, so that the semiconductor structure has a regular structure, and the structural design and formation are easy to realize.

In this embodiment, the semiconductor structure further includes a plurality of second interconnection plugs 301 respectively located on the electrode layers 203 exposed at the bottoms of the electrode openings 204 and electrically connected to the corresponding electrode layers 203.

The second interconnect plugs 301 are used to load electrical signals to the corresponding electrode layers 203.

In this embodiment, the plurality of second interconnection plugs 301 are located on the exposed electrode layer 203 on the pillar 112, so that there is no need to form an additional area for etching the electrode layer 203 to be dedicated for forming the second interconnection plugs 301, which is beneficial to saving the occupied area of the semiconductor structure.

In this embodiment, the material of the second interconnection plug 301 is tungsten. In other embodiments, the material of the second interconnect plug may also be cobalt or ruthenium.

In this embodiment, the semiconductor structure further includes a plurality of second interconnect lines 401, where the second interconnect lines 401 extend along the first direction and are located on top of the second interconnect plugs 301 on the corresponding pillar groups 113, and the second interconnect lines 401 located on top of the second interconnect plugs 301 of the same electrode layer 203 are connected in parallel.

The second interconnect line 401 is used to electrically connect with the second interconnect plug 301, thereby loading the corresponding electrode layer 203 with an electrical signal through the second interconnect plug 301.

In this embodiment, the second interconnect lines 401 extend along the first direction and are located at the top of the second interconnect plugs 301 on the corresponding pillar groups 113, so that the pillars 112 of the same pillar group 113 expose the same electrode layer 203, and the same second interconnect lines 401 load the same electrode layer 203 with an electrical signal, and the second interconnect lines 401 located at the top of the second interconnect plugs 301 of the same electrode layer 203 are connected in parallel, so that the same electrical signal is loaded on the same electrode layer 203 in the multi-layer electrode layer 203, thereby realizing the basic function of the deep trench capacitor structure.

In this embodiment, the material of the second interconnect line 401 is tungsten. In other embodiments, the material of the second interconnect line may also be cobalt or ruthenium.

In this embodiment, among the plurality of second interconnect lines 401, the second interconnect lines 401 on top of the second interconnect plugs 301 of the electrode layers 203 of the odd numbered layers are connected in parallel, and the second interconnect lines 401 on top of the second interconnect plugs 301 of the electrode layers 203 of the even numbered layers are connected in parallel.

The second interconnection lines 401 on top of the second interconnection plugs 301 of the electrode layers 203 of the odd layers are connected in parallel, and the second interconnection lines 401 on top of the second interconnection plugs 301 of the electrode layers 203 of the even layers are connected in parallel, so that the electrode layers 203 of the odd layers load the same electrical signal, the electrode layers 203 of the even layers load the same electrical signal, and thus, the potential difference between the adjacent electrode layers 203 can be realized, and meanwhile, the electrical connection lines of the electrode layers 203 of the multi-layers are simplified, so that the electrical connection structure of the electrode layers 203 of the multi-layers is simple and easy to realize, and the formation cost of the semiconductor structure is saved.

Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 8 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 8, a substrate 100 is provided.

The device region 100A is used to form a capacitor structure, and the lead region 100B is used to electrically lead out the electrode layer.

Specifically, in the present embodiment, the lead regions 100B are located at both sides of the device region 100A, so that the subsequently formed multi-layered electrode layers can be electrically connected from the lead regions 100B at both sides, respectively, by distribution in the lead regions 100B at both sides, so that the electrical connection lines of the electrode layers are simplified and easy to implement.

Referring to fig. 9 and 10 in combination, fig. 10 is a sectional view of a portion of the pillars of fig. 9, a groove 200 is formed in the base 100, and pillars 110 protruding from the bottom of the groove 200 are formed, and the plurality of pillars 110 are separated from each other.

In this embodiment, the recess 200 is used to provide a spatial location for the formation of the electrode layer and the dielectric layer to be subsequently formed.

In this embodiment, the pillars 110 are used to form electrode layers formed later on the sidewalls thereof, so as to provide support for the formation of sidewall electrodes.

In this embodiment, the step of forming the recess 200 in the substrate 100 and forming the pillars 110 protruding from the bottom of the recess 200 includes patterning the substrate 100, forming the recess 200 in the substrate 100, and forming the plurality of pillars 110 protruding from the bottom of the recess 200.

The pillars 110 are obtained by patterning the substrate 100, and thus, the bottoms of the pillars 110 are connected to the substrate 100 to form an integrated structure, so that the pillars are obtained relatively simply, and, in this embodiment, the formation of the electrode layer 210 is correspondingly facilitated by patterning the substrate 100 while obtaining the recess 200 and the pillars 110 protruding from the bottom of the recess 200, such that the top surfaces of the pillars 110 are flush with the top of the recess 200.

In the present embodiment, in the step of forming the pillar 110 protruding from the bottom of the recess 200, the shape of the pillar 110 includes a cylindrical shape.

The pillar 110 is cylindrical, and then the sidewall electrode formed on the sidewall of the pillar 110 subsequently also encloses into a cylinder, so that the sidewall electrode tangential planes of the sidewalls of the adjacent pillar 110 are contacted, and a plurality of corresponding contacted surfaces can enclose into a gap.

In the step of forming the pillars 110, a plurality of pillars 110 extending in a first direction (as shown in an X direction in fig. 9) form a pillar group 111, the pillars 111 are arranged in parallel in a second direction (as shown in a Y direction in fig. 9), and the pillars 110 are staggered in the second direction in the adjacent pillar group 111, and the first direction is perpendicular to the second direction.

The plurality of columns 110 extending and arranged along the first direction form the column group 111, the number of the column groups 111 is a plurality of columns and the columns are arranged in parallel along the second direction, that is, the arrangement regularity of the columns 110 is good, and the remaining spaces except for the columns 110 in the grooves 200 are regular, so that the formation of the subsequent electrode layers is facilitated, and the electrical property of the capacitor structure formed by the electrode layers is stable.

In the adjacent column groups 111, the columns 110 are staggered in the second direction, that is, the columns 110 in one column group 111 are located at intervals of the adjacent columns 110 in the other column group 111 in the second direction in the adjacent column groups 111, so that the columns 110 and the adjacent columns 110 at the corresponding intervals can form a gap.

Referring to fig. 11 to 14 in combination, a multi-layered stacked electrode layer 201 and a dielectric layer (not shown) are formed, in the multi-layered electrode layer 201, the lowermost electrode layer 201 covers the respective surfaces of the grooves 200 and the respective surfaces of the pillars 110, and the remaining electrode layers 201 are sequentially stacked on the lowermost electrode layer 201, wherein a portion of the uppermost electrode layer 201 located on the sidewalls of the pillars 110 serves as a sidewall electrode 202, with a gap 200s between any adjacent sidewall electrodes 202.

Specifically, referring to fig. 12 and 13 in combination, fig. 13 is a cross-sectional view along AA direction of fig. 12, the pillar 110 is cylindrical, which is advantageous in that a stress direction generated in the groove 200 by the multi-layered stacked electrode layer 201 is along a diameter direction of the pillar 110 (as shown by a dotted arrow in fig. 13), so that stress distribution is more dispersed, thereby improving a problem of stress concentration and reducing an influence of stress on a semiconductor structure.

In the embodiment, in the step of forming the electrode layer 201 and the dielectric layer stacked in multiple layers, a furnace tube process is used to form each electrode layer 201 and each dielectric layer.

The electrode layer 201 and the dielectric layer are formed by a furnace tube process, which is beneficial to better forming the electrode layer 201 and the dielectric layer on the side wall of the upright post 110, and the gap 200s is not filled as much as possible.

In other embodiments, each electrode layer and dielectric layer may be formed by a chemical vapor deposition process.

Referring to fig. 11, 12 and 14 in combination, fig. 12 is a partial enlarged view of the triangular region 100t in fig. 11, fig. 14 is a cross-sectional view along the BB direction in fig. 12, and in the step of forming the electrode layer 201, the sidewall electrodes 202 on the sidewalls of the adjacent three pillars 110 arranged in a triangle form enclose a gap 200s.

In the step of forming the electrode layer 201 in this embodiment, the total thickness of the electrode layer 201 and the dielectric layer of the multi-layer stack satisfies the formulaWhere T represents the total thickness of the electrode layers 201 and the dielectric layers of the multi-layer stack, L represents the distance between the centers of circles of adjacent pillars 110 arranged in a triangle, and r represents the radius of the pillar 110.

Referring to fig. 11, in the step of forming the electrode layers 201, the electrode layers 201 are further located on top of the substrate 100 of the lead region 100B, and in the lead region 100B, any one electrode layer 201 exposes another adjacent electrode layer 201 located thereunder.

Specifically, in the step of forming the electrode layer 201 in this embodiment, the multi-layered electrode layer 201 includes the first electrode layer 210 and the second electrode layer 220 stacked alternately, the first electrode layer 210 exposing the surface of the second electrode layer 220 in any one of the lead regions 100B, and the second electrode layer 220 exposing the surface of the first electrode layer 210 in the other lead region 100B.

In this embodiment, after forming the electrode layer 201 and the dielectric layer, the forming method further includes forming a sealing layer 700 on top of the sealing gap 200 s.

In this embodiment, after forming the electrode layers 201 and the dielectric layers of the multi-layer stack, the forming method further includes forming, on each of the electrode layers 201 exposed in the lead region 100B, a plurality of first interconnect plugs 300 electrically connected to the corresponding electrode layer 201, the first interconnect plugs 300 on each of the electrode layers 201 being arranged along an extending direction of the lead region 100B, the extending direction being perpendicular to a direction in which the lead region 100B points to the device region 100A.

In this embodiment, a plurality of first interconnect lines 400 are formed, and each first interconnect line 400 is correspondingly located on the first interconnect plug 300 on the same electrode layer 201 and is electrically connected to a corresponding plurality of first interconnect plugs 300.

Referring to fig. 15, in the step of forming the electrode layers 203, electrode openings 204 are formed in the electrode layers 203 of the rest of the electrode layers 203 except for the electrode layer 203 of the bottommost layer, and the electrode openings 204 penetrate through the electrode layer 203 where they are located, wherein the electrode openings 204 of the electrode layers 203 are located at the top of different pillars 112.

In the step of forming the electrode layer 203 in this embodiment, the number of layers of the electrode layer 203 is n, and the electrode openings 204 of the same electrode layer 203 are located on top of the pillars 112 of the same pillar group 113 and are in one-to-one correspondence with the pillars 112.

In the step of forming the electrode layers 203 in this embodiment, the electrode openings 204 of each electrode layer 203 are sequentially distributed on top of the pillars 112 of the different pillar groups 113 along the second direction and according to a predetermined period, and each predetermined period has n neighboring pillar groups 113, where the first direction is perpendicular to the second direction.

In this embodiment, after forming the electrode layer 203 and the dielectric layer of the multi-layer stack, the forming method further includes forming second interconnection plugs 301 on the electrode layer 203 exposed at the bottom of the electrode opening 204, respectively, where the second interconnection plugs 301 are electrically connected to the corresponding electrode layers 203.

In this embodiment, a plurality of second interconnect lines 401 are formed on top of the second interconnect plugs 301, and the second interconnect lines 401 extend along the first direction and are located on top of the second interconnect plugs 301 on the corresponding pillar groups 113, and the second interconnect lines 401 located on top of the second interconnect plugs 301 of the same electrode layer 203 are connected in parallel.

In the step of forming the plurality of second interconnect lines 401 in this embodiment, the second interconnect lines 401 on top of the second interconnect plugs 301 of the electrode layers 203 of the odd numbered layers are connected in parallel, and the second interconnect lines 401 on top of the second interconnect plugs 301 of the electrode layers 203 of the even numbered layers are connected in parallel.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

A substrate;

A recess in the substrate;

the upright posts are convexly arranged at the bottom of the groove, and the upright posts are mutually separated;

The electrode layers are stacked in multiple layers, the electrode layer at the bottommost layer covers each surface of the groove and each surface of the upright post, and other electrode layers are stacked on the electrode layer at the bottommost layer in sequence, wherein the part of the electrode layer at the topmost layer, which is positioned on the side wall of the upright post, is used as a side wall electrode;

The dielectric layer is positioned between the adjacent electrode layers;

and a gap between any adjacent sidewall electrodes.

2. The semiconductor structure of claim 1, wherein the pillar bottom is connected to the base to form a unitary structure.

3. The semiconductor structure of claim 1, wherein a top surface of the pillar is flush with a top of the recess.

4. The semiconductor structure of claim 1, wherein the shape of the pillar comprises a cylindrical shape.

5. The semiconductor structure of claim 4, wherein a plurality of pillars extending in a first direction form a pillar group, the plurality of pillar groups being plural and arranged in parallel in a second direction, the plurality of pillars in adjacent pillar groups being staggered in the second direction, the first direction being perpendicular to the second direction;

the side wall electrodes on the side walls of the adjacent three upright posts which are arranged in a triangle form the gap.

6. The semiconductor structure of claim 5, wherein a total thickness of the electrode layer and the dielectric layer of the multi-layer stack satisfies a formula

Wherein T represents the total thickness of the electrode layers and the dielectric layers stacked in multiple layers, L represents the distance between circle centers of adjacent upright posts distributed in a triangle shape, and r represents the radius of each upright post.

7. The semiconductor structure of claim 1, further comprising a sealing layer located on top of and sealing the gap top.

8. The semiconductor structure of claim 7, wherein the material of the sealing layer comprises silicon oxide.

9. The semiconductor structure of any of claims 1-8, wherein the substrate comprises a device region, and a lead region adjacent to the device region;

the groove is positioned in the device region;

The electrode layers are also located on top of the base of the lead region, and in the lead region, any one electrode layer exposes an adjacent another electrode layer thereunder.

10. The semiconductor structure of claim 9, wherein the lead regions are located on both sides of the device region;

The plurality of electrode layers includes a first electrode layer and a second electrode layer alternately stacked, the first electrode layer exposing a surface of the second electrode layer in any one of the lead regions, and the second electrode layer exposing a surface of the first electrode layer in the other of the lead regions.

11. The semiconductor structure of claim 9, further comprising a first interconnect plug in the lead region on each exposed electrode layer and electrically connected to a corresponding electrode layer, the number of first interconnect plugs on each electrode layer being plural and arranged along an extension direction of the lead region, the extension direction being perpendicular to a direction in which the lead region is directed toward a device region;

And a plurality of first interconnection lines, each of which corresponds to a first interconnection plug on the same electrode layer and is electrically connected with the corresponding plurality of first interconnection plugs.

12. The semiconductor structure of any one of claims 1-8, further comprising electrode openings respectively located in the remaining electrode layers except the bottom electrode layer and penetrating the electrode layer, wherein the electrode openings of each electrode layer are located at the top of different pillars.

13. The semiconductor structure of claim 12, wherein a plurality of the pillars arranged in a first direction form a pillar group, the number of pillar groups being a plurality and arranged in parallel in a second direction;

The number of the electrode layers is n, and the electrode openings of the same electrode layer are positioned at the tops of the upright posts of the same upright post group and correspond to the upright posts one by one;

along the second direction and according to preset period, the electrode openings of each electrode layer are sequentially distributed at the tops of the upright posts of different upright post groups, each preset period is provided with n adjacent upright post groups, and the first direction is perpendicular to the second direction.

14. The semiconductor structure of claim 13, further comprising a plurality of second interconnect plugs respectively located on the electrode layers exposed at the bottom of the electrode openings and electrically connected to the corresponding electrode layers;

and the second interconnecting wires extend along the first direction and are positioned at the tops of the second interconnecting plugs on the corresponding column groups, and the second interconnecting wires positioned at the tops of the second interconnecting plugs of the same electrode layer are connected in parallel.

15. The semiconductor structure of claim 14, wherein among the plurality of second interconnect lines, second interconnect lines on top of second interconnect plugs of electrode layers of an odd number layer are connected in parallel, and second interconnect lines on top of second interconnect plugs of electrode layers of an even number layer are connected in parallel.

16. The semiconductor structure of claim 1, further comprising a via interconnect structure extending through the substrate;

The groove surrounds the through hole interconnection structure and comprises a plurality of sub-grooves which are communicated in sequence along the circumferential direction;

in each of the sub-grooves, a plurality of the pillars constitute hexagonal pillar cells.

17. The semiconductor structure of claim 1, wherein the material of the electrode layer comprises one or more of Si, W, cu, co, tiN, ti, ta, taN, ru, ruN and Al and the material of the dielectric layer comprises one or more of HfO₂、HfSiO、TiO₂、HfZrO、HfSiON、HfTaO、HfTiO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃、BaSrTiO and SiN.

18. A method of forming a semiconductor structure, comprising:

Providing a substrate;

forming a recess in the substrate;

Forming upright posts protruding from the bottoms of the grooves, wherein a plurality of the upright posts are mutually separated;

And forming a plurality of stacked electrode layers and dielectric layers, wherein in the plurality of electrode layers, the electrode layer at the bottommost layer covers each surface of the groove and each surface of the upright post, and the rest electrode layers are sequentially stacked on the electrode layer at the bottommost layer, wherein the part of the electrode layer at the topmost layer, which is positioned on the side wall of the upright post, is used as a side wall electrode, and a gap is formed between any two adjacent side wall electrodes.

19. The method of forming a semiconductor structure as recited in claim 18 wherein the step of forming a recess in said substrate and forming a stud protruding from a bottom of said recess comprises patterning said substrate, forming a recess in said substrate and forming a plurality of studs protruding from a bottom of said recess.

20. The method of forming a semiconductor structure of claim 18, wherein in the step of forming pillars protruding from the bottoms of the recesses, the pillars have a shape comprising a cylinder.

21. The method of forming a semiconductor structure according to claim 20, wherein in the step of forming the pillars, a plurality of pillars extending in a first direction form a pillar group, the plurality of pillar groups are arranged in parallel in a second direction, and a plurality of pillars in adjacent pillar groups are staggered in the second direction, the first direction being perpendicular to the second direction;

In the step of forming the electrode layer, the side wall electrodes on the side walls of the adjacent three upright posts which are arranged in a triangle form enclose the gaps.

22. The method of forming a semiconductor structure according to claim 21, wherein in the step of forming the electrode layer, a total thickness of the electrode layer and the dielectric layer of the multi-layer stack satisfies a formula

23. The method of forming a semiconductor structure as claimed in claim 18, wherein after forming the electrode layer and the dielectric layer, the method further comprises forming a sealing layer sealing a top of the gap.

24. The method of forming a semiconductor structure according to any one of claims 18 to 23, wherein in the step of providing the substrate, the substrate includes a device region and a lead region adjacent to the device region;

In the step of forming the groove, the groove is positioned in the device region;

In the step of forming the electrode layers, the electrode layers are further located on top of the substrate of the lead region, and in the lead region, any one electrode layer exposes another adjacent electrode layer located therebelow.

25. The method of forming a semiconductor structure of claim 24, wherein in the step of providing the substrate, the lead regions are located on both sides of the device region;

In the step of forming the electrode layers, the multi-layered electrode layer includes first electrode layers and second electrode layers alternately stacked, the first electrode layers exposing the second electrode layer surface in any one of the lead regions, and the second electrode layers exposing the first electrode layer surface in the other lead region.

26. The method of forming a semiconductor structure as claimed in claim 24, wherein after forming the electrode layers and the dielectric layers of the multi-layered stack, the method further comprises forming a plurality of first interconnection plugs electrically connected to the corresponding electrode layers on each of the electrode layers exposed in the lead region, the first interconnection plugs on each of the electrode layers being arranged in an extending direction of the lead region, the extending direction being perpendicular to a direction in which the lead region is directed toward the device region;

And forming a plurality of first interconnection lines, wherein each first interconnection line is correspondingly positioned on the first interconnection plug on the same electrode layer and is electrically connected with the corresponding plurality of first interconnection plugs.

27. The method for forming a semiconductor structure according to any one of claims 18 to 23, wherein in the step of forming the electrode layers, electrode openings are formed in the electrode layers of the remaining layers except for the electrode layer of the bottommost layer, the electrode openings penetrate through the electrode layer where the electrode openings are located, and wherein the electrode openings of the electrode layers are located at the top of different pillars.

28. The method of forming a semiconductor structure according to claim 27, wherein in the step of forming the pillars, a plurality of the pillars arranged to extend in a first direction form a pillar group, the number of the pillar group being plural and arranged in parallel in a second direction;

in the step of forming the electrode layers, the number of layers of the electrode layers is n, and electrode openings of the same electrode layer are positioned at the tops of the upright posts of the same upright post group and correspond to the upright posts one by one;

In the step of forming the electrode layers, along the second direction and according to preset periods, electrode openings of the electrode layers are sequentially distributed at the tops of the columns of different column groups, each preset period is provided with n adjacent column groups, and the first direction is perpendicular to the second direction.

29. The method of forming a semiconductor structure as claimed in claim 28, wherein after forming the electrode layers and the dielectric layers of the multi-layer stack, the method further comprises forming second interconnection plugs on the electrode layers exposed at the bottoms of the electrode openings, respectively, the second interconnection plugs being electrically connected to the corresponding electrode layers;

and forming a plurality of second interconnection lines on the tops of the second interconnection plugs, wherein the second interconnection lines extend along the first direction and are positioned on the tops of the second interconnection plugs on the corresponding column groups, and the interconnection lines on the tops of the second interconnection plugs on the same electrode layer are connected in parallel.

30. The method of forming a semiconductor structure according to claim 29, wherein in the step of forming a plurality of the second interconnect lines, the second interconnect lines on top of the second interconnect plugs of the electrode layers of the odd numbered layers are connected in parallel, and the second interconnect lines on top of the second interconnect plugs of the electrode layers of the even numbered layers are connected in parallel.

31. The method of forming a semiconductor structure of claim 18, wherein in the step of providing the substrate, a via interconnect structure is formed through the substrate in the substrate;

In the step of forming the groove, the groove surrounds the through hole interconnection structure and comprises a plurality of sub-grooves which are communicated in sequence along the circumferential direction;

in the step of forming the pillars, in each of the sub-grooves, a plurality of the pillars constitute hexagonal pillar cells.

32. The method of claim 18, wherein in the step of forming the electrode layer and the dielectric layer of the multi-layer stack, a furnace tube process is used to form each of the electrode layer and the dielectric layer.