CN110956008B - A subthreshold digital circuit timing optimization method and system - Google Patents
A subthreshold digital circuit timing optimization method and system Download PDFInfo
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Abstract
A method for optimizing time sequence of sub-threshold digital circuit includes confirming logic unit circuit capable of utilizing reverse short channel effect to raise performance, carrying out time sequence analysis on given integrated circuit to obtain all signal paths not meeting time sequence requirement, confirming multiple main delay units capable of utilizing reverse short channel effect to raise performance in each signal path not meeting time sequence requirement, utilizing reverse short channel effect to regulate gate length of device of main delay unit according to preset time sequence constraint condition and optimizing time sequence of sub-threshold digital circuit by regulation of gate length size. The invention increases the gate length of the device of the main delay unit by utilizing the reverse short channel effect so as to realize time sequence optimization, improve the circuit performance of the sub-threshold digital circuit, reduce the delay time of the unit, and simultaneously, improve the consistency of the delay of the unit by utilizing the area increase so as to enhance the robustness of the circuit.
Description
Technical Field
The invention relates to the technical field of circuit timing optimization, in particular to a sub-threshold digital circuit timing optimization method and system.
Background
The subthreshold digital circuit refers to a digital logic circuit with the working voltage lower than the threshold voltage of a transistor device, and the dynamic power consumption and the static power consumption of the circuit can be greatly reduced because the circuit works in a subthreshold area. Because the device works in the subthreshold region, the current and the voltage of the device are in an exponential relation, and the change of the size of the device can cause obvious current change and parasitic capacitance change, so that the electrical property of the circuit is obviously changed. In addition, the fluctuation of the circuit performance along with the PVT (Process-Voltage-Temperature-Voltage) deviation is large, so that in order to make the designed sub-threshold digital circuit have high robustness, the statistical analysis and optimization of the PVT deviation need to be considered in the design optimization Process of the sub-threshold digital circuit, and the complexity of the device size optimization of the sub-threshold digital circuit can be exponentially increased, so that the device optimization speed Process becomes very slow.
At present, with the increase of the scale of a sub-threshold digital circuit, the statistical analysis and optimization of PVT deviation and the traditional random optimization algorithm and heuristic optimization algorithm are combined together, so that the method cannot be directly applied to the optimization of the sub-threshold digital circuit with a larger scale, and particularly cannot be directly applied to the optimization of a sub-threshold digital time sequence circuit with a larger scale. In addition, in order to improve the performance of the subthreshold digital circuit, the traditional method is to increase the gate width/gate length ratio of the MOS devices in the circuit, but the increase of the gate width can obviously increase the area, can cause the discretization of the cell heights in the standard cell library to be used, further cause the area waste, and the reduction of the gate length of the cells working in the subthreshold region can possibly reduce the performance of the cells due to the reverse short channel effect, and simultaneously can cause the performance distribution of the cells to be flatter due to the reduction of the product of the gate width and the gate length, thereby reducing the robustness of the circuit design.
Disclosure of Invention
The invention provides a sub-threshold digital circuit time sequence optimizing method and a system, which utilize reverse short channel effect to increase the gate length of a device of a main delay unit so as to realize time sequence optimization, improve the circuit performance of the sub-threshold digital circuit, reduce the delay time of the unit, and simultaneously, utilize area increase to improve the consistency of the unit delay, thereby enhancing the robustness of the circuit.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a sub-threshold digital circuit timing optimization method, comprising:
Determining a logic cell circuit capable of improving performance by utilizing reverse short channel effect;
Performing time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement, wherein the signal paths comprise latches and front-end combinational logic thereof or flip-flops and front-end combinational logic thereof;
determining a plurality of main delay units which can utilize reverse short channel effect to improve performance in each signal path which does not meet the time sequence requirement;
and the gate length of the device of the main delay unit is increased by utilizing the reverse short channel effect according to a preset time sequence constraint condition, so that the time sequence of the sub-threshold digital circuit is optimized through the adjustment of the gate length.
Further, the step of determining a logic cell circuit capable of improving performance by utilizing reverse short channel effect includes:
Acquiring a logic unit circuit in a logic unit library or a logic unit circuit cited in the design to be optimized;
Changing the gate length of an MOS device in each logic unit circuit, obtaining the input-output waveform of the logic unit circuit under the corresponding gate length through simulation of the logic unit circuits, and measuring the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length to obtain gate length-delay data;
Checking the gate length-delay data to see whether a region with delay smaller than that under the original gate length exists in a region with the gate length longer than the original gate length;
and if yes, the logic unit circuit is listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit is not listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect.
Further, the method further comprises the following steps:
And for the logic unit circuit capable of improving performance by utilizing reverse short channel effect, changing the gate length of an MOS device in the logic unit circuit, obtaining the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measuring the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit, and establishing a delay-gate length relation lookup table of the logic unit circuit.
Further, the method further comprises the following steps:
And for the logic unit circuit capable of improving performance by utilizing reverse short channel effect, changing the gate length of an MOS device in the logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit, acquiring the power consumption of the logic unit circuit under the delay, and establishing a delay-power consumption relation lookup table of the logic unit circuit.
Further, the method further comprises the following steps:
And obtaining the minimum delay of the logic unit circuit under the preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, namely the performance optimization coefficient of the logic unit circuit.
Further, the method further comprises the following steps:
And the design meeting the time sequence constraint takes the gate length as an initial value, the gate length is finely adjusted through an optimization algorithm, and the power consumption of the logic unit circuit is estimated by utilizing the gate length-power consumption relation lookup table on the premise of meeting the preset time sequence constraint condition, so that the power consumption of the circuit is optimized.
Further, the step of performing timing analysis on the given integrated circuit to obtain all signal paths which do not meet the timing requirement includes:
Carrying out time sequence analysis on a given integrated circuit by using a statistical time sequence analysis tool or based on circuit statistical simulation to obtain the time delay distribution of all signal paths;
judging whether the delay distribution of each signal path meets the preset time sequence constraint condition or not;
And listing the signal paths which do not meet the preset time sequence constraint conditions and correspond to the signal paths which do not meet the time sequence requirements.
Further, the step of determining a number of main delay cell circuits in each of the signal paths that do not meet timing requirements that can improve performance using reverse short channel effects includes:
If the logic unit circuit in the signal path which does not meet the time sequence requirement is the calibrated logic unit circuit in the performance improvement by utilizing the reverse short channel effect, the logic unit circuit is listed as a main delay unit circuit in the performance improvement by utilizing the reverse short channel effect;
if the latch or the trigger in the signal path which does not meet the time sequence requirement is the calibrated logic unit circuit which can utilize the reverse short channel effect to improve the performance, the latch or the trigger is listed as the main delay unit circuit which can utilize the reverse short channel effect to improve the performance.
A sub-threshold digital circuit timing optimization system, comprising:
a first determination unit configured to determine a logic cell circuit that can improve performance using reverse short channel effect;
the analysis unit is used for carrying out time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement, wherein the signal paths comprise a relay and front-end combination logic thereof;
A second determining unit, configured to determine a plurality of main delay units capable of improving performance by using reverse short channel effect in each signal path that does not meet a timing requirement;
And the adjusting unit is used for adjusting the gate length of the device of the main delay unit according to a preset time sequence constraint condition by utilizing the reverse short channel effect so as to optimize the time sequence of the sub-threshold digital circuit through the adjustment of the gate length.
Further, the first determining unit includes:
The acquisition unit is used for acquiring logic unit circuits in a logic unit library or logic unit circuits referenced in the design to be optimized;
the processing unit is used for changing the gate length of the MOS device in each logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length through simulation of the logic unit circuits, and measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit under the corresponding gate length so as to acquire gate length-delay data;
The checking unit is used for checking the gate length-delay data to see whether an area with delay smaller than that under the original gate length exists in an area with the gate length longer than the original gate length;
and if yes, the logic unit circuit is listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit is not listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect.
Compared with the prior art, the invention discloses a sub-threshold digital circuit time sequence optimizing method and a sub-threshold digital circuit time sequence optimizing system, wherein the method comprises the steps of firstly determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect; the method comprises the steps of obtaining a time sequence requirement of a sub-threshold digital circuit, carrying out time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement, determining a plurality of main delay units which can improve performance by utilizing reverse short channel effect in each signal path which does not meet the time sequence requirement, and finally utilizing the reverse short channel effect to adjust the gate length of a device of the main delay unit according to a preset time sequence constraint condition so as to optimize the time sequence of the sub-threshold digital circuit through the adjustment of the gate length. The invention increases the gate length of the device of the main delay unit by utilizing the reverse short channel effect so as to realize time sequence optimization, improve the circuit performance of the sub-threshold digital circuit, reduce the delay time of the unit, and simultaneously, improve the consistency of the delay of the unit by utilizing the area increase so as to enhance the robustness of the circuit.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a sub-threshold digital circuit timing optimization method according to an embodiment of the present invention;
FIG. 2 is a flowchart of a specific implementation of step S101 according to an embodiment of the present invention;
FIG. 3 is a flowchart of a specific implementation of step S102 according to an embodiment of the present invention;
Fig. 4 is a structural diagram of a sub-threshold digital circuit timing optimization system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the embodiment of the invention provides a sub-threshold digital circuit timing optimization method, which specifically includes the following steps:
s101, determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect.
In an embodiment of the present invention, as shown in fig. 2, in a specific implementation manner of the step S101, specifically, the step of determining the logic cell circuit capable of improving performance by using the reverse short channel effect includes:
S201, acquiring a logic unit circuit in a logic unit library or a logic unit circuit referenced in the design to be optimized.
S202, changing the gate length of the MOS device in each logic unit circuit, obtaining the input-output waveform of the logic unit circuit under the corresponding gate length through simulation of the logic unit circuit, and measuring the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length to obtain the gate length-delay data.
And S203, checking the gate length-delay data to see whether an area with delay smaller than that of the original gate length exists in the area with the gate length larger than the original gate length, if so, executing the step S204, and if not, executing the step S205.
S204, the logic unit circuits are listed as logic unit circuits capable of improving performance by utilizing reverse short channel effect.
S205, the logic unit circuit is listed as a logic unit circuit which can not utilize the reverse short channel effect to improve the performance.
Further, after determining the logic cell circuit capable of improving performance by utilizing the reverse short channel effect, the method further comprises:
For a logic unit circuit capable of improving performance by utilizing reverse short channel effect, changing the gate length of an MOS device in the logic unit circuit, acquiring an input-output waveform of the logic unit circuit under the corresponding gate length through simulation of the logic unit circuit, measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit, and establishing a delay-gate length relation lookup table of the logic unit circuit.
Further, after determining the logic cell circuit capable of improving performance by utilizing the reverse short channel effect, the method further comprises:
For a logic unit circuit capable of improving performance by utilizing reverse short channel effect, changing the gate length of an MOS device in the logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length through simulation of the logic unit circuit, measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit, acquiring the power consumption of the logic unit circuit under the delay, and establishing a delay-power consumption relation lookup table of the logic unit circuit.
Further, after determining the logic cell circuit capable of improving performance by utilizing the reverse short channel effect, the method further comprises:
For the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, the minimum delay of the logic unit circuit under the preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length are obtained, namely the performance optimization coefficient of the logic unit circuit.
Further, after determining the logic cell circuit capable of improving performance by utilizing the reverse short channel effect, the method further comprises:
Based on the statistical simulation of the logic unit circuit, a statistical delay-gate length relation lookup table of the logic unit circuit is established.
Further, after determining the logic cell circuit capable of improving performance by utilizing the reverse short channel effect, the method further comprises:
And the design meeting the time sequence constraint takes the gate length as an initial value, the gate length is finely adjusted through an optimization algorithm, and the power consumption of the logic unit circuit is estimated by using the gate length-power consumption relation lookup table on the premise of meeting the preset time sequence constraint condition, so that the power consumption of the circuit is optimized.
S102, carrying out time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement, wherein the signal paths comprise latches and front-end combinational logic thereof or flip-flops and front-end combinational logic thereof.
In the embodiment of the present invention, as shown in fig. 3, in a specific implementation manner of the step S102, specifically, the step of performing timing analysis on a given integrated circuit to obtain all signal paths that do not meet the timing requirement includes:
S301, performing time sequence analysis on a given integrated circuit by using a statistical time sequence analysis tool or based on circuit statistical simulation to obtain the time delay distribution of all signal paths, wherein the signal paths comprise latches and front-end combinational logic or flip-flops and front-end combinational logic.
S302, judging whether the delay distribution of each signal path meets the preset time sequence constraint condition, if not, executing step S303, and if yes, executing step S304.
S303, the signal paths which do not meet the preset time sequence constraint conditions are listed as the signal paths which do not meet the time sequence requirements.
S304, the signal paths corresponding to the preset time sequence constraint conditions are listed into the signal paths meeting the time sequence requirements.
In the embodiment of the present invention, for each latch and its front-end combinational logic or flip-flop and its front-end combinational logic, a preset time sequence constraint condition needs to be satisfied, where the preset time sequence constraint condition specifically is:
tPrev_FF-Pdelay,max+tCML-Pdelay,max+tFF-setup,max＜α.Tclock
tPrev_FF-Pdelay,min+tCML-Pdelay,min＞β.tFF-hold,max
wherein alpha is between (0, 1), beta is between (1, +_1), T Prev_FF-Pdelay,max is the maximum value of the output delay time of the front-stage latch or trigger, T CML-Pdelay,max is the maximum value of the time when the output signal of the front-end combinational logic circuit reaches the latch or trigger, T clock is the clock signal period of the time sequence circuit, namely the inverse value of the clock signal frequency, T CML-Pdelay,min is the minimum value of the time when the output of the front-end combinational logic reaches the latch or trigger, T Prev_FF-Pdelay,min is the minimum value of the data output delay time of the front-stage latch or trigger, T FF-hold,max is the maximum data input holding time of the latch or trigger, and T FF-setup,max is the maximum data input establishing time of the latch or trigger.
S103, determining a plurality of main delay units which can improve the performance by utilizing the reverse short channel effect in each signal path which does not meet the time sequence requirement.
In the embodiment of the present invention, specifically, the step of determining a plurality of main delay unit circuits capable of improving performance by using reverse short channel effect in each signal path which does not meet the timing requirement includes:
if the logic unit circuit in the signal path which does not meet the time sequence requirement is the calibrated logic unit circuit which can utilize the reverse short channel effect to improve the performance, the logic unit circuit is listed as the main delay unit circuit which can utilize the reverse short channel effect to improve the performance.
If the latches or flip-flops in the signal path that do not meet the timing requirements are calibrated logic cell circuits that can improve performance using reverse short channel effects, they are listed as the main delay cell circuits that can improve performance using reverse short channel effects.
Specifically, for each front-end combined logic circuit which does not meet the time sequence requirement and a latch or a trigger, the result of determining a unit capable of improving the performance by utilizing the reverse short channel effect is utilized to check out a main delay unit capable of improving the performance by utilizing the reverse short channel effect, if the logic unit in the front-end combined logic circuit which does not meet the time sequence requirement is the calibrated logic unit capable of improving the performance by utilizing the reverse short channel effect, the logic unit is listed as the main delay unit capable of improving the performance by utilizing the reverse short channel effect, otherwise, the logic unit is excluded from units to be optimized, and the latch or the trigger circuit is subjected to the same treatment.
S104, utilizing the reverse short channel effect to adjust the gate length of the device of the main delay unit according to a preset time sequence constraint condition so as to optimize the time sequence of the sub-threshold digital circuit through the adjustment of the gate length.
In the embodiment of the present invention, according to the predetermined timing constraint conditions that each latch or flip-flop and front-end combinational logic circuit must follow, the predetermined timing constraint conditions are:
tPrev_FF-Pdelay,max+tCML-Pdelay,max+tFF-setup,max＜α.Tclock
tPrev_FF-Pdelay,min+tCML-Pdelay,min＞β.tFF-hold,max
Wherein T clock is the clock signal period of the time sequence circuit, namely the inverse value of the clock signal frequency, T Prev_FF-Pdelay,max is the maximum value of the output delay time of a front-stage latch or trigger, T CM-LPd,elay is the maximum value of the time when the output signal of the front-stage ma-end x combination logic circuit reaches the latch or trigger, T clock is the clock signal period of the time sequence circuit, namely the inverse value of the clock signal frequency, T CML-Pdelay,min is the minimum value of the time when the output of the front-stage combination logic reaches the latch or trigger, T Prev_FF-Pdelay,min is the minimum value of the data output delay time of the front-stage latch or trigger, T FF-hold,max is the data input maximum holding time of the latch or trigger, and T FF-setup,max is the data input maximum establishing time of the latch or trigger.
In addition, t CML-Pdelay,max and t CML-Pdelay,min are respectively determined by the maximum delay time and the minimum delay time of each stage of logic gate, specifically:
tCML-Pdelay,max＝∑tCell-Pdelay,max,i
tCML-Pdelay,min＝∑tCell-Pdelay,min,i
For latches or flip-flops and their front-end combinational logic that do not meet the above-mentioned predetermined timing constraints, the delay space that needs to be improved is respectively located as follows:
tdelay_improve_goal1＝(tPrev_FF-Pdelay,max+tCML-Pdelay,max+tFF-setup,max)-α.Tclock
tdelay_improve_goal2＝β.tFF-hold,max-(tPrev_FF-Pdelay,min+tCML-Pdelay,min)
in addition, it is considered that only the logic cell circuits that can utilize the reverse short channel effect are adjusted to optimize the delay performance of the front-end combinational logic circuit (latch or flip-flop is not adjusted or not adjustable):
-∑ΔtRCSE_Cell-Pdelay,max,i≥tdelay_improve_goal1
∑ΔtRCSE_Cell-Pdelay,min,i≥tdelay_improve_goal2
In addition, it is contemplated that the cells (including latches or flip-flops) that can take advantage of reverse short channel effects may be tuned to optimize the delay performance of the front-end combinational logic circuit:
-∑ΔtRCSE_Cell-Pdelay,max,i-ΔtPrev_FF-Pdelay,max-ΔtFF-setup,max≥tdelay_improve_goal1
∑ΔtRCSE_Cell-Pdelay,min,i-ΔtFF-hold,max+ΔtPrev_FF-Pdelay,min≥tdelay_improve_goal2
Wherein:
ΔtRCSE_Cell-Pdelay,max,i＝tRCSE_Cell-Pdelay,max,i,new-tRCSE_Cell-Pdelay,max,I,org
ΔtRCSE_Cell-Pdelay,min,i＝tRCSE_Cell-Pdelay,min,i,new-tRCSE_Cell-Pdelay,min,i,org
ΔtPrev_FF-Pdelay,max＝tPrev_FF-Pdelay,max,new-tPrev_FF-Pdelay,max,org
ΔtPrev_FF-Pdelay,min＝tPrev_FF-Pdelay,min,new-tPrev_FF-Pdelay,min,org
ΔtFF-setup,max＝tFF-setup,max,new-tFF-setup,max,org
ΔtFF-hold,max＝tFF-hold,max,new-tFF-hold,max,org
Specifically, t RCSE_Cell-Pdelay,max,i,new is the maximum delay time after the gate length can be adjusted by the logic unit i for improving the delay performance by using the reverse short channel effect, t RCSE_Cell-Pdelay,max,I,org is the maximum delay time before the gate length can be adjusted by the logic unit i for improving the delay performance by using the reverse short channel effect (i.e. the original gate length), t RCSE_Cell-Pdelay,min,i,new is the minimum delay time after the gate length can be adjusted by the logic unit i for improving the delay performance by using the reverse short channel effect, t RCSE_Cell-Pdelay,min,i,org is the minimum delay time before the gate length can be adjusted by the logic unit i for improving the delay performance by using the reverse short channel effect (i.e. the original gate length), t Prev_FF-Pdelay,max,new is the maximum delay time after the gate length can be adjusted by the front latch or the trigger for improving the delay performance by using the reverse short channel effect, t Prev_FF-Pdelay,max,org is the maximum delay time before the gate length can be adjusted by using the front latch or the trigger for improving the delay performance by using the reverse short channel effect (i.e. the original gate length), t Prev_FF-Pdelay,min,new is the minimum delay time after the gate length can be adjusted by using the reverse short channel effect, t Prev_FF-Pdelay,min,org is the front latch or the trigger for improving the delay performance by using the reverse short channel effect (i.e. the original gate length can be adjusted by using the reverse short channel effect), t FF-setup,max,new is the front latch or the trigger for improving the delay performance by using the reverse short channel effect T FF-hold,max,org is the maximum retention time of the input data before the latch or the trigger for improving the delay performance by utilizing the reverse short channel effect adjusts the gate length (namely the original gate length).
For the set of inequality:
-∑ΔtRCSE_Cell-Pdelay,max,i≥tdelay_improve_goal1
∑ΔtRCSE_Cell-Pdelay,min,i≥tdelay_improve_goal2
Or (b)
-∑ΔtRCSE_Cell-Pdelay,max,i-ΔtFF-setup,max≥tdelay_improve_goal1+ΔtPrev_FF-Pdelay,max
∑ΔtRCSE_Cell-Pdelay,min,i-ΔtFF-hold,max≥tdelay_improve_goal2-ΔtPrev_FF-Pdelay,min
Solving to obtain the minimum value of delta t RCSE_Cell-Pdelay,max,i of each adjustable logic unit circuit, the maximum value of delta t RCSE_Cell-Pdelay,min,i of each adjustable logic unit, the maximum value of delta t FF-setup,max of each adjustable latch or trigger, and the maximum value of delta t FF-hold,max of each adjustable latch or trigger;
Further according to the following four formulas:
tRCSE_Cell-Pdelay,max,i,new＝tRCSE_Cell-Pdelay,max,I,org+ΔtRCSE_Cell-Pdelay,max,i
tRCSE_Cell-Pdelay,min,i,new＝tRCSE_Cell-Pdelay,min,i,org+ΔtRCSE_Cell-Pdelay,min,i
tFF-setup,max,new＝tFF-setup,max,org+ΔtFF-setup,max
tFF-hold,max,new＝tFF-hold,max,org+ΔtFF-hold,max
The delay of the cell at the new gate length is obtained as t RCSE_Cell-Pdelay,max,i,new;tRCSE_Cell-Pdelay,min,i,new;tFF-setup,max,new and t FF-hold,max,new.
According to the established delay-gate length relation lookup table of the unit, the gate length after the adjustment of the corresponding adjustable logic unit is obtained, and the delay t RCS_EC-ellP,dela,y,max、itRCSE_Cell-Pdelay,min,i,new、tFF-setup,max,new and t FF-hold,max,new of the unit under the new gate length can enable the corresponding front-end combination logic circuit and latch or trigger circuit to meet the time sequence requirement, so that the optimization of the time sequence through the adjustment of the gate length is realized.
Further, the adjusted gate length is used as an initial value, the gate length is finely adjusted through an optimization algorithm, and the unit power consumption is estimated by using the established gate length-power consumption relation lookup table on the premise that the preset time sequence constraint condition is met, so that the power consumption of the circuit is optimized.
Further, based on the sequence of the signal paths, the gate length of the front-end combination logic circuit and the latch or trigger circuit combination is increased for the device of the main delay unit by utilizing the reverse short channel effect, so that the circuit performance is improved, the delay time of the unit is reduced, the delay consistency of the unit is improved, the time sequence optimization is realized, and the path delay consistency is improved.
The embodiment of the invention discloses a sub-threshold digital circuit time sequence optimizing method, which comprises the steps of firstly determining a logic unit circuit capable of improving performance by utilizing reverse short channel effect, then carrying out time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet time sequence requirements, then determining a plurality of main delay units capable of improving the performance by utilizing the reverse short channel effect in each signal path which do not meet the time sequence requirements, and finally utilizing the reverse short channel effect to adjust the gate length of a device of the main delay units according to preset time sequence constraint conditions so as to optimize the time sequence of the sub-threshold digital circuit by adjusting the gate length. The invention increases the gate length of the device of the main delay unit by utilizing the reverse short channel effect so as to realize time sequence optimization, improve the circuit performance of the sub-threshold digital circuit, reduce the delay time of the unit, and simultaneously, improve the consistency of the delay of the unit by utilizing the area increase so as to enhance the robustness of the circuit.
Referring to fig. 4, based on the sub-threshold digital circuit timing optimization method disclosed in the above embodiment, the present embodiment correspondingly discloses a sub-threshold digital circuit timing optimization system, which specifically includes a first determining unit 401, an analyzing unit 402, a second determining unit 403, and an adjusting unit 404, wherein:
a first determining unit 401 for determining a logic cell circuit that can improve performance using reverse short channel effect;
An analysis unit 402, configured to perform timing analysis on a given integrated circuit, to obtain all signal paths that do not meet the timing requirement, where the signal paths include a relay and front-end combinational logic thereof;
a second determining unit 403, configured to determine a plurality of main delay units in each signal path that does not meet the timing requirement, where the main delay units can improve performance by using reverse short channel effect;
And the adjusting unit 404 is configured to adjust the gate length of the device of the main delay unit according to a preset timing constraint condition by using the reverse short channel effect, so as to optimize the timing of the subthreshold digital circuit through the adjustment of the gate length.
Further, the first determining unit 401 specifically includes an acquiring unit 4011, a processing unit 4012, and an inspecting unit 4013, wherein:
An acquisition unit 4011 for acquiring a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized;
A processing unit 4012, configured to change a gate length of a MOS device in the logic unit circuit for each logic unit circuit, obtain an input-output waveform of the logic unit circuit corresponding to the gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit, and obtain a delay of the logic unit circuit corresponding to the gate length, so as to obtain gate length-delay data;
An inspection unit 4013 for inspecting the gate length-delay data to see whether there is a region with a delay smaller than the delay under the original gate length in a region with a gate length longer than the original gate length;
If yes, the logic unit circuit is listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit is not listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect.
The embodiment of the invention discloses a sub-threshold digital circuit time sequence optimizing system, which comprises a logic unit circuit capable of improving performance by utilizing reverse short channel effect through a first determining unit, a given integrated circuit is subjected to time sequence analysis through an analyzing unit to obtain all signal paths which do not meet the time sequence requirement, a plurality of main delay units capable of improving the performance by utilizing the reverse short channel effect in each signal path which do not meet the time sequence requirement are determined through a second determining unit, and finally, the gate length of a device of the main delay unit is increased by utilizing the reverse short channel effect according to a preset time sequence constraint condition through an adjusting unit so as to optimize the time sequence of the sub-threshold digital circuit through the adjustment of the gate length. The invention increases the gate length of the device of the main delay unit by utilizing the reverse short channel effect so as to realize time sequence optimization, improve the circuit performance of the sub-threshold digital circuit, reduce the delay time of the unit, and simultaneously, improve the consistency of the delay of the unit by utilizing the area increase so as to enhance the robustness of the circuit.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of additional like elements in an article or apparatus that comprises such an element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A method for sub-threshold digital circuit timing optimization, comprising:
Determining a logic cell circuit capable of improving performance by utilizing reverse short channel effect;
Performing time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement, wherein the signal paths comprise latches and front-end combinational logic thereof or flip-flops and front-end combinational logic thereof;
determining a plurality of main delay units which can utilize reverse short channel effect to improve performance in each signal path which does not meet the time sequence requirement;
the gate length of the device of the main delay unit is increased by utilizing the reverse short channel effect according to a preset time sequence constraint condition, so that the time sequence of the sub-threshold digital circuit is optimized through the adjustment of the gate length;
The step of determining a logic cell circuit that can improve performance using reverse short channel effect includes:
Acquiring a logic unit circuit in a logic unit library or a logic unit circuit cited in the design to be optimized;
Changing the gate length of an MOS device in each logic unit circuit, obtaining the input-output waveform of the logic unit circuit under the corresponding gate length through simulation of the logic unit circuits, and measuring the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length to obtain gate length-delay data;
Checking the gate length-delay data to see whether a region with delay smaller than that under the original gate length exists in a region with the gate length longer than the original gate length;
If yes, the logic unit circuit is listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit is not listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect;
The step of determining a number of main delay units in each of the signal paths that do not meet timing requirements that can improve performance using reverse short channel effects comprises:
If the logic unit circuit in the signal path which does not meet the time sequence requirement is the calibrated logic unit circuit in the performance improvement by utilizing the reverse short channel effect, the logic unit circuit is listed as a main delay unit circuit in the performance improvement by utilizing the reverse short channel effect;
if the latch or the trigger in the signal path which does not meet the time sequence requirement is the calibrated logic unit circuit which can utilize the reverse short channel effect to improve the performance, the latch or the trigger is listed as the main delay unit circuit which can utilize the reverse short channel effect to improve the performance.
2. The method as recited in claim 1, further comprising:
And for the logic unit circuit capable of improving performance by utilizing reverse short channel effect, changing the gate length of an MOS device in the logic unit circuit, obtaining the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measuring the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit, and establishing a delay-gate length relation lookup table of the logic unit circuit.
3. The method as recited in claim 1, further comprising:
And for the logic unit circuit capable of improving performance by utilizing reverse short channel effect, changing the gate length of an MOS device in the logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit, acquiring the power consumption of the logic unit circuit under the delay, and establishing a delay-power consumption relation lookup table of the logic unit circuit.
4. The method as recited in claim 1, further comprising:
And obtaining the minimum delay of the logic unit circuit under the preset gate width and the maximum value of the delay reduction coefficient relative to the original gate length for the logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, namely the performance optimization coefficient of the logic unit circuit.
5. The method as recited in claim 1, further comprising:
and the design meeting the time sequence constraint takes the gate length as an initial value, the gate length is finely adjusted through an optimization algorithm, and the power consumption of the logic unit circuit is estimated by utilizing a gate length-power consumption relation lookup table on the premise of meeting the preset time sequence constraint condition, so that the power consumption of the circuit is optimized.
6. The method of claim 1, wherein the step of performing a timing analysis on a given integrated circuit to derive all signal paths that do not meet timing requirements comprises:
Carrying out time sequence analysis on a given integrated circuit by using a statistical time sequence analysis tool or based on circuit statistical simulation to obtain the time delay distribution of all signal paths;
judging whether the delay distribution of each signal path meets the preset time sequence constraint condition or not;
And listing the signal paths which do not meet the preset time sequence constraint conditions and correspond to the signal paths which do not meet the time sequence requirements.
7. A sub-threshold digital circuit timing optimization system, comprising:
a first determination unit configured to determine a logic cell circuit that can improve performance using reverse short channel effect;
the analysis unit is used for carrying out time sequence analysis on a given integrated circuit to obtain all signal paths which do not meet the time sequence requirement, wherein the signal paths comprise a relay and front-end combination logic thereof;
A second determining unit, configured to determine a plurality of main delay units capable of improving performance by using reverse short channel effect in each signal path that does not meet a timing requirement;
The adjusting unit is used for adjusting the gate length of the device of the main delay unit according to a preset time sequence constraint condition by utilizing the reverse short channel effect so as to optimize the time sequence of the sub-threshold digital circuit through the adjustment of the gate length;
the first determination unit includes:
The acquisition unit is used for acquiring logic unit circuits in a logic unit library or logic unit circuits referenced in the design to be optimized;
the processing unit is used for changing the gate length of the MOS device in each logic unit circuit, acquiring the input-output waveform of the logic unit circuit under the corresponding gate length through simulation of the logic unit circuits, and measuring the input-output waveform of the logic unit circuit to acquire the delay of the logic unit circuit under the corresponding gate length so as to acquire gate length-delay data;
The checking unit is used for checking the gate length-delay data to see whether an area with delay smaller than that under the original gate length exists in an area with the gate length longer than the original gate length;
If yes, the logic unit circuit is listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect, otherwise, the logic unit circuit is not listed as a logic unit circuit capable of improving the performance by utilizing the reverse short channel effect;
The second determining unit is specifically configured to:
If the logic unit circuit in the signal path which does not meet the time sequence requirement is the calibrated logic unit circuit in the performance improvement by utilizing the reverse short channel effect, the logic unit circuit is listed as a main delay unit circuit in the performance improvement by utilizing the reverse short channel effect;
if the latch or the trigger in the signal path which does not meet the time sequence requirement is the calibrated logic unit circuit which can utilize the reverse short channel effect to improve the performance, the latch or the trigger is listed as the main delay unit circuit which can utilize the reverse short channel effect to improve the performance.
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| CN102663155A (en) * | 2012-03-09 | 2012-09-12 | 中国科学院微电子研究所 | Method and device for optimizing layout grid length |
| CN108092660A (en) * | 2017-12-29 | 2018-05-29 | 中国科学院微电子研究所 | Sub-threshold circuit optimization method and system |
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| US7441211B1 (en) * | 2005-05-06 | 2008-10-21 | Blaze Dfm, Inc. | Gate-length biasing for digital circuit optimization |
| US7652519B2 (en) * | 2006-06-08 | 2010-01-26 | Telefonaktiebolaget Lm Ericsson (Publ) | Apparatus and method for exploiting reverse short channel effects in transistor devices |
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| CN102663155A (en) * | 2012-03-09 | 2012-09-12 | 中国科学院微电子研究所 | Method and device for optimizing layout grid length |
| CN108092660A (en) * | 2017-12-29 | 2018-05-29 | 中国科学院微电子研究所 | Sub-threshold circuit optimization method and system |
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