CN110956009B - Sub-threshold digital circuit power consumption optimization method and system - Google Patents

Abstract

The present invention discloses a method and system for optimizing power consumption of a subthreshold digital circuit. The method first determines a logic unit circuit that can reduce performance and power consumption; then performs timing analysis on a given integrated circuit to obtain all signal paths with loose timing; then determines a number of main delay units that can reduce performance and power consumption in each signal path with loose timing; finally, according to preset timing constraints, the gate length of the device of the main delay unit is increased or shortened to adjust the device, so as to optimize the power consumption of the subthreshold circuit by adjusting the gate length. The present invention reduces the circuit performance and improves the delay time of the unit by increasing or shortening the gate length of the device of the main delay unit within a reasonable range, thereby reducing the power consumption of the integrated circuit under the premise of meeting the timing requirements. In addition, the power consumption can be reduced and the area can be saved by reducing the gate length. At the same time, the method also improves the optimization speed.

Description

A method and system for optimizing power consumption of subthreshold digital circuits

Technical Field

The present invention relates to the technical field of circuit power consumption optimization, and in particular to a sub-threshold digital circuit power consumption optimization method and system.

Background Art

Subthreshold digital circuits refer to digital logic circuits whose operating voltage is lower than the threshold voltage of transistor devices. Since the circuit operates in the subthreshold region, the dynamic power consumption and static power consumption of the circuit can be greatly reduced. And because the device operates in the subthreshold region, the current and voltage of the device are exponentially related. Changes in device size will lead to significant changes in current and parasitic capacitance, which will significantly change the electrical performance of the circuit. In addition, the circuit performance fluctuates greatly with PVT (Process-Voltage-Temperature) deviations. In order to make the designed subthreshold digital circuit have higher robustness, the statistical analysis and optimization of PVT deviations need to be considered in the design optimization process of subthreshold digital circuits. This will exponentially increase the complexity of device size optimization of subthreshold digital circuits, making the device optimization speed process extremely slow.

At present, with the increase in the scale of subthreshold digital circuits, the statistical analysis and optimization of PVT deviation combined with traditional random optimization algorithms and heuristic optimization algorithms can no longer be directly applied to the optimization of large-scale subthreshold digital circuits, especially the optimization of large-scale subthreshold digital timing circuits. In addition, in order to reduce the power consumption of subthreshold digital circuits, the performance of subthreshold digital circuits can be reduced under the premise of meeting the timing requirements. The traditional method is to reduce the gate width/gate length ratio of the MOS device in the circuit. However, reducing the gate width will cause the discretization of the cell height in the standard cell library used, further causing area waste; and increasing the gate length of the cell working in the subthreshold region may improve the performance of the cell due to the reverse short channel effect, and in the random optimization algorithm, the device size optimization will fall into the local optimum due to the reverse short channel effect. These further increase the complexity of subthreshold circuit design optimization, resulting in excessively long optimization time.

Summary of the invention

The present invention proposes a sub-threshold digital circuit power consumption optimization method and system, which increases or shortens the gate length of the device of the main delay unit within a reasonable range, reduces its circuit performance, improves the delay time of the unit, and reduces the power consumption of the integrated circuit while meeting the timing requirements. In addition, it is also possible to reduce power consumption and save area by reducing the gate length.

To achieve the above object, the present invention provides the following technical solutions:

A method for optimizing power consumption of a subthreshold digital circuit, comprising:

Identify logic cell circuits that can reduce performance and power consumption;

Performing timing analysis on a given integrated circuit to obtain all signal paths with loose timing, wherein the signal paths include: a latch and a front-end combinational logic unit thereof or a trigger and a front-end combinational logic unit thereof;

Determining a number of major delay elements in each of the relaxed timing signal paths that can reduce performance and power consumption;

The gate length of the device of the main delay unit is increased or shortened according to the preset timing constraint condition, so as to optimize the power consumption of the sub-threshold circuit by adjusting the gate length size.

Furthermore, the step of determining a logic unit circuit that can reduce performance and power consumption includes:

Obtaining a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized;

For each of the logic unit circuits, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit under the corresponding gate length, and the gate length-delay data is obtained;

Check the gate length-delay data. If the delay is less than the delay under the original gate length, remove the corresponding gate length-delay data.

If there is gate length-delay data of a delay greater than the delay under the original gate length, the logic unit circuit is listed as a logic unit circuit that can reduce performance and power consumption, otherwise it is a logic unit circuit that cannot reduce performance and power consumption.

Furthermore, it also includes:

For the logic unit circuit capable of reducing performance and power consumption, a delay-gate length relationship query table of the logic unit circuit is established by using the gate length-delay data with a delay greater than the delay under the original gate length.

Furthermore, it also includes:

For the logic unit circuit that can reduce performance and power consumption, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and the power consumption of the logic unit circuit under the delay is obtained at the same time, and the gate length-delay and power consumption data with a delay greater than the delay under the original gate length are used to establish a delay-power consumption relationship query table of the logic unit circuit.

Furthermore, it also includes:

For the logic unit circuit capable of reducing performance and power consumption, the maximum delay of the logic unit circuit under a fixed gate width and the maximum value of the delay amplification factor relative to the original gate length, that is, the performance shrinkage factor of the logic unit circuit, are obtained.

Furthermore, it also includes:

For the logic unit circuit capable of reducing performance and power consumption, based on statistical simulation of the logic unit circuit, a statistical delay-gate length relationship query table is established for the logic unit circuit whose delay is greater than the delay under the original gate length.

Furthermore, the step of performing timing analysis on a given integrated circuit to obtain all signal paths with loose timing includes:

Perform timing analysis on a given integrated circuit using statistical timing analysis tools or based on circuit statistical simulation to obtain the delay distribution of all signal paths;

Determining whether the delay distribution of each of the signal paths satisfies the preset timing constraint condition;

The signal paths that meet the preset timing constraints are listed as signal paths with loose timing.

Furthermore, the step of determining a number of main delay units in each of the signal paths with loose timing that can reduce performance and power consumption includes:

If the logic unit circuit in the timing-relaxed signal path that meets the preset timing constraint condition is a calibrated logic unit circuit that can reduce performance and power consumption, then the logic unit circuit is included in the main delay unit circuit that can reduce performance and power consumption;

If the latch or trigger in the timing-relaxed signal path that does not meet the preset timing constraint condition is a logic unit circuit that has been calibrated to reduce performance and power consumption, it will be included in the main delay unit circuit that can reduce performance and power consumption.

A subthreshold digital circuit power consumption optimization system, comprising:

A first determining unit, used to determine a logic unit circuit that can reduce performance and power consumption;

An analysis unit, used to perform timing analysis on a given integrated circuit to obtain all signal paths with loose timing, wherein the signal paths include: a latch and a front-end combinational logic unit thereof or a trigger and a front-end combinational logic unit thereof;

A second determining unit, configured to determine a number of main delay units in each of the signal paths with loose timing that can reduce performance and power consumption;

The adjustment unit is used to increase or shorten the gate length of the device of the main delay unit according to the preset timing constraint condition, so as to optimize the power consumption of the subthreshold circuit by adjusting the gate length size.

Furthermore, the first determining unit includes:

An acquisition unit, used to acquire a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized;

A processing unit, configured to change the gate length of the MOS device in each logic unit circuit, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data;

A checking unit, used for checking the gate length-delay data, and if the delay is less than the delay under the original gate length, removing the corresponding gate length-delay data;

If there is gate length-delay data of a delay greater than the delay under the original gate length, the logic unit circuit is listed as a logic unit circuit that can reduce performance and power consumption, otherwise it is a logic unit circuit that cannot reduce performance and power consumption.

Through the above technical solutions, it can be known that compared with the prior art, the present invention discloses a method and system for optimizing power consumption of a subthreshold digital circuit, which first determines the logic unit circuit that can reduce performance and power consumption; then performs timing analysis on a given integrated circuit to obtain all signal paths with loose timing; then determines several main delay units that can reduce performance and power consumption in each signal path with loose timing; finally, according to the preset timing constraints, the gate length of the device of the main delay unit is increased or shortened to adjust the device, so as to optimize the power consumption of the subthreshold circuit by adjusting the gate length. The present invention reduces the circuit performance and improves the delay time of the unit by increasing or shortening the gate length of the device of the main delay unit within a reasonable range, thereby reducing the power consumption of the integrated circuit while meeting the timing requirements. In addition, it can also reduce power consumption and save area by reducing the gate length, and the method also improves the optimization speed.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

FIG1 is a flow chart of a method for optimizing power consumption of a subthreshold digital circuit provided by an embodiment of the present invention;

FIG2 is a flowchart of a specific implementation method of step S101 provided in an embodiment of the present invention;

FIG3 is a flowchart of a specific implementation method of step S102 provided in an embodiment of the present invention;

FIG4 is a structural diagram of a sub-threshold digital circuit power consumption optimization system provided by an embodiment of the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

As shown in FIG1 , an embodiment of the present invention provides a method for optimizing power consumption of a sub-threshold digital circuit. The method may specifically include the following steps:

S101. Determine a logic unit circuit that can reduce performance and power consumption.

In an embodiment of the present invention, as shown in FIG. 2 , a specific implementation of the above step S101 is shown. Specifically, the above step of determining the logic unit circuit that can reduce performance and power consumption includes:

S201. Obtain a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized.

S202. For each logic unit circuit, change the gate length of the MOS device in the logic unit circuit, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data.

S203, check the gate length-delay data to determine whether there is a delay less than the delay under the original gate length, if so, execute step S204, if not, execute step S205.

S204, removing the corresponding gate length-delay data.

S205 , classify the logic unit circuit as a logic unit circuit that can reduce performance and power consumption, otherwise it is a logic unit circuit that cannot reduce performance and power consumption.

Further, after determining the logic unit circuit for improving performance, it also includes:

For a logic unit circuit that can reduce performance and power consumption, the above gate length-delay data with a delay greater than the delay under the original gate length is used to establish a delay-gate length relationship query table of the logic unit circuit.

Further, after determining the logic unit circuit for improving performance, it also includes:

For logic unit circuits that can reduce performance and power consumption, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and the power consumption of the logic unit circuit under the delay is obtained at the same time, and the gate length-delay and power consumption data when the delay is greater than the delay under the original gate length are used to establish a delay-power consumption relationship query table for the logic unit circuit.

Further, after determining the logic unit circuit for improving performance, it also includes:

For a logic unit circuit that can reduce performance and power consumption, the maximum delay of the logic unit circuit under a fixed gate width and the maximum value of the delay amplification factor relative to the original gate length, that is, the performance shrinkage factor of the logic unit circuit, are obtained.

Further, after determining the logic unit circuit for improving performance, it also includes:

For logic unit circuits that can reduce performance and power consumption, a statistical delay-gate length relationship query table is established for logic unit circuits with a delay greater than the original gate length based on statistical simulation of the logic unit circuits.

S102, performing timing analysis on a given integrated circuit to obtain all signal paths with loose timing, wherein the signal paths include: a latch and its front-end combinational logic unit or a trigger and its front-end combinational logic unit.

In an embodiment of the present invention, as shown in FIG. 3 , a specific implementation of the above step S102 is shown. Specifically, the above step of performing timing analysis on a given integrated circuit to obtain all signal paths with loose timing includes:

S301, performing timing analysis on a given integrated circuit using a statistical timing analysis tool or based on circuit statistical simulation to obtain delay distributions of all signal paths;

S302: Determine whether the delay distribution of each signal path meets the preset timing constraint condition. If yes, execute step S303; if not, execute step S304.

S303: List the signal paths that meet the preset timing constraint conditions into signal paths with loose timing.

S304: List the signal paths that do not meet the preset timing constraint conditions into signal paths that do not meet the timing looseness.

In the embodiment of the present invention, each latch or trigger and its front-end combinational logic need to meet a preset timing constraint condition, and the preset timing constraint condition is specifically:

t _{Prev_FF-Pdelay,max} +t _{CML-Pdelay,max} +t _FF-setup,max <α.T _clock

t _{Prev_FF-Pdelay,min} +t _{CML-Pdelay,min} >β.t _FF-hold,max

Among them, α is between (0, 1), and the maximum value is generally 0.5; β is between (1, +∞), and the minimum value is generally 1.5. t _{Prev_FF-Pdelay,max} is the maximum value of the output delay time of the previous latch or trigger; t _{CML-Pdelay,max} is the maximum value of the time for the output signal of the front-end combinational logic circuit to reach the latch or trigger; T _clock is the clock signal period of the timing circuit, that is, the inverse value of the clock signal frequency; t _{CML-Pdelay,min} is the minimum value of the time for the output of the front-end combinational logic to reach the latch or trigger; t _{Prev_FF-Pdelay,min} is the minimum value of the data output delay time of the previous latch or trigger; t _FF-hold,max is the maximum data input hold time of the latch or trigger; t _FF-setup,max is the maximum data input setup time of the latch or trigger.

S103 , determining several main delay units in each signal path with loose timing that can reduce performance and power consumption.

In the embodiment of the present invention, specifically, the step of determining a number of main delay units in each of the signal paths with loose timing that can reduce performance and power consumption includes:

If the logic unit circuit in the timing-relaxed signal path that meets the preset timing constraint condition is a logic unit circuit that has been calibrated to reduce performance and power consumption, it is included in the main delay unit circuit that can reduce performance and power consumption;

If the latch or trigger in the timing-relaxed signal path that does not meet the preset timing constraints is a logic unit circuit that has been calibrated to reduce performance and power consumption, it will be included in the main delay unit circuit that can reduce performance and power consumption.

Specifically, for each front-end combinational logic circuit and latch or trigger with loose timing, the results of the units that can reduce performance and power consumption determined in the above steps are used to check the main delay units that can reduce performance and power consumption. If the logic unit in the front-end combinational logic circuit with loose timing is the aforementioned calibrated logic unit that can reduce performance and power consumption, it will be included in the main delay unit that can reduce performance and power consumption, otherwise the logic unit will be excluded from the unit to be optimized; the same process is performed on the latch or trigger circuit.

S104 , increasing or shortening the gate length of the device of the main delay unit according to the preset timing constraint condition, so as to optimize the power consumption of the sub-threshold circuit by adjusting the gate length size.

In the embodiment of the present invention, each latch and its front-end combinational logic unit or trigger and front-end combinational logic circuit must comply with the above-mentioned preset timing constraints, and the preset timing constraints are:

t _{Prev_FF-Pdelay,max} +t _{CML-Pdelay,max} +t _FF-setup,max <α.T _clock

t _{Prev_FF-Pdelay,min} +t _{CML-Pdelay,min} >β.t _FF-hold,max

Among them, α takes values between (0, 1), β takes values between (1, +∞), T _clock is the clock signal period of the sequential circuit, that is, the reciprocal value of the clock signal frequency; t _{Prev_FF-Pdelay,max} is the maximum value of the output delay time of the previous latch or trigger; t _{CML-Pdelay,max} is the maximum value of the time for the output signal of the front-end combinational logic circuit to reach the latch or trigger; T _clock is the clock signal period of the sequential circuit, that is, the reciprocal value of the clock signal frequency; t _{CML-Pdelay,min} is the minimum value of the time for the output of the front-end combinational logic circuit to reach the latch or trigger; t _{Prev_FF-Pdelay,min} is the minimum value of the data output delay time of the previous latch or trigger; t _FF-hold,max is the maximum data input hold time of the latch or trigger; t _FF-setup,max is the maximum data input setup time of the latch or trigger.

In addition, t _{CML-Pdelay,max} and t _{CML-Pdelay,min} are determined by the maximum delay time and minimum delay time of each level of logic gates, respectively, as follows:

t _{CML-Pdelay,max} =∑t _{Cell-Pdelay,max,i}

t _{CML-Pdelay,min} =∑t _{Cell-Pdelay,min,i}

For the latch and its front-end combinational logic unit or the trigger and its front-end combinational logic under the loose book order, the delay space that can be reduced is respectively positioned as:

t _{delay_improve_goal1} = α _s .T _clock -(t _{Prev_FF-Pdelay,max} +t _{CML-Pdelay,max} +t _FF-setup,max )

t _{delay_improve_goal2} = (t _{Prev_FF-Pdelay,min} +t _{CML-Pdelay,min} )-β _s .t _FF-hold,max

Among them, α _s takes a value between (0, 1), and α _s >α; β _s takes a value between (1, +∞), and β _s < β.

Considering that only cells are adjusted to optimize the delay and power consumption of the front-end combinational logic circuit (latches or flip-flops are not adjusted or cannot be adjusted):

∑Δt _{RCSE_Cell-Pdelay,max,i} ≤t _{delay_improve_goal1}

∑Δt _{RCSE_Cell-Pdelay,min,i} ≥t _{delay_improve_goal2}

Furthermore, considering the tuning of cells (including latches or flip-flops) to optimize the delay performance and power consumption of the front-end combinational logic circuit:

∑Δt _{RCSE_Cell-Pdelay,max,i} +Δt _{Prev_FF-Pdelay,max} +Δt _FF-setup,max ≤t _{delay_improve_goal1}

∑Δt _{RCSE_Cell-Pdelay,min,i} -Δt _FF-hold,max +Δt _{Prev_FF-Pdelay,min} ≥t _{delay_improve_goal2}

in:

Δt _{RCSE_Cell-Pdelay,max,i} =t _{RCSE_Cell-Pdelay,max,i,new} -t _{RCSE_Cell-Pdelay,max,I,org}

Δt _{RCSE_Cell-Pdelay,min,i} =t _{RCSE_Cell-Pdelay,min,i,new} -t _{RCSE_Cell-Pdelay,min,i,org}

Δt _{Prev_FF-Pdelay,max} =t _{Prev_FF-Pdelay,max,new} -t _{Prev_FF-Pdelay,max,org}

Δt _{Prev_FF-Pdelay,min} =t _{Prev_FF-Pdelay,min,new} -t _{Prev_FF-Pdelay,min,org}

Δt _FF-setup,max =t _{FF-setup,max,new} -t _{FF-setup,max,org}

Δt _FF-hold,max =t _{FF-hold,max,new} -t _{FF-hold,max,org}

Specifically, t _{RCSE_Cell-Pdelay,max,i,new} is the maximum delay time after the logic cell i adjusts the gate length; t _{RCSE_Cell-Pdelay,max,i,org} is the maximum delay time before the logic cell i adjusts the gate length (i.e., the original gate length); t _{RCSE_Cell-Pdelay,min,i,new} is the minimum delay time after the logic cell i adjusts the gate length; t _{RCSE_Cell-Pdelay,min,i,org} is the minimum delay time before the logic cell i adjusts the gate length (i.e., the original gate length); t _{Prev_FF-Pdelay,max,new} is the maximum delay time after the previous latch or trigger adjusts the gate length; t _{Prev_FF-Pdelay,max,org} is the maximum delay time before the previous latch or trigger adjusts the gate length (i.e., the original gate length); t _{Prev_FF-Pdelay,min,new} is the minimum delay time after the previous latch or trigger adjusts the gate length; t _{Prev_FF-Pdelay,min,org} is the minimum delay time before the previous latch or trigger adjusts the gate length (i.e., the original gate length); t _{FF-setup,max,new} is the maximum setup time of the input data after the latch or trigger adjusts the gate length; t _{FF-setup,max,org} is the maximum setup time of the input data before the latch or trigger adjusts the gate length (i.e., the original gate length); t _{FF-hold,max,new} is the maximum hold time of the input data after the latch or trigger adjusts the gate length; t _{FF-hold,max,org} is the maximum hold time of the input data before the latch or trigger adjusts the gate length (i.e., the original gate length).

For the system of inequalities:

∑Δt _{RCSE_Cell-Pdelay,max,i} ≤t _{delay_improve_goal1}

∑Δt _{RCSE_Cell-Pdelay,min,i} ≥t _{delay_improve_goal2}

or

∑Δt _{RCSE_Cell-Pdelay,max,i} +Δt _FF-setup,max ≤t _{delay_improve_goal1} +Δt _{Prev_FF-Pdelay,max}

∑Δt _{RCSE_Cell-Pdelay,min,i} -Δt _FF-hold,max ≥t _{delay_improve_goal2} -Δt _{Prev_FF-Pdelay,min}

Solve and obtain: the minimum value of Δt _{RCSE_Cell-Pdelay,max,i} of each adjustable logic unit circuit; the maximum value of Δt _{RCSE_Cell-Pdelay,min,i} of each adjustable logic unit; the maximum value of Δt _FF-setup,max of each adjustable latch or trigger; the maximum value of Δt _FF-hold,max of each adjustable latch or trigger;

Further according to the following four formulas:

t _{RCSE_Cell-Pdelay,max,i,new} =t _{RCSE_Cell-Pdelay,max,I,org} +Δt _{RCSE_Cell-Pdelay,max,i}

t _{RCSE_Cell-Pdelay,min,i,new} =t _{RCSE_Cell-Pdelay,min,i,org} +Δt _{RCSE_Cell-Pdelay,min,i}

t _{FF-setup,max,new} =t _{FF-setup,max,org} +Δt _FF-setup,max

t _{FF-hold,max,new} =t _{FF-hold,max,org} +Δt _FF-hold,max

The delay of the cell under the new gate length can be obtained: t _{RCSE_Cell-Pdelay,max,i,new} ; t _{RCSE_Cell-Pdelay,min,i,new} ; t _{FF-setup,max,new} and t _{FF-hold,max,new} .

According to the delay-gate length relationship query table of the unit established above, the gate length of the corresponding adjustable logic unit after adjustment is obtained. Under the new gate length, the delays t _{RCSE_Cell-Pdelay, max, i, new} , t _{RCSE_Cell-Pdelay, min, i, new} , t _{FF-setup, max, new} and t _{FF-hold, max, new of the} unit can make the corresponding front-end combinational logic circuit and latch or trigger meet the timing requirements. At this point, the optimization of timing is achieved by adjusting the gate length size.

Furthermore, when there are multiple gate length values that can meet the timing requirement, the gate length value corresponding to the lowest power consumption is selected as the gate length size of the corresponding unit after adjustment.

Furthermore, when there are multiple gate length values that can meet the timing requirements, the gate length value with the lowest power consumption is selected as the gate length size of the corresponding unit after adjustment under the premise of ensuring the robustness of the performance distribution.

Furthermore, taking the above-adjusted gate length as the initial value, the gate length is fine-tuned through the optimization algorithm, and on the premise of meeting the timing requirements, the unit power consumption is estimated using the gate length-power consumption relationship query table established above, thereby reducing the delay performance and power consumption on the premise of meeting the timing requirements.

Furthermore, based on the sequence of signal flow, the gate length of the devices of the main delay units of the front-end combinational logic circuit and the latch or trigger circuit combination is increased/reduced in turn, thereby reducing the unit circuit performance and power consumption while ensuring that the timing requirements are met.

The embodiment of the present invention discloses a method for optimizing power consumption of a subthreshold digital circuit. The method first determines a logic unit circuit that can reduce performance and power consumption; then performs a timing analysis on a given integrated circuit to obtain all signal paths with loose timing; then determines a number of main delay units that can reduce performance and power consumption in each signal path with loose timing; finally, according to a preset timing constraint, the gate length of the device of the main delay unit is increased or shortened to adjust the device, so as to optimize the power consumption of the subthreshold circuit by adjusting the gate length. The method reduces the circuit performance and improves the delay time of the unit by increasing or shortening the gate length of the device of the main delay unit within a reasonable range, thereby reducing the power consumption of the integrated circuit while meeting the timing requirements. In addition, the power consumption and area saving can be achieved by reducing the gate length.

Please refer to FIG. 4 . Based on the sub-threshold digital circuit power optimization method disclosed in the above embodiment, this embodiment correspondingly discloses a sub-threshold digital circuit power consumption optimization system, which specifically includes: a first determination unit 401, an analysis unit 402, a second determination unit 403 and an adjustment unit 404, wherein:

A first determining unit 401 is used to determine a logic unit circuit that can reduce performance and power consumption;

An analysis unit 402 is used to perform timing analysis on a given integrated circuit to obtain all signal paths with loose timing, wherein the signal paths include: a latch and its front-end combinational logic unit or a trigger and its front-end combinational logic unit;

A second determining unit 403, configured to determine a number of main delay units in each timing-relaxed signal path that can reduce performance and power consumption;

The adjusting unit 404 is used to adjust the device of the main delay unit by increasing or shortening its gate length according to the preset timing constraint condition, so as to optimize the power consumption of the sub-threshold circuit by adjusting the gate length size.

Furthermore, the first determining unit 401 includes: an acquiring unit 4011, a processing unit 4012 and a checking unit 4013, wherein:

An acquisition unit 4011 is used to acquire a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized;

The processing unit 4012 is used to change the gate length of the MOS device in each logic unit circuit, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data;

The checking unit 4013 is used to check the gate length-delay data, and if the delay is less than the delay under the original gate length, the corresponding gate length-delay data is removed;

If there is gate length-delay data of a delay greater than the delay under the original gate length, the logic unit circuit is listed as a logic unit circuit that can reduce performance and power consumption, otherwise it is a logic unit circuit that cannot reduce performance and power consumption.

The embodiment of the present invention discloses a subthreshold digital circuit power consumption optimization system, which first determines the logic unit circuit that can reduce performance and power consumption through a first determination unit; then performs timing analysis on a given integrated circuit through an analysis unit to obtain all signal paths with loose timing; then determines several main delay units that can reduce performance and power consumption in each signal path with loose timing through a second determination unit; finally, adjusts the device of the main delay unit by increasing or shortening its gate length according to preset timing constraints through an adjustment unit, so as to optimize the power consumption of the subthreshold circuit by adjusting the gate length size. This system reduces the circuit performance and improves the delay time of the unit by increasing or shortening the gate length of the device of the main delay unit within a reasonable range, thereby reducing the power consumption of the integrated circuit while meeting the timing requirements. In addition, it can also reduce power consumption and save area by reducing the gate length.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A method for optimizing power consumption of a subthreshold digital circuit, comprising: Identify logic cell circuits that can reduce performance and power consumption; Performing timing analysis on a given integrated circuit to obtain all signal paths with loose timing, wherein the signal paths include: a latch and a front-end combinational logic unit thereof or a trigger and a front-end combinational logic unit thereof; Determining a number of major delay elements in each of the relaxed timing signal paths that can reduce performance and power consumption; According to the preset timing constraint condition, the gate length of the device of the main delay unit is increased or shortened to adjust the power consumption of the subthreshold circuit by adjusting the gate length size; The step of determining a logic unit circuit that can reduce performance and power consumption includes: Obtaining a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized; For each of the logic unit circuits, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the logic unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit under the corresponding gate length, and the gate length-delay data is obtained; Check the gate length-delay data. If the delay is less than the delay under the original gate length, remove the corresponding gate length-delay data. If there is gate length-delay data of a delay greater than the delay under the original gate length, the logic unit circuit is listed as a logic unit circuit that can reduce performance and power consumption, otherwise it is a logic unit circuit that cannot reduce performance and power consumption; The step of determining a number of main delay units in each of the signal paths with loose timing that can reduce performance and power consumption includes: If the logic unit circuit in the timing-relaxed signal path that meets the preset timing constraint condition is a logic unit circuit that has been calibrated to reduce performance and power consumption, then the logic unit circuit is included in the main delay unit circuit that can reduce performance and power consumption; If the latch or trigger in the timing-relaxed signal path that does not meet the preset timing constraint condition is a logic unit circuit that has been calibrated to reduce performance and power consumption, it will be included in the main delay unit circuit that can reduce performance and power consumption. 2. The method according to claim 1, further comprising: For the logic unit circuit capable of reducing performance and power consumption, a delay-gate length relationship query table of the logic unit circuit is established by using the gate length-delay data with a delay greater than the delay under the original gate length. 3. The method according to claim 1, further comprising: For the logic unit circuit that can reduce performance and power consumption, the gate length of the MOS device in the logic unit circuit is changed, the input-output waveform of the unit circuit under the corresponding gate length is obtained by simulating the logic unit circuit, the input-output waveform of the logic unit circuit is measured to obtain the delay of the logic unit circuit, and the power consumption of the logic unit circuit under the delay is obtained at the same time, and the gate length-delay and power consumption data when the delay is greater than the delay under the original gate length are used to establish a delay-power consumption relationship query table of the logic unit circuit. 4. The method according to claim 1, further comprising: For the logic unit circuit capable of reducing performance and power consumption, the maximum delay of the logic unit circuit under a fixed gate width and the maximum value of the delay amplification factor relative to the original gate length, that is, the performance shrinkage factor of the logic unit circuit, are obtained. 5. The method according to claim 1, further comprising: For the logic unit circuit capable of reducing performance and power consumption, based on statistical simulation of the logic unit circuit, a statistical delay-gate length relationship query table is established for the logic unit circuit whose delay is greater than the delay under the original gate length. 6. The method according to claim 1, wherein the step of performing timing analysis on a given integrated circuit to obtain all signal paths with loose timing comprises: Perform timing analysis on a given integrated circuit using statistical timing analysis tools or based on circuit statistical simulation to obtain the delay distribution of all signal paths; Determining whether the delay distribution of each of the signal paths satisfies the preset timing constraint condition; The signal paths that meet the preset timing constraints are listed as signal paths with loose timing. 7. A subthreshold digital circuit power consumption optimization system, comprising: A first determining unit, used to determine a logic unit circuit that can reduce performance and power consumption; An analysis unit, used to perform timing analysis on a given integrated circuit to obtain all signal paths with loose timing, wherein the signal paths include: a latch and a front-end combinational logic unit thereof or a trigger and a front-end combinational logic unit thereof; A second determining unit, configured to determine a number of main delay units in each of the signal paths with loose timing that can reduce performance and power consumption; An adjustment unit, used to increase or shorten the gate length of the device of the main delay unit according to a preset timing constraint condition, so as to optimize the power consumption of the subthreshold circuit by adjusting the gate length size; The first determining unit includes: An acquisition unit, used to acquire a logic unit circuit in a used logic unit library or a logic unit circuit referenced in a design to be optimized; A processing unit, configured to change the gate length of the MOS device in each of the logic unit circuits, obtain the input-output waveform of the logic unit circuit under the corresponding gate length by simulating the logic unit circuit, measure the input-output waveform of the logic unit circuit to obtain the delay of the logic unit circuit under the corresponding gate length, and obtain gate length-delay data; A checking unit, used for checking the gate length-delay data, and if the delay is less than the delay under the original gate length, the corresponding gate length-delay data is removed; If there is gate length-delay data of a delay greater than the delay under the original gate length, the logic unit circuit is listed as a logic unit circuit that can reduce performance and power consumption, otherwise it is a logic unit circuit that cannot reduce performance and power consumption; The second determining unit determines a number of main delay units in each of the signal paths with loose timing that can reduce performance and power consumption, including: If the logic unit circuit in the timing-relaxed signal path that meets the preset timing constraint condition is a logic unit circuit that has been calibrated to reduce performance and power consumption, then it is included in the main delay unit circuit that can reduce performance and power consumption; If the latch or trigger in the timing-relaxed signal path that does not meet the preset timing constraint condition is a logic unit circuit that has been calibrated to reduce performance and power consumption, it will be included in the main delay unit circuit that can reduce performance and power consumption.