CN111383994B - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and its forming method, the forming method comprising: providing a base, including a peripheral area for forming an input/output device and a core area for forming a core device, the base includes a substrate, a fin protruding from the substrate , and a plurality of channel stacks sequentially located on the fin, each channel stack includes a sacrificial layer and a channel layer located on the sacrificial layer; an isolation film is formed on the substrate where the channel stack is exposed; and the peripheral A region channel stack, forming an opening in the isolation film; forming a fin material layer of the same material as the fin in the opening, the fin material layer and the fin at the bottom of the fin material layer as a peripheral region fin structure; forming the fin After the internal structure is formed, the isolation film is etched, and the remaining isolation film after etching is used as an isolation layer. The isolation layer in the core area exposes the channel stack in the core area, and the isolation layer in the peripheral area covers part of the side wall of the fin structure. The embodiments of the present invention are beneficial to simplify the process flow, reduce the process cost, and improve the electrical performance of the semiconductor structure.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the gradual development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors is also continuously shortened accordingly. However, with the shortening of the channel length of the device, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage also decreases. The larger and larger the subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) is more likely to occur.

Therefore, in order to better meet the requirements of scaling down the device size, the semiconductor process has gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field-Effect Transistors (FinFETs). , Gate-all-around (GAA) transistor. The gate of the FinFET can control the ultra-thin body (fin) from at least two sides, so the control ability of the channel is stronger, and the short channel effect can be well suppressed. Compared with other devices, the FinFET is different from the existing Integrated circuit manufacturing has better compatibility; the fully surrounded gate transistor gate surrounds the area where the channel is located from all sides, which can further enhance the control ability of the gate to the channel, and the effect of suppressing the short channel effect is more significant.

In addition, MOSFET field effect transistors are mainly divided into core (Core) devices and input/output (I/O) devices according to their functions. Typically, input/output devices operate at much higher voltages than core devices. In order to prevent problems such as electrical breakdown, when the operating voltage of the device is greater, the thickness of the gate dielectric layer of the device is required to be thicker. Therefore, the thickness of the gate dielectric layer of the input/output device is usually greater than the thickness of the gate dielectric layer of the core device. .

Contents of the invention

The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a peripheral region for forming an input/output device and a core region for forming a core device, and the substrate includes a substrate, a fin protruding from the substrate, and a plurality of channel stacks sequentially located on the fin, each channel stack including a sacrificial layer and a channel layer located on the sacrificial layer forming an isolation film on the substrate where the channel stack is exposed; removing the channel stack in the peripheral region to form an opening in the isolation film; forming a fin material layer in the opening, the The fin material layer is made of the same material as the fin, and the fin material layer and the fin at the bottom of the fin material layer are used as the fin structure in the peripheral region; after forming the fin structure in the peripheral region, etching the isolation film, the remaining isolation film after etching is used as an isolation layer, the isolation layer in the core area exposes the channel stack in the core area, and the isolation layer in the peripheral area covers part of the sidewall of the fin structure.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate, including a peripheral region for forming an input/output device and a core region for forming a core device; a fin protruding from the surface of the substrate a channel structure layer located on the fin of the core region and spaced apart from the fin, the channel structure layer comprising a plurality of channel layers arranged at intervals; a fin material layer located in the peripheral region On the fin part, the material layer of the fin part and the material of the fin part are the same, the material layer of the fin part and the fin part at the bottom of the material layer of the fin part constitute the fin part structure; the isolation layer is located in the channel structure layer On the substrate where the fin structure is exposed, the isolation layer in the core area exposes the space between the fin in the core area and the channel structure layer, and the isolation layer in the peripheral area covers part of the fin structure.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the field of semiconductors, the thickness of the gate dielectric layer in the peripheral region is usually greater than the thickness of the gate dielectric layer in the core region by making the thickness of the gate oxide layer in the peripheral region greater than the thickness of the gate oxide layer in the core region, and both the peripheral region and the core region use a channel Compared with the stacking scheme, in the embodiment of the present invention, the peripheral region adopts a fin structure, and the core region adopts a channel stack structure. Therefore, the gates of the peripheral region and the core region can be formed in different process steps later. oxide layer, avoiding the step of removing part of the thickness of the gate oxide layer in the core region, so that the steps of forming the gate oxide layer in the peripheral region and the core region will not affect each other, thereby simplifying the process flow and reducing the difficulty of the process. It is beneficial to reduce the process cost; in addition, the material of the gate oxide layer is usually the same as that of the isolation layer, avoiding the step of removing the gate oxide layer with a partial thickness of the core region, thereby avoiding the problem of loss of the isolation layer in this step, which is beneficial The possibility of increasing the surface area of the fin exposed by the isolation layer in the core area is reduced, the surface area of the fin of the parasitic device is reduced, and the electrical performance of the semiconductor structure is improved.

In an optional solution, after forming the isolation film and before forming the isolation layer, the forming method further includes: forming an etching stop layer in the isolation film in the peripheral region, the bottom of the etching stop layer is higher than the The top of the fin in the core area, the top of the etching stop layer can play a role in defining the etching stop position in the step of etching the isolation film, so that the top of the isolation layer in the peripheral area is higher than the top of the isolation film The top of the isolation layer in the core area, so while exposing the isolation layer to the channel stack in the core area, the height of the peripheral area fin structure exposed by the isolation layer is small, reducing the peripheral area fin structure The surface area exposed to the isolation layer is beneficial to reduce the parasitic capacitance on the fin structure in the peripheral area, and optimizes the electrical performance of the input/output device.

Description of drawings

1 to 8 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure;

9 to 20 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Detailed ways

Currently formed devices still suffer from poor performance. The reasons for the poor performance of the device are analyzed in conjunction with a method of forming a semiconductor structure.

Referring to FIG. 1 to FIG. 8 , schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure are shown.

Referring to FIG. 1 , a base is provided, the base includes a peripheral area I for forming input/output devices and a core area II for forming core devices, the base includes a substrate 1, protruding from the substrate 1 The fin 2 , and a plurality of channel stacks 3 sequentially located on the fin 2 , each channel stack 3 includes a sacrificial layer 4 and a channel layer 5 located on the sacrificial layer 4 .

Referring to FIG. 2 , an isolation layer 6 is formed on the substrate 1 where the channel stack 3 is exposed, and the isolation layer 6 exposes the channel stack 3 in the peripheral region I and the core region II.

Referring to FIG. 3, a dummy gate structure 9 is formed across the channel stack 3, the dummy gate structure 9 covers part of the top and part of the sidewall of the channel stack 3, and the dummy gate structure 9 includes a dummy A gate oxide layer 7 and a dummy gate layer 8 covering the dummy gate oxide layer 7 .

Referring to FIG. 4 , a dielectric layer 10 is formed on the substrate 1 exposed by the dummy gate structure 9 .

Referring to Fig. 5, the dummy gate structure 9 is removed, and a first opening 11 and a second opening 12 are respectively formed in the dielectric layer 10 of the peripheral region I and the core region II.

Referring to FIG. 6 , the sacrificial layer 4 in the peripheral region I and the core region II is removed, and a plurality of channel layers 5 arranged at intervals on the fin portion 2 serve as a channel structure layer (not shown).

Referring to FIG. 7 , a gate oxide layer 13 is formed on the surface of the channel layer 5 exposed by the first opening 11 and the second opening 12 .

Referring to FIG. 8 , a protection layer 14 is formed in the first opening 11 ; after the formation of the protection layer 14 , a part of the thickness of the gate oxide layer 13 exposed by the second opening 12 is removed.

In the semiconductor field, the thickness of the gate dielectric layer 13 in the peripheral region I is usually greater than the thickness of the gate oxide layer 13 in the core region II so that the thickness of the gate dielectric layer in the peripheral region I is greater than the thickness of the gate dielectric layer in the core region II. In the forming method, both the peripheral region I and the core region II adopt the structure of the channel stack 3, after removing the dummy gate oxide layer 7 and the sacrificial layer 4 of the peripheral region I and the core region II, in order to make the core The thickness of the gate oxide layer 13 in the region II is smaller than the thickness of the gate oxide layer 13 in the peripheral region I. It is necessary to form a thicker gate oxide layer 13 in the same step, and then remove the gate oxide layer 13 with a partial thickness in the core region II. The gate oxide layer 13 adjacent to the channel layer 5 is difficult to remove, the process flow is complicated, the process is difficult, and it is easy to increase the process cost.

Moreover, in the field of semiconductors, the gate oxide layer 13 is usually made of the same material as the isolation layer 6, and the isolation layer 6 is likely to be lost during the step of removing the part-thick gate oxide layer 13 exposed by the second opening 12, Thereby it is easy to increase the height of the fins 2 exposed by the isolation layer 6 of the core region II, so that the surface area of the fins 2 exposed by the isolation layer 6 of the core region II is larger, which increases the surface area of the fins of the parasitic device, thereby easily affecting the electrical properties of the semiconductor structure. Performance has adverse effects, such as increasing parasitic capacitance, leakage current, etc.

In order to solve the above technical problems, the fin material layer and the fin at the bottom of the fin material layer in the embodiment of the present invention are used as the fin structure in the peripheral region, compared with the solution in which both the peripheral region and the core region use channel stacking In the embodiment of the present invention, the peripheral region adopts a fin structure, and the core region adopts a channel stack structure. Therefore, the gate oxide layers of the peripheral region and the core region can be formed in different process steps later, avoiding removal The step of forming the gate oxide layer with a partial thickness in the core region prevents the formation steps of the gate oxide layer in the peripheral region and the core region from interfering with each other, thereby simplifying the process flow, reducing process difficulty, and helping to reduce process cost; in addition , in the field of semiconductors, the material of the gate oxide layer is usually the same as that of the isolation layer, avoiding the step of removing part of the thickness of the gate oxide layer in the core region, thereby avoiding the problem of loss of the isolation layer in this step, which is beneficial to reduce The possibility of increasing the surface area of the fin exposed by the isolation layer in the core area reduces the surface area of the fin of the parasitic device and improves the electrical performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

9 to 20 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIGS. 9 to 10, a base is provided, the base includes a peripheral region I for forming an input/output device and a core region II for forming a core device, the base includes a substrate 100 (as shown in FIG. 10 ) , a fin 110 protruding from the substrate 100 (as shown in FIG. 10 ), and a plurality of channel stacks 103 (as shown in FIG. 10 ) sequentially located on the fin 110 , each channel The stack 103 includes a sacrificial layer 101 (as shown in FIG. 10 ) and a channel layer 102 on the sacrificial layer 101 (as shown in FIG. 10 ).

The substrate 100 is used to provide a process platform for subsequent formation of gate-all-around (Gate-all-around, GAA) transistors in the core region I and fin field effect transistors (FinFETs) in the peripheral region I.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a silicon-on-insulator substrate. Other types of substrates such as germanium substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

The fin portion 110 exposes part of the substrate 100 , thereby providing a process basis for subsequent formation of an isolation layer on the substrate 100 . In this embodiment, the fin portion 110 and the substrate 100 are obtained by etching the same semiconductor material layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

Therefore, in this embodiment, the material of the fin portion 110 is the same as that of the substrate 100 , and the material of the fin portion 110 is silicon. In other embodiments, the material of the fins can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, which are suitable for forming fins, and the fins can also be combined with the The material of the substrate is different.

The channel stack 103 is used to provide a process basis for the subsequent formation of the channel layer 102 with suspended spaces. Specifically, the sacrificial layer 101 is used to support the channel layer 102 and at the same time occupy a space for the subsequent formation of the metal gate structure, and the channel layer 102 is used to provide a channel fully surrounding the gate transistor.

In this embodiment, the material of the channel layer 102 is Si, and the material of the sacrificial layer 101 is SiGe. In other embodiments, when the formed all-enclosed gate transistor is a PMOS transistor, in order to improve the performance of the PMOS transistor, SiGe channel technology may be used. Correspondingly, the materials of the fin and the channel layer are both SiGe, The material of the sacrificial layer is Si.

In this embodiment, two channel stack layers 103 are formed on the fin portion 110 , that is, two sacrificial layers 101 and two channel layers 102 are formed alternately on the fin portion 110 . In other embodiments, according to actual process requirements, the number of the channel stacks is not limited to two.

It should be noted that, in this embodiment, a fin mask layer 104 is also formed on the top of the channel stack 103, and the fin mask layer 104 is used as a base for forming the substrate 100 and the fin 110. An etching mask, the fin mask layer 104 is also used to protect the top of the channel stack 103 in the subsequent process. In this embodiment, the material of the fin mask layer 104 is silicon nitride.

Specifically, referring to FIG. 9 , the step of forming the substrate 100, the fin 110 and the channel stack 103 includes: providing a semiconductor material layer 100a; forming at least two channel material stacks on the semiconductor material layer 100a; Layer 103a, the channel material stack 103a includes a sacrificial material layer 101a and a channel material layer 102a located on the sacrificial material layer 101a; patterning the channel material stack 103a and the semiconductor material layer 100a forms a lining The bottom 100 , the fin 110 protruding from the surface of the substrate 100 , and the channel stack 103 on the fin 110 .

In this embodiment, the number of the channel stacks 103 is two, and the number of the channel material stacks 103a is correspondingly two.

In this embodiment, the channel material stack 103a is formed on the semiconductor material layer 100a by epitaxial growth, so the formation quality of the sacrificial material layer 101a and the channel material layer 102a is better, and the sacrificial material layer 102a The quality of the layer 101 and the channel layer 102 is correspondingly good, and the channel formed to fully surround the gate transistor is located in high-quality materials, which is conducive to improving device performance.

It should be noted that, in this embodiment, a fin mask material layer 104a is formed on the top of the channel material stack 103a, and the fin mask material layer 104a is used to form the fin mask layer 104. . Correspondingly, before patterning the channel material stack 103 a and the semiconductor material layer 100 a , it further includes: patterning the fin mask material layer 104 a to form the fin mask layer 104 .

Referring to FIG. 11 , an isolation film 105 is formed on the substrate 100 where the channel stack 103 is exposed. Specifically, the isolation film 105 covers the sidewalls of the fin portion 110 and the channel stack 103 .

The isolation film 105 is used to subsequently form an isolation layer, thereby realizing electrical insulation between adjacent devices.

In this embodiment, the material of the isolation film 105 is silicon oxide, which is beneficial to reduce the process difficulty and cost of forming the isolation film 105 and improve the function of subsequent isolation layers for isolating adjacent devices. In other embodiments, the material of the isolation film may also be other insulating materials such as silicon nitride and silicon oxynitride.

Specifically, the step of forming the isolation film 105 includes: forming an initial isolation film (not shown in the figure) on the substrate 100 exposed by the fin portion 110, the initial isolation film covering the top of the channel stack 103; The top of the initial isolation film is planarized to form the isolation film 105 .

In this embodiment, the initial isolation film is formed by using a flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process, which is beneficial to reduce the probability of forming defects such as cavities in the initial isolation film, and correspondingly helps to improve the isolation. The film-forming quality of the film 105.

In this embodiment, the chemical-mechanical polishing (CMP) process is used to planarize the initial isolation film, which is conducive to improving the flatness of the top surface of the isolation film 105, and correspondingly helps to improve the subsequent isolation layer. formation quality.

In this embodiment, in order to reduce the process difficulty of forming the isolation film 105 , the top of the isolation film 105 is flush with the top of the fin mask layer 104 . In other embodiments, the top of the isolation film may also be lower than the top of the fin mask layer.

Referring to FIGS. 12 to 13 , the channel stack 103 in the peripheral region I is removed, and an opening 300 is formed in the isolation film 105 (as shown in FIG. 13 ).

By forming the opening 300 , a spatial location is provided for the subsequent formation of a fin material layer in the opening 300 , thereby forming the fin structure of the peripheral region I.

Specifically, the step of forming the opening 300 includes: forming a first mask layer 108 (as shown in FIG. 13 ) covering the channel stack 103 and the isolation film 105 of the core region II; The film layer 108 is a mask, and the channel stack 103 in the peripheral region I is removed to form an opening 300 in the isolation film 105 .

In this embodiment, the material of the first mask layer 108 is photoresist.

In this embodiment, a dry etching process is used to remove the channel stack 103 in the peripheral region I.

The dry etching process has good controllability of the etching profile, which is conducive to making the shape of the opening 300 meet the process requirements, thereby improving the formation quality of the subsequent fin material layer.

It should be noted that, in this embodiment, a fin mask layer 104 is formed on the top of the channel stack 103, therefore, before removing the channel stack 103 in the peripheral region 1, the peripheral region 1 is also removed. The fin mask layer 104 of I.

In an actual process, in order to ensure that the channel stack 103 in the peripheral region I can be completely removed, the channel stack 103 in the peripheral region I is usually over-etched. Therefore, in this embodiment, the removal of the After the channel stack 103 in the peripheral region I, part of the fins 110 in the peripheral region I will be etched.

With reference to FIG. 12 , it should be noted that, in this embodiment, after forming the isolation film 105 and before etching the isolation film 105 to form an isolation layer, the forming method further includes: An etch stop layer 106 is formed in 105 , the bottom of the etch stop layer 106 is higher than the top of the fin portion 110 .

The subsequent process also includes: removing the channel stack 103 in the peripheral region I, and forming a fin structure in the peripheral region I. Since the channel layers 102 in the core region II and the sacrificial layers 101 are alternately arranged at intervals, in the peripheral region I In the case where the top of the fin structure is flush with the top of the channel stack, the fin structure in the peripheral region I can use more material for the channel. By forming an etch stop layer 106 in the isolation film 105 of the peripheral region I, the isolation film 105 can be etched subsequently using the top of the etch stop layer 106 as a stop position to form isolation between the peripheral region I and the core region II. layer, and the top of the isolation layer in the peripheral region I is higher than the top of the isolation layer in the core region II, so that while the isolation layer exposes the channel stack in the core region II, the fin structure in the peripheral region I exposed by the isolation layer The height is small, which is beneficial to reduce the parasitic capacitance on the fin structure in the peripheral region I, and optimizes the electrical performance of the input/output device.

In this embodiment, the step of forming the etching stop layer 106 includes: before forming the opening 300, forming a second mask layer 107 covering the channel stack 103 and the isolation film 105 of the core region II; The second mask layer 107 is a mask, and ion implantation 200 is performed to form an etching stop layer 106 , the bottom of the etching stop layer 106 is higher than the top of the fin portion 110 .

In this embodiment, before forming the opening 300, the etching stop layer 106 is formed, compared with the solution of forming the etching stop layer after forming the opening and forming the fin material layer in the opening, it is beneficial The ion implantation process for forming the etching stop layer is prevented from causing damage to the fin structure in the peripheral region, and the electrical performance of the input/output device is optimized.

In other embodiments, according to actual process requirements, the etching stop layer may also be formed after forming the fin structure.

It should be noted that, in this embodiment, the opening 300 is formed after the etching stop layer 106 is formed. Therefore, after the etching stop layer 106 is formed, the second mask layer 107 can be reserved as an etching mask for removing the I-channel stack 103 in the peripheral region. Correspondingly, in this embodiment, the first mask layer 108 and the second mask layer 107 are the same mask layer.

In other embodiments, according to actual process requirements, different mask layers may be formed in the steps of forming the opening and the etching stop layer.

Specifically, the etching stop layer 106 is formed by implanting silicon ions into the isolation film 105 of the peripheral region I.

The material of the isolation film 105 is silicon oxide, and the material of the etching stop layer 106 is silicon oxide doped with silicon ions.

The silicon oxide material doped with silicon ions has higher hardness, and the etching selectivity of silicon oxide and silicon is relatively large. By implanting silicon ions into the isolation film 105, it is beneficial to improve the isolation film 105 and the etching stop. The etch selectivity of the layer 106, so that the top of the etch stop layer 106 can play a role in defining the etch stop position.

It should be noted that, in this embodiment, the implantation energy of silicon ions should not be too small, nor should it be too large. If the implantation energy of silicon ions is too small, it will be difficult to implant silicon ions into the isolation film 105, and the implantation depth of the silicon ions is likely to be insufficient, which will cause the top of the etch stop layer 106 to separate from the channel. The distance at the top of the stack 103 is too small, and after the isolation film 105 is etched to form an isolation layer with the top of the etching stop layer 106 as the etching stop position, the height of the fin structure exposed by the isolation layer in the peripheral region I is If it is too small, it is easy to cause adverse effects on the electrical properties such as the carrier mobility of the input/output device; if the implantation energy of silicon ions is too large, it is easy to cause the implantation depth of the silicon ions to be too deep, thus easily causing the inscription. The distance between the top of the etch stop layer 106 and the top of the channel stack 103 is too large. After the subsequent formation of the isolation layer, the height of the fin structure exposed by the isolation layer in the peripheral region I is too large, which will easily lead to parasitic capacitance of the input/output device. Larger, reducing the electrical performance of the input/output device. Therefore, in this embodiment, the implantation energy of silicon ions is 1.0 keV to 20.0 keV.

It should also be noted that, in this embodiment, the implantation dose of silicon ions should not be too small, nor should it be too large. If the implant dose is too small, it will easily lead to low silicon content in the etch stop layer 106, and the effect of increasing the etch selectivity ratio of the etch stop layer 106 and the isolation film 105 is not significant, thereby easily reducing the silicon content of the etch stop layer 106. The top of the etch stop layer 106 is used to define the effect of the etch stop position; if the implantation dose is too large, it is easy to cause the doping concentration of silicon ions in the etch stop layer 106 to be relatively high, and then it is easy to increase the amount of the etch stop layer. The probability of problems such as leakage current in 106. Therefore, in this embodiment, the silicon ion implantation dose is 5.0e12 atoms per square centimeter to 1.0e16 atoms per square centimeter.

In addition, in order to ensure that silicon ions can be implanted into the predetermined area of the peripheral region I and avoid implanting silicon ions into the core region II, in this embodiment, the implantation angle of silicon ions is 0° to 5°. Wherein, the implantation angle refers to the included angle between the implantation direction and the surface normal of the substrate 100 .

In this embodiment, the role of the top of the etching stop layer 106 in defining the etching stop position is more significant by properly setting the implantation energy, implantation dose, and implantation angle of silicon ions and using them in combination.

Moreover, the thickness of the etch stop layer 106 can meet the process requirements by setting the implant energy, implant dose, implant angle and other parameters reasonably. Therefore, in this embodiment, the thickness of the etching stop layer 106 should neither be too small nor too large. If the thickness of the etching stop layer 106 is too small, it is easy to reduce the role of the subsequent etching stop layer 106 top for defining the etching stop position; if the thickness of the etching stop layer 106 is too large, it is easy to cause subsequent The height of the fin structure exposed by the isolation layer in the peripheral region I is too small, and the performance of the formed input/output device is not good. Therefore, in this embodiment, the thickness of the etching stop layer 106 is 2 nm to 4 nm.

Referring to FIG. 14 , a fin material layer 115 is formed in the opening 300 (as shown in FIG. 13 ), the fin material layer 115 is made of the same material as the fin 110, and the fin material layer 115 and the fin The fin 110 at the bottom of the material layer 115 is used as the fin structure 120 in the peripheral region I.

In the field of semiconductors, the thickness of the gate dielectric layer in the peripheral region is usually greater than the thickness of the gate dielectric layer in the core region by making the thickness of the gate oxide layer in the peripheral region greater than the thickness of the gate oxide layer in the core region, and both the peripheral region and the core region use a channel Compared with the stacking scheme, in the embodiment of the present invention, the peripheral region I adopts the fin structure 120, and the core region II adopts the channel stack 103, and the peripheral region I and the core region can be formed in different process steps later. The gate oxide layer of II avoids the step of removing part of the thickness of the gate oxide layer in the core region, so that the formation steps of the gate oxide layer in the peripheral region I and core region II will not affect each other, thereby simplifying the process flow and reducing the cost of the gate oxide layer. process difficulty, and help to reduce process cost; in addition, the gate oxide layer is generally the same material as the isolation layer, avoiding the step of removing part of the thickness of the gate oxide layer in the core region, thereby avoiding the loss of the isolation layer in this step The problem is that it is beneficial to reduce the possibility of increasing the surface area of the fin 110 exposed by the isolation layer of the core region II, reduce the surface area of the fin of the parasitic device, and improve the electrical performance of the semiconductor structure.

In this embodiment, the material of the fin material layer 115 is the same as that of the fin 110 , and the material of the fin material layer 115 is also Si. By making the material of the fin material layer 115 and the fin portion 110 the same, the fin material layer 115 and the fin portion 110 at the bottom of the fin material layer 115 constitute the peripheral region I fin structure 120, thereby providing input/ channel of the output device.

In this embodiment, the fin material layer 115 is formed in the opening 300 by adopting an epitaxial growth process, which is beneficial to improving the formation quality of the fin material layer 115 and correspondingly improving the quality of the fin structure 120 in the peripheral region I. The quality of the formation optimizes the electrical performance of the input/output device.

In this embodiment, in the step of forming the fin material layer 115, the top of the fin material layer 115 is flush with the top of the channel stack 103, which is beneficial to improve process compatibility and reduce differences in semiconductor structures. (variability) the probability of the problem.

Referring to FIG. 13 , in this embodiment, after forming the opening 300 and before forming the fin structure 120 , the forming method further includes: removing the first mask layer 108 .

In this embodiment, the material of the first mask layer 108 is photoresist, so the first mask layer 108 is removed by a wet stripping process or a dry etching process.

In other embodiments, according to actual process requirements, the first mask layer may be removed after the fin structure is formed.

Referring to FIG. 15, after forming the fin structure 120 in the peripheral region I, the isolation film 105 (as shown in FIG. 14 ) is etched, and the remaining isolation film 105 after etching is used as the isolation layer 130. The isolation of the core region II The layer 130b exposes the channel stack 103 of the core region II, and the isolation layer 130a of the peripheral region I covers part of the sidewall of the fin structure 120 .

Since the channel layers 102 of the core region II and the sacrificial layers 101 are alternately arranged at intervals, when the top of the fin structure 120 is flush with the top of the channel stack 103, the peripheral region The fin structure 120 of I has more material that can be used as a channel. In this embodiment, the isolation film 105 is etched with the top of the etching stop layer 106 as the stop position, so that the top of the isolation layer 130a in the peripheral region I is higher than the top of the isolation layer 130b in the core region II, so While the isolation layer 130 exposes the channel stack 103 in the core region II, the height of the fin structure 120 in the peripheral region I exposed by the isolation layer 130 is relatively small, thereby helping to reduce the height of the fin structure 120 in the peripheral region I. parasitic capacitance, optimizing the electrical performance of the input/output device.

In this embodiment, a dry etching process is used to etch the isolation film 105 . The dry etching process has better controllability of the etching profile, which is beneficial to improving the formation quality of the isolation layer 130 .

Referring to FIG. 16 to FIG. 19, after forming the isolation layer 130, it further includes: forming a first gate oxide layer 135, the first gate oxide layer 135 covering the surface of the fin structure 120 exposed by the isolation layer 130; forming a second gate oxide layer 135; Two gate oxide layers 141 , the second gate oxide layer 141 is located on the surface of the channel layer 102 , and the thickness of the second gate oxide layer 141 is smaller than the thickness of the first gate oxide layer 135 .

By making the thickness of the second gate oxide layer 141 smaller than the thickness of the first gate oxide layer 135 , the thickness of the gate dielectric layer of the input/output device is increased, which is beneficial to improve the breakdown voltage of the input/output device.

In the embodiment of the present invention, the gate oxide layer of the peripheral region I and the core region II is formed in different process steps, avoiding the step of removing the gate oxide layer with a partial thickness of the core region, and making the gate oxide layer of the peripheral region I and the core region II The formation steps of the oxide layer will not affect each other, thereby simplifying the process flow, reducing the difficulty of the process, and helping to reduce the cost of the process; in addition, the material of the gate oxide layer is usually the same as that of the isolation layer, and it is avoided to remove part of the thickness of the core region. gate oxide layer, thereby avoiding the problem of loss of the isolation layer in this step, thereby helping to reduce the probability of increasing the surface area of the fin 110 exposed by the isolation layer 130b in the core region II, and reducing the surface area of the fin of the parasitic device, The electrical performance of the semiconductor structure is improved.

In this embodiment, the material of the first gate oxide layer 135 and the second gate oxide layer 141 is the same as that of the isolation layer 130, and the material of the first gate oxide layer 135 and the second gate oxide layer 141 is silicon oxide . In other embodiments, the material of the first gate oxide layer and the second gate oxide layer may also be silicon oxynitride.

Specifically, the steps of forming the first gate oxide layer 135 and the second gate oxide layer 141 will be described in detail below with reference to the accompanying drawings.

As shown in FIG. 16, a dummy gate structure 137 is formed across the fin structure 120 and the channel stack 103, the dummy gate structure 137 includes a first gate oxide layer 135, and covers the first gate oxide layer 135 dummy gate layer 136 .

It should be noted that a sidewall layer 138 is further formed on the sidewall of the dummy gate layer 136 , and the sidewall layer 138 is used to protect the sidewall of the dummy gate layer 136 during the formation of the semiconductor structure.

As shown in FIG. 17 , a dielectric layer 139 is formed on the substrate 100 where the dummy gate structure 137 is exposed.

As shown in FIG. 18, the dummy gate layer 136 is removed, and a first opening 340 is formed in the dielectric layer 139 of the peripheral region I, and a second opening 350 is formed in the dielectric layer 139 of the core region II. The first opening 340 and the second opening 350 expose the first gate oxide layer 135 .

As shown in FIG. 19 , a protective layer 147 is formed in the first opening 340; after the protective layer 147 is formed, the first gate oxide layer 135 exposed by the second opening 350 is removed; the sacrificial layer 101 is removed; After removing the sacrificial layer 101 , a second gate oxide layer 141 is formed on the surface of the channel layer 102 exposed by the second opening 350 , and the thickness of the second gate oxide layer 141 is smaller than that of the first gate oxide layer 135 .

Referring to FIG. 20, after forming the second gate oxide layer 141, remove the protection layer 147; form a high-k dielectric layer 142 covering the first gate oxide layer 135 and the second gate oxide layer 141, and cover the The gate electrode layer 143 of the high-k dielectric layer 142, the first gate oxide layer 135 and the high-k dielectric layer 142 of the peripheral region I constitute the gate dielectric layer (not shown) of the peripheral region I, and the gate dielectric layer of the peripheral region I layer and the gate electrode layer 143 constitute the first gate structure 144, the second gate oxide layer 141 and the high-k dielectric layer 142 of the core region II constitute the gate dielectric layer (not marked) of the core region II, and the core region II The gate dielectric layer and the gate electrode layer 143 form a second gate structure 145 .

The thickness of the second gate oxide layer 141 is smaller than that of the first gate oxide layer 135 , so that the thickness of the gate dielectric layer in the core region II is smaller than the thickness of the gate dielectric layer in the peripheral region I.

In other embodiments, the second gate oxide layer may not be formed after removing the sacrificial layer, so that the gate dielectric layer in the core region includes a high-k dielectric layer, and the gate dielectric layer in the peripheral region includes a second gate dielectric layer. A gate oxide layer and a high-k dielectric layer, so that the thickness of the gate dielectric layer in the core area is smaller than the thickness of the gate dielectric layer in the peripheral area.

In this embodiment, the first gate structure 144 and the second gate structure 145 are metal gate structures.

Correspondingly, the present invention also provides a semiconductor structure. Referring to FIG. 20 , it shows a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

The semiconductor structure includes: a substrate 100 including a peripheral region I for forming input/output devices and a core region II for forming core devices; fins 110 protruding from the substrate 100 surface; channel structure layer 125, located on the fin 110 of the core region II and spaced apart from the fin 110, the channel structure layer 125 includes a plurality of channel layers 102 spaced apart; fin material Layer 115, located on the fin portion 110 of the peripheral region I, the fin portion material layer 115 and the fin portion 110 are made of the same material, the fin portion material layer 115 and the fin portion 110 at the bottom of the fin portion material layer 115 Constituting the fin structure 120; the isolation layer 130 is located on the substrate 100 exposed by the channel structure layer 125 and the fin structure 120, and the isolation layer 130 of the core region II exposes the fin and channel of the core region II The space between the structure layers 125 , the isolation layer 130 of the peripheral region I covers part of the sidewall of the fin structure 120 .

In the embodiment of the present invention, the core device is an all-enclosed gate field effect transistor, which is beneficial to improve the control ability of the second gate structure 145 on the channel layer 102, thereby optimizing the electrical performance of the core device. Moreover, compared with the solution in which both the peripheral region and the core region adopt a channel structure layer and a fully surrounded gate structure, in the embodiment of the present invention, the peripheral region I adopts the fin structure 120, and the core region II adopts the channel structure Layer 125, the gate oxide layer of the peripheral region I and the core region II can be formed in different steps, which is beneficial to avoid the mutual influence of the formation steps of the gate oxide layer of the peripheral region I and the core region II, simplifying the process flow and reducing the It reduces the difficulty of the process and is conducive to reducing the cost of the process.

In addition, in the field of semiconductors, the material of the gate oxide layer is generally the same as that of the isolation layer. In the embodiment of the present invention, the step of removing the gate oxide layer with a partial thickness of the core region II is avoided, and the isolation layer 130 is avoided in this step. The problem of loss occurs, which helps to reduce the probability of increasing the surface area of the fin 110 exposed by the isolation layer 130b in the core region II, reduces the surface area of the fin of the parasitic device, and improves the electrical performance of the semiconductor structure.

The substrate 100 is used to provide a process platform for the formation of all-around gate transistors and fin field effect transistors.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium, and the substrate can also be a silicon-on-insulator substrate or a silicon-on-insulator substrate. Other types of substrates such as germanium substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

The fin portion 110 exposes part of the substrate 100 , thereby providing a process basis for the formation of the isolation layer 130 . In this embodiment, the fin portion 110 and the substrate 100 are obtained by etching the same semiconductor material layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

Therefore, in this embodiment, the material of the fin portion 110 is the same as that of the substrate 100 , and the material of the fin portion 110 is silicon. In other embodiments, the material of the fins can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium, which are suitable for forming fins, and the fins can also be combined with the The material of the substrate is different.

The channel layer 102 is used to provide a channel fully surrounding the gate transistor.

In this embodiment, the semiconductor structure is an NMOS transistor, and the material of the channel layer 102 is Si, thereby improving the performance of the NMOS transistor. In other embodiments, when the semiconductor structure is a PMOS transistor, in order to improve the performance of the PMOS transistor, SiGe channel technology can be used. Correspondingly, the materials of the fin and the channel layer are both SiGe.

In this embodiment, two channel layers 102 are formed on the fin portion 110 . In other embodiments, according to actual process requirements, the number of the channel layers is not limited to two.

In this embodiment, the material of the fin material layer 115 is the same as that of the fin 110 , and the material of the fin material layer 115 is also Si. By making the material of the fin material layer 115 and the fin 110 the same, so that the fin material layer 115 and the fin 110 at the bottom of the fin material layer 115 constitute the fin structure 120 of the peripheral region 1, thereby providing input / Channel of the output device.

In this embodiment, the top of the fin material layer 115 is flush with the top of the channel structure layer 125, which is conducive to improving the height consistency between the fin structure 120 and the channel structure layer 125, and reducing the problem of differences in semiconductor structures. probability.

In this embodiment, the material of the isolation layer 130 is silicon oxide, which is beneficial to reduce the process cost and improve the function of the isolation layer 130 for isolating adjacent devices. In other embodiments, the material of the isolation layer may also be other insulating materials such as silicon nitride and silicon oxynitride.

In this embodiment, the top of the isolation layer 130 in the peripheral region I is higher than the top of the isolation layer 130 in the core region II, so that the height of the fin structure 120 in the peripheral region I exposed by the isolation layer 130 is smaller, which is beneficial to reduce the The parasitic capacitance on the I-fin structure 120 optimizes the electrical performance of the I/O device.

It should be noted that, in this embodiment, the semiconductor structure further includes: an etch stop layer 106 located on the top of the isolation layer 130 in the peripheral region I, and the bottom of the etch stop layer 106 is higher than that of the core region II the top of the fin 110 .

The top of the etching stop layer 106 is used as an etching stop position for defining the peripheral region I isolation layer 130a when forming the isolation layer 130, so that the top of the peripheral region I isolation layer 130a is higher than the core region II isolation layer. On the top of the layer 130b, the height of the fin structure 120 in the peripheral region I exposed by the isolation layer 130 is relatively small, which is beneficial to reduce the parasitic capacitance on the fin structure 120 in the peripheral region I and optimizes the electrical performance of the input/output device.

In this embodiment, the etching stop layer 106 is a material of the isolation layer 130 doped with silicon ions. In this embodiment, the material of the isolation layer 130 is silicon oxide, and the material of the etching stop layer 106 is silicon oxide doped with silicon ions.

The silicon oxide material doped with silicon ions has higher hardness, and the etching selectivity of silicon oxide and silicon is relatively large, which is conducive to improving the etching selectivity ratio of the isolation layer 130 and the etching stop layer 106, so that the The top of the etch stop layer 106 can function to define etch stop locations.

Therefore, in this embodiment, the doping concentration of silicon ions in the etching stop layer 106 should not be too small, nor should it be too large. If the doping concentration of silicon ions in the etch stop layer 106 is too small, the effect of increasing the etch selectivity ratio of the etch stop layer 106 and the isolation layer 130 is not significant, so that the etch stop layer 106 is easily reduced. The top is used to define the etching stop position; if the doping concentration of silicon ions in the etching stop layer 106 is too high, the probability of problems such as leakage current in the etching stop layer 106 will easily increase. Therefore, in this embodiment, the doping concentration of silicon ions in the etching stop layer 106 is 1.0e18 atoms per cubic centimeter to 50.0e20 atoms per cubic centimeter.

It should be noted that, in this embodiment, the distance from the top of the etching stop layer 106 in the peripheral region I to the top of the isolation layer 130b in the core region II should not be too small, nor should it be too large. If the distance is too small, since the channel layer 102 of the core region II is spaced from the fin 110, and the peripheral region I is the fin structure 120, it is easy to cause the exposed fin structure of the isolation layer 130a in the peripheral region I. If the height of 120 is too large, the parasitic capacitance on the fin structure 120 of the input/output device is too large; if the distance is too large, the core region II isolation layer 130b exposes the Therefore, the height of the fin structure 120 exposed by the isolation layer 130a of the peripheral region 1 is too small, and the material of the fin structure 120 for providing input/output devices is too small, which is easy to be damaged. The electrical performance of the input/output device, such as the drive current, will have adverse effects. Therefore, in this embodiment, the distance from the top of the etching stop layer 106 in the peripheral region I to the top of the isolation layer 130b in the core region II is greater than 0 nm and less than 65 nm.

Specifically, in this embodiment, the distance from the top of the etching stop layer 106 in the peripheral region I to the top of the fin structure 120 is greater than 35 nm and less than 50 nm, and the distance from the top of the isolation layer 130b in the core region I to the trench The distance from the top of the track structure layer 125 is greater than 50nm and less than 100nm.

It should also be noted that, in this embodiment, the thickness of the etching stop layer 106 should not be too small, nor should it be too large. If the thickness is too small, it is easy to reduce the top of the etching stop layer 106 for defining the etching stop position; if the thickness is too large, it is easy to cause the height of the fin structure 120 exposed by the isolation layer 130a in the peripheral region I. Too small and the resulting I/O device has poor performance. Therefore, in this embodiment, the thickness of the etching stop layer 106 is 2 nm to 4 nm.

In this embodiment, the semiconductor structure further includes: a first gate oxide layer 135 located on the surface of the fin structure 120 exposed by the isolation layer 130; a second gate oxide layer 141 located on the channel exposed by the isolation layer 130 On the surface of the structure layer 125 , the thickness of the second gate oxide layer 141 is smaller than the thickness of the first gate oxide layer 135 .

By making the thickness of the second gate oxide layer 141 smaller than the thickness of the first gate oxide layer 135 , the thickness of the gate dielectric layer of the input/output device is increased, which is beneficial to improve the breakdown voltage of the input/output device.

In the embodiment of the present invention, the peripheral region I adopts the fin structure 120, and the core region II adopts the channel structure layer 125, so that the formation steps of the peripheral region I and the core region II gate oxide layer will not affect each other, simplifying The process flow for forming the semiconductor structure is improved, and it is beneficial to reduce the process cost; in addition, the materials of the gate oxide layer and the isolation layer are usually the same, and in the embodiment of the present invention, the separation of the isolation layer in the step of removing the gate oxide layer with a partial thickness of the core region II is avoided. The loss is beneficial to reduce the probability of increasing the surface area of the fin 110 exposed by the isolation layer of the core region II, reduces the surface area of the fin of the parasitic device, and improves the electrical performance of the semiconductor structure.

In this embodiment, the material of the first gate oxide layer 135 and the second gate oxide layer 141 is the same as that of the isolation layer 130, and the material of the first gate oxide layer 135 and the second gate oxide layer 141 is silicon oxide . In other embodiments, the material of the first gate oxide layer and the second gate oxide layer may also be silicon oxynitride.

It should be noted that, in this embodiment, the semiconductor structure further includes: a high-k dielectric layer 142 covering the first gate oxide layer 135 and the second gate oxide layer 141; a gate electrode layer 143 covering the high-k dielectric layer 142, the first gate oxide layer 135 and the high-k dielectric layer 142 in the peripheral region I constitute the gate dielectric layer (not marked) in the peripheral region I, and the gate dielectric layer and the gate electrode layer 143 in the peripheral region I constitute the first The gate structure, the second gate oxide layer 141 and the high-k dielectric layer 142 of the core region II constitute the gate dielectric layer (not marked) of the core region II, and the gate dielectric layer and the gate electrode layer 143 of the core region II constitute The second gate structure 145 .

The thickness of the second gate oxide layer 141 is smaller than that of the first gate oxide layer 135 , so that the thickness of the gate dielectric layer in the core region II is smaller than the thickness of the gate dielectric layer in the peripheral region I. In other embodiments, the second gate dielectric layer may not include a gate oxide layer.

In this embodiment, the first gate structure 144 and the second gate structure 145 are metal gate structures.

It should also be noted that, in this embodiment, the semiconductor structure further includes: sidewalls 138 located on the sidewalls of the first gate structure 144 and the second gate structure 145; a source-drain doped layer (Fig. not shown), located in the fin structure 120 on both sides of the first gate structure 144, and in the channel structure layer 125 on both sides of the second gate structure 145; the dielectric layer 139, located in the first gate The structure 144 and the second gate structure 145 are exposed on the substrate 100 .

The semiconductor structure may be formed using the forming methods described in the foregoing embodiments, or may be formed using other forming methods. For the specific description of the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the preceding embodiments, and details will not be repeated here in this embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (22)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a peripheral region used for forming an input/output device and a core region used for forming a core device, the substrate comprises a substrate, a fin portion protruding out of the substrate and a plurality of channel laminated layers sequentially located on the fin portion, and each channel laminated layer comprises a sacrificial layer and a channel layer located on the sacrificial layer;

forming an isolation film on the substrate exposed by the channel lamination;

removing the channel lamination layer on the peripheral area, and forming an opening in the isolation film;

forming a fin material layer in the opening, wherein the fin material layer is made of the same material as the fin part, and the fin part material layer and the fin part at the bottom of the fin material layer are used as fin part structures of the peripheral area;

after the fin structure in the peripheral area is formed, the isolation film is etched, the etched residual isolation film serves as an isolation layer, the isolation layer in the core area is exposed out of the channel lamination layer in the core area, and the isolation layer in the peripheral area covers part of the side wall of the fin structure.

2. The method of forming a semiconductor structure of claim 1, wherein the step of forming the opening comprises: forming a first mask layer covering the channel lamination layer and the isolation film of the core region; removing the channel lamination layer in the peripheral area by taking the first mask layer as a mask, and forming an opening in the isolation film;

after forming the opening, the forming method further includes: and removing the first mask layer.

3. The method of forming a semiconductor structure of claim 1, wherein the channel stack in the peripheral region is removed using a dry etch process.

4. The method of claim 1, wherein an epitaxial growth process is used to form a layer of fin material within the opening.

5. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the layer of fin material, a top of the layer of fin material is flush with a top of the channel stack.

6. The method of forming a semiconductor structure according to claim 1, wherein after the forming of the isolation film and before the forming of the isolation layer, further comprising: forming an etching stop layer in the isolation film in the peripheral area, wherein the bottom of the etching stop layer is higher than the top of the fin part;

in the step of forming the isolation layer, the top of the etching stop layer is used as a stop position, the isolation film is etched, the isolation layer in the peripheral area and the isolation layer in the core area are formed, and the top of the isolation layer in the peripheral area is higher than that of the isolation layer in the core area.

7. The method of forming a semiconductor structure according to claim 6, wherein the step of forming an etch stop layer in the isolation film in the peripheral region comprises: before forming the opening, forming a second mask layer covering the channel lamination layer and the isolation film of the core region;

and performing ion implantation by taking the second mask layer as a mask to form an etching stop layer.

8. The method for forming a semiconductor structure according to claim 6 or 7, wherein the etch stop layer is formed by implanting silicon ions into the isolation film in the peripheral region.

9. The method of forming a semiconductor structure according to claim 8, wherein the parameters for implanting silicon ions into the isolation film in the peripheral region include: the implantation energy of the silicon ions is 1.0 to 20.0kev, the implantation dose is 5.0 to 1.0 e12 to 16 atoms per square centimeter, and the implantation angle is 0 to 5 °.

10. The method of claim 8, wherein the isolation film is made of silicon oxide, and the etch stop layer is made of silicon oxide doped with silicon ions.

11. The method of forming a semiconductor structure of claim 6, wherein in the step of forming the etch stop layer, the etch stop layer has a thickness of 2nm to 4nm.

12. The method of forming a semiconductor structure of claim 1, further comprising, after forming said spacer layer: forming a pseudo gate structure crossing the fin part structure and the channel lamination layer, wherein the pseudo gate structure covers part of the top and part of the side wall of the fin part structure and the channel lamination layer, and comprises a first gate oxide layer and a pseudo gate layer covering the first gate oxide layer;

forming a dielectric layer on the substrate exposed out of the pseudo gate structure;

removing the pseudo gate layer, and respectively forming a first opening in the dielectric layer of the peripheral region and a second opening in the dielectric layer of the core region, wherein the first opening and the second opening expose the first gate oxide layer;

forming a protective layer in the first opening, wherein the protective layer covers the first gate oxide layer;

after the protective layer is formed, removing the first gate oxide layer exposed from the second opening;

removing the sacrificial layer;

and after removing the sacrificial layer, forming a second gate oxide layer on the surface of the channel layer exposed by the second opening, wherein the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer.

13. A semiconductor structure, comprising:

a substrate including a peripheral region for forming input/output devices and a core region for forming core devices;

the fin part protrudes out of the surface of the substrate;

the channel structure layer is positioned on the fin part of the core region and is arranged at intervals with the fin part, and the channel structure layer comprises a plurality of channel layers arranged at intervals;

the fin material layer is positioned on the fin part of the peripheral area, the material of the fin material layer is the same as that of the fin part, and the fin material layer and the fin part at the bottom of the fin material layer form a fin part structure;

the isolation layer is positioned on the substrate where the channel structure layer and the fin structure are exposed, the isolation layer of the core region is exposed out of the interval between the fin part of the core region and the channel structure layer, and the isolation layer of the peripheral region covers part of the side wall of the fin structure; the top of the isolation layer in the peripheral area is higher than that of the isolation layer in the core area.

14. The semiconductor structure of claim 13, wherein a top of the fin material layer is flush with a top of the channel structure layer.

15. The semiconductor structure of claim 13, further comprising an etch stop layer on top of the isolation layer in the peripheral region, wherein a bottom of the etch stop layer is higher than a top of the core region fin.

16. The semiconductor structure of claim 15, wherein a distance from a top of the etch stop layer to a top of the core region isolation layer is greater than 0nm and less than 65nm.

17. The semiconductor structure of claim 15, wherein a distance from a top of the etch stop layer to a top of the fin structure is greater than 35nm and less than 50nm, and a distance from a top of the isolation layer of the core region to a top of the channel structure layer is greater than 50nm and less than 100nm.

18. The semiconductor structure of claim 15, wherein the etch stop layer has a thickness of 2nm to 4nm.

19. The semiconductor structure of claim 15, wherein the etch stop layer is a spacer material doped with silicon ions.

20. The semiconductor structure of claim 15 or 19, wherein the material of the isolation layer is silicon oxide, and the material of the etch stop layer is silicon oxide doped with silicon ions.

21. The semiconductor structure of claim 19, wherein the etch stop layer has a doping concentration of silicon ions of 1.0e18 atoms per cubic centimeter to 50.0e20 atoms per cubic centimeter.

22. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises:

the first gate oxide layer is positioned on the surface of the fin structure exposed out of the isolation layer;

and the second gate oxide layer is positioned on the surface of the channel structure layer exposed out of the isolation layer, and the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer.

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