[go: up one dir, main page]

CN111430295B - Interconnection structure, manufacturing method thereof and semiconductor device - Google Patents

Interconnection structure, manufacturing method thereof and semiconductor device Download PDF

Info

Publication number
CN111430295B
CN111430295B CN201910024057.8A CN201910024057A CN111430295B CN 111430295 B CN111430295 B CN 111430295B CN 201910024057 A CN201910024057 A CN 201910024057A CN 111430295 B CN111430295 B CN 111430295B
Authority
CN
China
Prior art keywords
layer
interlayer dielectric
groove
dielectric layer
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910024057.8A
Other languages
Chinese (zh)
Other versions
CN111430295A (en
Inventor
高成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN201910024057.8A priority Critical patent/CN111430295B/en
Publication of CN111430295A publication Critical patent/CN111430295A/en
Application granted granted Critical
Publication of CN111430295B publication Critical patent/CN111430295B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides an interconnection structure, a manufacturing method thereof and a semiconductor device, wherein the manufacturing method comprises the following steps: providing a substrate, forming a first interlayer dielectric layer on the surface of the substrate, forming a first metal layer in the first interlayer dielectric layer, forming a second groove in the second dielectric layer until part of the first metal layer is exposed, forming a second barrier layer on the side wall and the bottom of the second groove, and filling the second metal layer in the second groove and the through hole. The second barrier layer covers the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate, so that the wettability of the subsequently formed second metal layer is better. And the first metal layer is internally provided with the concave, so that the bottom of the through hole is arc-shaped, the cross section area of the through hole current is increased, the contact resistance of the through hole is reduced, and the electromigration resistance is improved.

Description

Interconnection structure, manufacturing method thereof and semiconductor device
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an interconnection structure, a method for manufacturing the interconnection structure, and a semiconductor device.
Background
In the semiconductor industry today, copper interconnect lines are gradually replacing aluminum interconnect lines, and copper lines have the following advantages over aluminum lines: 1) Resistivity 2) good resistance to electron migration, copper being higher than aluminum in resistance to electron migration; 3) Copper has a higher melting point than aluminum and a better thermal budget than aluminum.
However, copper has poor adhesion to silicon oxide, and has a high diffusivity in silicon oxide and silicon, and copper diffusion causes serious metal contamination. Tantalum/tantalum nitride (Ta/TaN) is used as a copper diffusion barrier layer in a general process, and has good adhesion property to copper and good diffusion barrier property to copper.
However, with further reduction of the feature size, the ratio of Ta/TaN in the wire cross section is larger and larger, the Ta film resistivity is 150 to 180 μΩ·cm at 20 ℃, and TaN is 200 to 240 μΩ·cm, so that the wire resistance and the via resistance are increased, resulting in deterioration of the resistance-capacitance delay (RC delay) and the power consumption, and at the same time, with further reduction of the feature size, the performance of the Cu wire against electron migration is affected.
Disclosure of Invention
The invention mainly aims to provide an interconnection structure, a manufacturing method thereof and a semiconductor device, which solve the problem that the copper interconnection line is defective due to the reduction of the size.
In order to achieve the above object, the present invention provides a method for manufacturing an interconnection structure, including: providing a substrate, wherein a first interlayer dielectric layer is formed on the surface of the substrate, and a first metal layer is arranged in the first interlayer dielectric layer; forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer; forming a second groove in the second interlayer dielectric layer, wherein the second groove exposes part of the first metal layer; forming a second barrier layer on the side wall and the bottom of the second groove, wherein the material of the second barrier layer comprises ruthenium tantalate; and filling a second metal layer in the second groove and the through hole.
Optionally, in the method for manufacturing an interconnection structure, a first groove is formed in the first interlayer dielectric layer, and the first metal layer is filled in the first groove.
Optionally, in the method for manufacturing an interconnection structure, after forming the first groove, before filling the first metal layer, the method further includes: and forming a first barrier layer on the side wall and the bottom of the first groove, wherein the material of the first barrier layer comprises ruthenium tantalate.
Optionally, in the method for manufacturing an interconnection structure, the step of forming the second groove includes:
forming a plurality of third grooves in the second interlayer dielectric layer, wherein the first metal layer is not exposed by the third grooves;
forming a through hole in the second dielectric layer at the bottom of the third groove until part of the first metal layer is exposed, wherein the width of the through hole is smaller than that of the third groove;
the third groove and the through hole jointly form the second groove. .
Optionally, in the method for manufacturing an interconnection structure, after forming the through hole, before forming the second barrier layer, the method further includes:
Forming a protective layer on the side wall and the bottom of the second groove and the side wall of the through hole, wherein the material of the protective layer comprises nitrogen-containing ruthenium tantalate;
The step of forming the protective layer includes:
forming a protective layer on the side walls and the bottoms of the third groove and the through hole;
etching the protective layer and the first metal layer at the bottom of the through hole to form a recess in the first metal layer, so that the bottom of the through hole is arc-shaped.
Optionally, in the method for manufacturing an interconnection structure, a thickness of the protective layer is smaller than a thickness of the second barrier layer.
Correspondingly, the invention also provides an interconnection structure, which comprises: a substrate; the first interlayer dielectric layer is positioned on the substrate and is internally provided with a first metal layer; the second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer, a second groove is formed in the second interlayer dielectric layer, and part of the first metal layer is exposed out of the second groove; the second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate; and the second metal layer is filled in the second groove.
Optionally, in the interconnection structure, a first groove is formed in the first interlayer dielectric layer, and the first metal layer is filled in the first groove.
Optionally, in the interconnection structure, a first barrier layer is further included, the first barrier layer is located on a side wall and a bottom of the first groove, and a material of the first barrier layer includes ruthenium tantalate.
Optionally, in the interconnection structure, the second groove includes: the second metal layer is formed on the second interlayer dielectric layer, the third groove is formed in the second interlayer dielectric layer, the through hole is formed in the bottom of the third groove, the width of the through hole is smaller than that of the second groove, and part of the first metal layer is exposed out of the through hole.
Optionally, in the interconnection structure, the interconnection structure further includes a protection layer formed on a sidewall and a bottom of the third groove and a sidewall of the through hole, and the material of the protection layer includes nitrogen-containing ruthenium tantalate.
Optionally, in the interconnection structure, a thickness of the protective layer is smaller than a thickness of the second barrier layer.
Optionally, in the interconnection structure, a recess is formed in the first metal layer so that the bottom of the through hole is arc-shaped.
Correspondingly, the invention also provides a semiconductor device, which comprises: a substrate; the first interlayer dielectric layer is positioned on the substrate and is internally provided with a first metal layer; the second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer, a second groove is formed in the second interlayer dielectric layer, and part of the first metal layer is exposed out of the second groove; the second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate; and the second metal layer is filled in the second groove.
Compared with the prior art, the invention has the following beneficial effects:
after the second groove is formed, a second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate, so that the wettability of a subsequently formed second metal layer is better.
Further, the second groove comprises a third groove and a through hole, after the third groove and the side wall and the bottom of the through hole form a protective layer, the protective layer and the first metal layer at the bottom of the through hole are etched to form a recess in the first metal layer, so that the bottom of the through hole is arc-shaped, the bottom of the second barrier layer and the bottom of the second metal layer which are formed subsequently are arc-shaped, the cross-sectional area of the through hole current is increased, the contact resistance of the through hole is reduced, and the anti-electron migration capability is increased.
Further, before forming the second barrier layer, forming a protective layer on the side wall and the bottom of the third groove and the side wall of the through hole, wherein the material of the protective layer comprises nitrogen-containing ruthenium tantalate, and the material of the second barrier layer comprises ruthenium tantalate, so that compared with tantalum/tantalum nitride, the resistance value of the through hole of ruthenium tantalate/nitrogen-containing ruthenium tantalate is reduced, and RC delay and power consumption can be effectively reduced; and the nitrogen-containing ruthenium tantalate can effectively block the diffusion of the second metal layer, so that the performance of the device is improved.
Further, compared with the wettability of tantalum and copper, the wettability of ruthenium tantalate and copper is improved, a thin copper seed layer which is uniformly and continuously formed can be deposited on the ruthenium tantalate, and the formation of opening overhang is prevented, so that the formation of cavities is avoided; and compared with tantalum/tantalum nitride, the barrier property of ruthenium tantalate/nitrogen-containing ruthenium tantalate to oxygen is enhanced, so that the electromigration resistance effect of the Cu wire is improved, and meanwhile, the smooth and continuous Cu seed layer formed on the ruthenium tantalate can improve the performance of subsequent Cu electroplating.
Further, the thickness of the protective layer is smaller than that of the second barrier layer, when the protective layer at the bottom of the through hole and the first metal layer are etched, the protective layer on the side wall can block pollutants sputtered to the side wall, the thickness of the protective layer is thinner, the cost can be reduced, the second barrier layer is thicker, electroplating can be realized only by depositing relatively fewer seed layers on the surface of the second barrier layer, and the formation of opening overhang is prevented.
Drawings
FIGS. 1a-1 d are schematic cross-sectional views of steps of a method of fabricating an interconnect structure;
FIGS. 2 a-2 b are schematic cross-sectional views of steps of a method of fabricating an interconnect structure;
FIGS. 3 a-3 b are schematic cross-sectional views of steps of a method of fabricating an interconnect structure;
FIGS. 4 a-4 b are schematic cross-sectional views of steps of a method of fabricating an interconnect structure;
FIG. 5 is a flowchart illustrating a method for fabricating an interconnect structure according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of a substrate provided in a method of fabricating an interconnect structure according to an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of a first metal layer being filled over the structure depicted in FIG. 6;
FIG. 8 is a schematic cross-sectional view of a second recess formed in the structure depicted in FIG. 7;
FIG. 9 is a schematic cross-sectional view of a protective layer formed over the structure depicted in FIG. 8;
FIG. 10 is a schematic cross-sectional view of forming a recess in the first metal layer at the bottom of the via on the structure shown in FIG. 9;
FIG. 11 is a schematic cross-sectional view of a second barrier layer formed over the structure shown in FIG. 10;
FIG. 12 is a schematic cross-sectional view of a metal seed layer formed over the structure shown in FIG. 11;
fig. 13 is a schematic cross-sectional view of filling a second metal layer over the structure shown in fig. 12.
Wherein, the reference numerals are as follows:
10-a first interlayer dielectric layer; 11-a first groove; 12-a first barrier layer; 13-a first metal layer; 14-a low dielectric constant barrier layer; 15-a second interlayer dielectric layer; 16-a second groove; 17-through holes; 18-a second barrier layer; 19-a metal seed layer; 20-a second metal layer; 100-a first interlayer dielectric layer; 110-a first groove; 120-a first barrier layer; 130-a first metal layer; 140-a low dielectric constant barrier layer; 150-a second interlayer dielectric layer; 160-a second groove; 161-third groove; 162-via; 170-a protective layer; 180-a second barrier layer; 190-a metal seed layer; 200-second metal layer
Detailed Description
FIGS. 1 a-1 d are schematic cross-sectional views of steps of a method for fabricating an interconnect structure. As shown in fig. 1a, a first interlayer dielectric layer 10 is first formed on a substrate (not shown), the material of the first interlayer dielectric layer 10 comprises silicon oxide, a first recess 11 is formed in the first interlayer dielectric layer 10 by etching, and then a first barrier layer 12 is formed, the first barrier layer 12 covers the sidewall and the bottom of the first recess 11, and the material of the first barrier layer 12 comprises tantalum/tantalum nitride (Ta/TaN). Next, referring to fig. 1b, the first metal layer 13 is filled in the first groove 11. In this embodiment, one first groove 11 may be formed, or a plurality of first grooves 11 may be formed.
Next, a low dielectric constant barrier layer 14 and a second interlayer dielectric layer 15 are sequentially formed on the first interlayer dielectric layer 10 and the first metal layer 13, and a portion of the second interlayer dielectric layer 15 is etched to form a second groove 16, wherein the low dielectric constant barrier layer 14 comprises a laminated structure composed of silicon nitride and silicon carbide nitride, and the material of the second interlayer dielectric layer 15 comprises silicon oxide. Then, the second interlayer dielectric layer 15 and the low-k dielectric layer 14 at the bottom of the second groove 16 are etched to form a via hole 17 until a part of the first metal layer 13 is exposed, and the width of the via hole 17 is smaller than the width of the second groove 16, as shown in fig. 1 c. Next, a second barrier layer 18 is formed on the sidewalls and bottom of the second recess 16 and the via hole 17, and the material of the second barrier layer 18 includes tantalum/tantalum nitride, as shown in fig. 1 d.
In this embodiment, tantalum/tantalum nitride (Ta/TaN) refers to: tantalum, tantalum nitride, or a stacked structure of tantalum and tantalum nitride. Wherein the tantalum nitride is formed by tantalum nitridation.
Then, a metal seed layer 19 is formed on the sidewalls and bottom of the second recess 16 and the via hole 17, and a second metal layer 20 is filled in the second recess 16 and the via hole 17 to form an interconnection structure, wherein the material of the metal seed layer 19 is preferably copper, and the material of the second metal layer 20 is preferably copper. However, as the feature size is reduced, the copper seed layer is too thin, which may cause the copper seed layer to agglomerate, as shown in fig. 2a, and the metal seed layer 19 may agglomerate on the second barrier layer 18, resulting in a subsequent failure of the second metal layer 20 to fill the via 17 and the second recess 16, as shown in fig. 2b, i.e., the copper seed layer may agglomerate, resulting in a failure to perform a normal copper plating fill.
However, too thick copper seed layer may cause overhang at the via opening, as shown in fig. 3a, and too thick metal seed layer 19 may form overhang at the top of the sidewall of the via 17, and voids are easily formed in the via due to overhang sealing when the second metal layer 20 is subsequently filled, as shown in fig. 3 b.
Referring to FIG. 4a, after normal electroplating, the electromigration failure is likely to occur due to poor oxygen barrier performance of Ta/TaN as a barrier layer, resulting in poor electromigration resistance of the interconnect lines. As shown in fig. 4b, as the feature size is further reduced, ta/TaN is more and more scaled in the wire cross section, increasing the wire resistance and via resistance, resulting in deterioration of RC delay and power consumption.
Based on the above problems, the applicant provides a method for manufacturing an interconnection structure, comprising: providing a substrate, wherein a first interlayer dielectric layer is formed on the surface of the substrate, a first metal layer is arranged in the first interlayer dielectric layer, a second interlayer dielectric layer is formed, the second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer, a second groove is formed in the second dielectric layer, the second groove exposes part of the first metal layer, a second barrier layer is formed on the side wall and the bottom of the second groove, the material of the second barrier layer comprises ruthenium tantalate, and the second metal layer is filled in the second groove.
Applicants also provide an interconnect structure comprising: the substrate is provided with a first interlayer dielectric layer which is positioned on the substrate and is internally provided with a first metal layer; the second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer, a second groove is formed in the second interlayer dielectric layer, and part of the first metal layer is exposed out of the second groove; the second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate; and the second metal layer is filled in the second groove.
In the interconnection structure and the manufacturing method thereof provided by the invention, after the second groove is formed, the second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate, so that the wettability of the subsequently formed second metal layer is better.
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In the following description, the present invention will be described in detail with reference to the drawings, which are not to be construed as limiting the invention, for the purpose of illustration and not as an actual scale.
Fig. 5 is a flowchart of a method for fabricating an interconnect structure according to an embodiment of the invention. As shown in fig. 5, the method for manufacturing the interconnection structure includes the following steps:
Step S01: providing a substrate, wherein a first interlayer dielectric layer is formed on the substrate, and a first metal layer is arranged in the first interlayer dielectric layer;
step S02: forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer;
Step S03: forming a plurality of second grooves in the second dielectric layer, wherein the second grooves expose part of the first metal layer;
step S04: forming a second barrier layer on the side wall and the bottom of the second groove, wherein the material of the second barrier layer comprises ruthenium tantalate;
step S05: and filling the second metal layer in the second groove.
Fig. 6 is a schematic cross-sectional view of a substrate provided in a method for fabricating an interconnect structure according to an embodiment of the invention. Referring to fig. 6, in step S01, a substrate is provided, a first interlayer dielectric layer 100 is formed on the surface of the substrate, and a first metal layer 130 is disposed in the first interlayer dielectric layer 100.
Specifically, first, a substrate (not shown) is provided, and the substrate may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon On Insulator (SOI), gallium arsenide or gallium nitride, or other materials known to those skilled in the art. The substrate surface may also be formed with a semiconductor device layer (not shown) in which a number of semiconductor devices such as MOS field effect transistors, diodes or resistors are formed, which need to be electrically connected by an interconnect structure composed of a plurality of layers of conductive plugs and a plurality of layers of metal interconnect lines to complete the electrical functions of the integrated circuit chip.
Then, a first interlayer dielectric layer 100 is formed on the substrate, which may be formed using a deposition process, for example. The material of the first interlayer dielectric layer 100 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., and in this embodiment, the material of the first interlayer dielectric layer 100 is preferably silicon oxide.
Next, a photoresist layer (not shown) is formed on the first interlayer dielectric layer 100, for example, by spin coating. The photoresist layer is then exposed and developed to form a patterned photoresist layer, in which a plurality of openings exposing the first interlayer dielectric layer 100 are formed. Next, the first interlayer dielectric layer 100 is etched using the patterned photoresist layer as a mask to form a first groove 110. The depth of the first groove 110 is between 170nm and 270nm, and the width of the first groove 110 is between 70nm and 170 nm. In this embodiment, one first groove 110 may be formed, or a plurality of first grooves 110 may be formed.
In this embodiment, before forming the first interlayer dielectric layer 100, the method may further include: a third interlayer dielectric layer (not shown) is formed on the substrate, and a plurality of through holes are formed in the third interlayer dielectric layer by using photolithography and etching processes to expose regions (not shown) of the substrate that need to be electrically connected. And forming a conductive material layer on the third interlayer dielectric layer, filling the through holes with the conductive material, and flattening the conductive material layer until the third interlayer dielectric layer is exposed, so as to form conductive plugs in the through holes. The material of the conductive plug includes, but is not limited to, tungsten, copper or cobalt, and in this embodiment, the material of the conductive plug is preferably tungsten. The conductive plugs connect regions of the substrate that require electrical connection with interconnect structures to achieve interconnection. Before forming the conductive material layer, further comprising: and forming a barrier layer on the side wall and the bottom of the through hole, wherein the barrier layer is used for preventing diffusion or migration of metal in the conductive plug.
Fig. 7 is a schematic cross-sectional view of filling the first metal layer on the structure shown in fig. 6, please refer to fig. 6 and 7, wherein a first barrier layer 120 is formed on the sidewall and the bottom of the first recess 110, and a first metal layer 130 is filled in the first recess 110, and the material of the first barrier layer 120 comprises ruthenium tantalate (RuTa).
Specifically, referring to fig. 6, a first barrier layer 120 is formed on the first interlayer dielectric layer 100, and the first barrier layer 120 covers the top of the first interlayer dielectric layer 100, the sidewall and the bottom of the first recess 110. The material of the first barrier layer 120 includes, but is not limited to, ruthenium tantalate, and the first barrier layer 120 may be deposited on the surfaces of the first interlayer dielectric layer 100 and the first recess 110 by a physical vapor deposition process.
In this embodiment, the material of the target used for forming the first barrier layer 120 includes 5at% to 20at% of tantalum and 95at% to 80at% of ruthenium, for example, the material of the target includes 10at% of tantalum and 90at% of ruthenium. The thickness of the first barrier layer 120 is between 10nm and 20nm, the film resistivity of the first barrier layer 120 is 50-70 mu omega cm, and compared with the resistivity of tantalum which is 150-180 mu omega cm and the resistivity of tantalum nitride which is 200-240 mu omega cm, the resistance of the subsequently formed first metal layer can be reduced. In other embodiments, the material of the first barrier layer 120 may be ruthenium tantalate (RuTaN) containing nitrogen, or the first barrier layer 120 may be a stacked structure of ruthenium tantalate and ruthenium tantalate containing nitrogen.
Next, referring to fig. 7, a first metal layer 130 is formed, for example, by electroplating. The first metal layer 130 fills the first recess 110 and covers the first interlayer dielectric layer 100, and then the first metal layer 130 is planarized to expose the first interlayer dielectric layer 100, so as to form a first metal interconnection line. The material of the first metal layer 130 includes, but is not limited to, copper.
The resistivity of copper is 1.678 mu omega cm lower than that of aluminum by 2.65 mu omega cm; copper has a melting point of 1084.77 ℃ and 5555 ℃ respectively, which is higher than aluminum by 666 ℃ and 2519 ℃; compared with aluminum wires, copper is used as wires, so that the wire resistance can be obviously reduced, and the reliability and the integration density of interconnection wires can be improved.
Referring to fig. 8, in step S02, a second interlayer dielectric layer 150 is formed, and the second interlayer dielectric layer 150 covers the first interlayer dielectric layer 100 and the first metal layer 130.
Specifically, first, the low-k barrier layer 140 may be formed, for example, by a deposition process, and the low-k barrier layer 140 covers the first interlayer dielectric layer 100, the first barrier layer 120, and the first metal layer 130. The material of the low-k barrier layer 140 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, etc., and in this embodiment, the low-k barrier layer 140 is a stacked structure including silicon nitride and silicon carbide nitride. The low dielectric constant barrier layer 140 has a thickness of between 60nm and 100 nm.
Next, a second interlayer dielectric layer 150 is formed, for example, by a deposition process, and the second interlayer dielectric layer 150 covers the low dielectric constant barrier layer 140. The material of the second interlayer dielectric layer 150 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., and in this embodiment, the material of the second interlayer dielectric layer 150 is preferably silicon oxide.
Fig. 8 is a schematic cross-sectional view of forming a second recess in the structure shown in fig. 7, please continue to refer to fig. 8, in which in step S03, a second recess 160 is formed in the second dielectric layer 150, and the second recess 160 exposes a portion of the first metal layer 130.
In this embodiment, the second groove 160 includes a third groove 161 formed in the second interlayer dielectric layer 150 and a via 162 formed in the second dielectric layer 150 at the bottom of the third groove 161, the via 162 exposes a portion of the first metal layer 130, and a width of the via 162 is smaller than a width of the third groove 161.
Specifically, a first photoresist layer (not shown) is formed on the second interlayer dielectric layer 150, and the first photoresist layer is exposed and developed, so as to form a first photoresist pattern, and an opening of the first photoresist pattern defines an opening width of a third groove 161 formed in a subsequent step. Then, the second interlayer dielectric layer 150 is etched according to the first photolithography pattern, thereby forming a third groove 161. The third groove 161 is located in the second interlayer dielectric layer 150 and does not penetrate through the second interlayer dielectric layer 150. And then, after the first photoetching pattern is stripped, a second photoetching layer is formed, the second photoetching layer is exposed and developed, so that a second photoetching pattern is formed, the opening of the second photoetching pattern defines the opening width of a through hole 162 formed in the subsequent step, and the opening of the second photoetching pattern is positioned in the second groove 160. Then, the second interlayer dielectric layer 150 in the third groove 161 is etched according to the second photolithography pattern until the low dielectric constant barrier layer 140 is exposed, and then the low dielectric constant barrier layer 140 is etched until a portion of the first metal layer 130 is exposed, thereby forming a via 162. Finally, the second lithography pattern is stripped. The third groove 161 and the through hole 162 together constitute the second groove 160.
In this embodiment, the width of the through hole 162 is smaller than the width of the third groove 161. The depth of the through hole 162 is between 280nm and 380nm, and the width of the through hole 162 is between 50nm and 150 nm; the depth of the third groove 161 is 300 nm-500 nm, and the width of the third groove 161 is 150 nm-300 nm.
Of course, in other embodiments, the through hole 162 may be formed first and then the third groove 161 may be formed according to actual process conditions, which is not limited by the present invention.
Fig. 9 is a schematic cross-sectional view of forming a protective layer on the structure shown in fig. 8, fig. 10 is a schematic cross-sectional view of forming a recess in a first metal layer at the bottom of a via on the structure shown in fig. 9, and fig. 11 is a schematic cross-sectional view of forming a second barrier layer on the structure shown in fig. 10. Referring to fig. 9 to 11, in step S04, a second barrier layer 190 is formed on the sidewall and the bottom of the second recess 160, and the material of the second barrier layer 190 includes ruthenium tantalate.
In this embodiment, the protection layer 170 is formed on the sidewall and bottom of the third recess 161 and the sidewall of the through hole 162 first, and then the second barrier layer 190 is formed on the sidewall and bottom of the third recess 161 and the through hole 162, wherein the material of the protection layer 170 includes nitrogen-containing ruthenium tantalate (RuTaN), and the material of the second barrier layer 190 includes ruthenium tantalate.
First, referring to fig. 9, a protection layer 170 is formed, for example, by a physical vapor deposition process, where the protection layer 170 covers the third recess 161 and the sidewalls and bottom of the through hole 162. The material of the protective layer 170 includes, but is not limited to, nitrogen-containing ruthenium tantalate. In physical vapor deposition, the material of the target material comprises 10% of tantalum and 90% of ruthenium, the ratio of nitrogen to argon in the sputtering gas is 1:1, the bias power is 500-1200 w, the temperature of the chamber is 350-450 ℃, for example, the temperature of the chamber is 400 ℃. Of course, in other embodiments, the material of the protective layer 170 may be ruthenium tantalate, or the protective layer 170 may be a stacked structure of ruthenium tantalate and nitrogen-containing ruthenium tantalate.
Next, referring to fig. 10, the bias power is increased to 1000 w-1800 w to accelerate the argon ions in the cavity vertically downward, so as to generate a physical etching effect on the bottom of the through hole 162, so as to etch the protection layer 170 and the first metal layer 130 at the bottom of the through hole 162, and form a recess in the first metal layer 130, so that the bottom of the through hole 162 is arc-shaped. A small amount of Cu at the bottom of the via 162 may be sputtered back to the sidewall of the via 162 without diffusing into the second interlayer dielectric layer 150 to cause contamination, and the temperature of the chamber in the physical etching is kept unchanged, i.e., between 350 ℃ and 450 ℃, for example, 400 ℃. The nitrogen-containing ruthenium tantalate has good wettability with copper sputtered onto the sidewall, and the copper can well cover the nitrogen-containing ruthenium tantalate on the sidewall of the via 162, so as to avoid the copper from diffusing into the second interlayer dielectric layer 150 and polluting.
Finally, the second barrier layer 180 may be formed, for example, by a physical vapor deposition process, where the second barrier layer 180 covers the third groove 161 and the sidewalls and bottom of the through hole 162. The material of the second barrier layer 180 includes, but is not limited to, ruthenium tantalate. In physical vapor deposition, the target material is 5at% -20at% of tantalum and 95at% -80at% of ruthenium, for example, the target material comprises 10% of tantalum and 90% of ruthenium, the bias power is 500 w-1200 w, the temperature of the chamber is 350-450 ℃, for example, the temperature of the chamber is 400 ℃. The second barrier layer 180 is used as a barrier layer and a wetting layer of a subsequently formed metal seed layer, and the thickness of the second barrier layer 180 is between 8nm and 13 nm. In other embodiments, the material of the second barrier layer 180 may be ruthenium tantalate (RuTaN) containing nitrogen, or the second barrier layer 180 may be a stacked structure of ruthenium tantalate and ruthenium tantalate containing nitrogen.
In this embodiment, the thickness of the protective layer 170 is smaller than that of the second barrier layer 180, when the protective layer 170 at the bottom of the through hole 162 and the first metal layer 130 are etched, the protective layer 170 on the sidewall can block the pollutant sputtered on the sidewall, the thickness of the protective layer is thinner, the cost can be reduced, the second barrier layer 180 is thicker, and electroplating can be realized by depositing relatively fewer seed layers on the surface of the second barrier layer, so that the formation of an opening overhang is prevented.
Fig. 12 is a schematic cross-sectional view of forming a metal seed layer on the structure shown in fig. 11, and fig. 13 is a schematic cross-sectional view of filling a second metal layer on the structure shown in fig. 12. As shown in fig. 12 and 13, in step S05, the second metal layer 210 is filled in the second groove 160.
First, referring to fig. 12, a metal seed layer 190 is formed on the sidewalls and bottom of the third recess 161 and the via 162, for example, by a physical vapor deposition process, and the metal seed layer 190 covers the second barrier layer 180. The material of the metal seed layer 190 includes, but is not limited to, copper.
Compared with the wettability of tantalum and copper, the wettability of ruthenium tantalate and copper is improved, so that a thin copper seed layer can be uniformly and continuously formed on ruthenium tantalate (namely the second barrier layer 180) without agglomerating and forming a suspension at an opening due to the fact that the seed layer is too thick, the electromigration resistance effect of a subsequently formed second metal layer is improved, and meanwhile, the smooth and continuous copper seed layer formed on ruthenium tantalate can improve the electroplating performance of the subsequently formed second metal layer. The thickness of the metal seed layer 190 is between 15nm and 25 nm.
Next, referring to fig. 13, a second metal layer 200 is formed, for example, by electroplating. The second metal layer 200 fills the third recess 161 and the via 162 and covers the second interlayer dielectric layer 150, and then planarizes the second metal layer 200 until the second interlayer dielectric layer 150 is exposed, so as to form a second metal interconnect. The material of the second metal layer 200 includes, but is not limited to, copper.
In this embodiment, the material of the protective layer 170 includes nitrogen-containing ruthenium tantalate, and the material of the second barrier layer 180 includes ruthenium tantalate, and in other embodiments, the material of the protective layer 170 may also be ruthenium tantalate, and the material of the second barrier layer 180 may also be nitrogen-containing ruthenium tantalate. Compared with tantalum/tantalum nitride, the resistance of the through hole of ruthenium tantalate/nitrogen-containing ruthenium tantalate is reduced, and RC delay and power consumption can be effectively reduced; and, the nitrogen-containing ruthenium tantalate can effectively block the diffusion of the second metal layer 200, thereby improving the performance of the device.
Compared with the wettability of tantalum and copper, the wettability of ruthenium tantalate and copper is improved, a thin copper seed layer which is uniformly and continuously formed can be deposited on the ruthenium tantalate, and the formation of opening overhang is prevented, so that the formation of cavities is avoided; and compared with tantalum/tantalum nitride, the barrier property of ruthenium tantalate/nitrogen-containing ruthenium tantalate to oxygen is enhanced, so that the electromigration resistance effect of the Cu wire is improved, and meanwhile, the smooth and continuous Cu seed layer formed on the ruthenium tantalate can improve the performance of subsequent Cu electroplating.
Further, after the third groove 161 and the side wall and bottom of the via hole 162 form the protective layer 170, the protective layer 170 and the first metal layer 130 at the bottom of the via hole 162 are etched to form a recess in the first metal layer 130, so that the bottom of the via hole 162 is arc-shaped, and the bottoms of the subsequently formed second barrier layer 180, metal seed layer 180 and second metal layer 200 are arc-shaped, so that the cross-sectional area of the current of the via hole is increased, thereby reducing the contact resistance of the via hole and increasing the electromigration resistance.
Of course, after the second metal layer 200 is formed, the third metal layer, the fourth metal layer, etc. may be formed by the same method, and may be determined according to actual requirements, which is not limited in the present invention.
Correspondingly, the invention also provides an interconnection structure which is manufactured by adopting the manufacturing method of the interconnection structure. Referring to fig. 13, the interconnection structure includes: a substrate (not shown), a first interlayer dielectric layer 100, a first metal layer 130, a second interlayer dielectric layer 150, a second barrier layer 180, and a second metal layer 200. The first interlayer dielectric layer 100 is located on the substrate, and the first interlayer dielectric layer 100 has a first metal layer 130 therein. The second interlayer dielectric layer 150 covers the first interlayer dielectric layer 100 and the first metal layer 130, and a second groove 160 is formed in the second interlayer dielectric layer 150, and the second groove 160 exposes a portion of the first metal layer 130. The second barrier layer 180 is formed on the sidewall and the bottom of the second recess 160, and the material of the second barrier layer 180 includes ruthenium tantalate. The second metal layer 200 is filled in the second groove 160.
In this embodiment, a first groove 110 is formed in the first interlayer dielectric layer 100, and the first metal layer 130 is filled in the first groove 110. The number of the first grooves 110 may be one or more, which is not limited in this embodiment.
In this embodiment, the second groove 160 includes: the second metal layer 130 is formed by forming a third groove 161 in the second interlayer dielectric layer 150 and forming a through hole 162 in the second interlayer dielectric layer 150 at the bottom of the third groove 161, wherein the width of the through hole 162 is smaller than that of the second groove 161, and the through hole 162 exposes a part of the first metal layer 130.
The interconnection structure further includes a protection layer 170, the protection layer 170 is formed on the sidewall and bottom of the third groove 161 and the sidewall of the through hole 162, and the material of the protection layer 170 includes nitrogen-containing ruthenium tantalate.
In this embodiment, the thickness of the protective layer 170 is smaller than that of the second barrier layer 180, when the protective layer 170 at the bottom of the through hole 162 and the first metal layer 130 are etched, the protective layer 170 on the sidewall can block the pollutant sputtered on the sidewall, the thickness of the protective layer is thinner, the cost can be reduced, and the second barrier layer 180 is thicker, and electroplating can be realized by depositing relatively fewer seed layers on the surface of the second barrier layer, so that the formation of the overhang of the opening is prevented.
In this embodiment, the material of the protective layer 170 includes nitrogen-containing ruthenium tantalate, and the material of the second barrier layer 180 includes ruthenium tantalate, and in other embodiments, the material of the protective layer 170 may also be ruthenium tantalate, and the material of the second barrier layer 180 may also be nitrogen-containing ruthenium tantalate. Compared with tantalum/tantalum nitride, the resistance of the through hole of ruthenium tantalate/nitrogen-containing ruthenium tantalate is reduced, and RC delay and power consumption can be effectively reduced; and, the nitrogen-containing ruthenium tantalate can effectively block the diffusion of the second metal layer 200, thereby improving the performance of the device.
Compared with the wettability of tantalum and copper, the wettability of ruthenium tantalate and copper is improved, a thin copper seed layer which is uniformly and continuously formed can be deposited on the ruthenium tantalate, and the formation of opening overhang is prevented, so that the formation of cavities is avoided; and compared with tantalum/tantalum nitride, the barrier property of ruthenium tantalate/nitrogen-containing ruthenium tantalate to oxygen is enhanced, so that the electromigration resistance effect of the Cu wire is improved, and meanwhile, the smooth and continuous Cu seed layer formed on the ruthenium tantalate can improve the performance of subsequent Cu electroplating.
In this embodiment, the first metal layer 130 is formed with a recess therein so that the bottom of the through hole 162 is arc-shaped, so that the bottoms of the second blocking layer 180 and the second metal layer 200 are arc-shaped, which increases the cross-sectional area of the through hole current, thereby reducing the contact resistance of the through hole and increasing the electromigration resistance.
The interconnect structure further includes: a metal seed layer 190, wherein the metal seed layer 190 is formed on the side walls and bottom of the third groove 161 and the through hole 162; the metal seed layer 190 covers the second barrier layer 180.
The interconnect structure further includes: a low dielectric constant barrier layer 140, wherein the low dielectric constant barrier layer 140 covers the first interlayer dielectric layer 100, the first barrier layer 120, and the first metal layer 130, and the second interlayer dielectric layer 150 covers the low dielectric constant barrier layer 140.
In this embodiment, the depth of the first groove 110 is between 170nm and 270nm, and the width of the first groove 110 is between 70nm and 170 nm. The depth of the through hole 162 is between 280nm and 380nm, and the width of the through hole 162 is between 50nm and 150 nm. The depth of the third groove 161 is 300 nm-500 nm, and the width of the third groove 161 is 150 nm-300 nm. The thickness of the first barrier layer 120 is between 10nm and 20nm, the thickness of the protective layer 170 is between 4nm and 7nm, the thickness of the second barrier layer 180 is between 8nm and 13nm, and the thickness of the metal seed layer 190 is between 15nm and 25 nm.
In this embodiment, the materials of the first interlayer dielectric layer 100 and the second interlayer dielectric layer 150 include, but are not limited to, silicon oxide, the materials of the first metal layer 130 and the second metal layer 200 include, but are not limited to, copper, the material of the metal seed layer 190 includes copper, and the material of the low dielectric constant barrier layer 140 includes silicon nitride and silicon carbide nitride.
Correspondingly, the invention further provides a semiconductor device which comprises the interconnection structure.
Specifically, the semiconductor device includes: the device comprises a substrate, a first metal layer of a first interlayer dielectric layer, a second barrier layer and a second metal layer. The first interlayer dielectric layer is positioned on the substrate, and the first metal layer is arranged in the first interlayer dielectric layer. The second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer, a second groove is formed in the second interlayer dielectric layer, and a part of the first metal layer is exposed out of the second groove. The second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate. The second metal layer is filled in the second groove.
A recess is formed in the first metal layer so that the bottom of the through hole is arc-shaped.
In summary, in the interconnect structure, the method for manufacturing the same, and the semiconductor device provided by the invention, after the second groove is formed, the second barrier layer is formed on the sidewall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate, so that the wettability of the subsequently formed second metal layer is better.
Further, the second groove comprises a third groove and a through hole, after the third groove and the side wall and the bottom of the through hole form a protective layer, the protective layer and the first metal layer at the bottom of the through hole are etched to form a recess in the first metal layer, so that the bottom of the through hole is arc-shaped, the bottom of the second barrier layer and the bottom of the second metal layer which are formed subsequently are arc-shaped, the cross-sectional area of the through hole current is increased, the contact resistance of the through hole is reduced, and the anti-electron migration capability is increased.
Further, before forming the second barrier layer, forming a protective layer on the side wall and the bottom of the third groove and the side wall of the through hole, wherein the material of the protective layer comprises nitrogen-containing ruthenium tantalate, and the material of the second barrier layer comprises ruthenium tantalate, so that compared with tantalum/tantalum nitride, the resistance value of the through hole of ruthenium tantalate/nitrogen-containing ruthenium tantalate is reduced, and RC delay and power consumption can be effectively reduced; and the nitrogen-containing ruthenium tantalate can effectively block the diffusion of the second metal layer, so that the performance of the device is improved.
Further, compared with the wettability of tantalum and copper, the wettability of ruthenium tantalate and copper is improved, a thin copper seed layer which is uniformly and continuously formed can be deposited on the ruthenium tantalate, and the formation of opening overhang is prevented, so that the formation of cavities is avoided; and compared with tantalum/tantalum nitride, the barrier property of ruthenium tantalate/nitrogen-containing ruthenium tantalate to oxygen is enhanced, so that the electromigration resistance effect of the Cu wire is improved, and meanwhile, the smooth and continuous Cu seed layer formed on the ruthenium tantalate can improve the performance of subsequent Cu electroplating.
Further, the thickness of the protective layer is smaller than that of the second barrier layer, when the protective layer at the bottom of the through hole and the first metal layer are etched, the protective layer on the side wall can block pollutants sputtered to the side wall, the thickness of the protective layer is thinner, the cost can be reduced, the second barrier layer is thicker, electroplating can be realized only by depositing relatively fewer seed layers on the surface of the second barrier layer, and the formation of opening overhang is prevented.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (16)

1. A method of fabricating an interconnect structure, comprising:
providing a substrate, wherein a first interlayer dielectric layer is formed on the surface of the substrate, and a first metal layer is arranged in the first interlayer dielectric layer;
forming a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer;
Forming a second groove in the second interlayer dielectric layer, wherein the second groove exposes part of the first metal layer;
Forming a second barrier layer on the side wall and the bottom of the second groove, wherein the material of the second barrier layer comprises ruthenium tantalate; and
Filling a second metal layer in the second groove; wherein the step of forming the second groove includes:
forming a plurality of third grooves in the second interlayer dielectric layer;
Forming a through hole in the second interlayer dielectric layer at the bottom of the third groove until part of the first metal layer is exposed, wherein the width of the through hole is smaller than that of the third groove;
The third groove and the through hole jointly form the second groove;
after forming the through hole, before forming the second barrier layer, further comprising:
and forming a protective layer on the side walls and the bottoms of the through holes and the third grooves, and etching the protective layer and the first metal layer at the bottoms of the through holes so as to form a recess in the first metal layer, so that the bottoms of the through holes are arc-shaped, wherein the protective layer is made of nitrogen-containing ruthenium tantalate.
2. The method for manufacturing an interconnect structure of claim 1, wherein a first recess is formed in the first interlayer dielectric layer, and the first metal layer is filled in the first recess.
3. The method of fabricating an interconnect structure of claim 2, further comprising, after forming the first recess, prior to filling the first metal layer: and forming a first barrier layer on the side wall and the bottom of the first groove, wherein the material of the first barrier layer comprises ruthenium tantalate.
4. The method of fabricating an interconnect structure of claim 1, wherein a thickness of the protective layer is less than a thickness of the second barrier layer.
5. An interconnect structure, comprising:
A substrate;
The first interlayer dielectric layer is positioned on the substrate and is internally provided with a first metal layer;
The second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer, a second groove is formed in the second interlayer dielectric layer, the second groove exposes part of the first metal layer, and the second groove comprises: the second interlayer dielectric layer is formed on the bottom of the first metal layer, the second interlayer dielectric layer is formed on the bottom of the second interlayer dielectric layer, the width of the through hole is smaller than that of the second interlayer dielectric layer, and part of the first metal layer is exposed out of the through hole;
the second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate; and
The second metal layer is filled in the second groove;
The interconnection structure further comprises a protection layer, wherein the protection layer is formed on the side wall and the bottom of the third groove and the side wall of the through hole, and the protection layer is made of nitrogen-containing ruthenium tantalate.
6. The interconnect structure of claim 5 wherein a first recess is formed in said first interlevel dielectric layer, said first metal layer filling said first recess.
7. The interconnect structure of claim 6, further comprising a first barrier layer located on sidewalls and a bottom of the first recess, wherein the first barrier layer comprises ruthenium tantalate.
8. The interconnect structure of claim 5, wherein a thickness of the protective layer is less than a thickness of the second barrier layer.
9. The interconnect structure of claim 5, wherein a recess is formed in the first metal layer such that a bottom of the via is arcuate.
10. The interconnect structure of claim 5 wherein said second barrier layer is formed using a physical vapor deposition process wherein a target comprising 5at% to 20at% tantalum and 95at% to 80at% ruthenium is used.
11. The interconnect structure of claim 7 wherein said first barrier layer is formed using a physical vapor deposition process wherein a target comprising 5at% to 20at% tantalum and 95at% to 80at% ruthenium is used.
12. The interconnect structure of claim 5 wherein said ruthenium tantalate is RuTa.
13. The interconnect structure of claim 5 wherein said nitrogen containing ruthenium tantalate is RuTaN.
14. The interconnect structure of claim 7, further comprising a low dielectric constant barrier layer between the first interlayer dielectric layer and the second interlayer dielectric layer.
15. The interconnect structure of claim 14 wherein the low dielectric constant barrier layer further covers the first barrier layer and a portion of the surface of the first metal layer, the second interlayer dielectric layer covering the low dielectric constant barrier layer.
16. A semiconductor device, comprising:
A substrate;
The first interlayer dielectric layer is positioned on the substrate and is internally provided with a first metal layer;
The second interlayer dielectric layer covers the first interlayer dielectric layer and the first metal layer, a second groove is formed in the second interlayer dielectric layer, the second groove exposes part of the first metal layer, and the second groove comprises: the second interlayer dielectric layer is formed on the bottom of the first metal layer, the second interlayer dielectric layer is formed on the bottom of the second interlayer dielectric layer, the width of the through hole is smaller than that of the second interlayer dielectric layer, and part of the first metal layer is exposed out of the through hole;
the second barrier layer is formed on the side wall and the bottom of the second groove, and the material of the second barrier layer comprises ruthenium tantalate;
the second metal layer is filled in the second groove;
The semiconductor device further comprises a protective layer, wherein the protective layer is formed on the side wall and the bottom of the third groove and the side wall of the through hole, and the material of the protective layer comprises nitrogen-containing ruthenium tantalate.
CN201910024057.8A 2019-01-10 2019-01-10 Interconnection structure, manufacturing method thereof and semiconductor device Active CN111430295B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910024057.8A CN111430295B (en) 2019-01-10 2019-01-10 Interconnection structure, manufacturing method thereof and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910024057.8A CN111430295B (en) 2019-01-10 2019-01-10 Interconnection structure, manufacturing method thereof and semiconductor device

Publications (2)

Publication Number Publication Date
CN111430295A CN111430295A (en) 2020-07-17
CN111430295B true CN111430295B (en) 2024-10-15

Family

ID=71546675

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910024057.8A Active CN111430295B (en) 2019-01-10 2019-01-10 Interconnection structure, manufacturing method thereof and semiconductor device

Country Status (1)

Country Link
CN (1) CN111430295B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114121893A (en) * 2021-10-25 2022-03-01 长鑫存储技术有限公司 Semiconductor structure and method of forming the same
CN119050053B (en) * 2024-10-31 2025-03-04 粤芯半导体技术股份有限公司 Preparation method of barrier layer of metal interconnection device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN209561401U (en) * 2019-01-10 2019-10-29 长鑫存储技术有限公司 Interconnection structure and semiconductor devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100720515B1 (en) * 2005-12-28 2007-05-22 동부일렉트로닉스 주식회사 Method of forming copper metal wiring with local barrier metal layer
US7531384B2 (en) * 2006-10-11 2009-05-12 International Business Machines Corporation Enhanced interconnect structure
US20080128907A1 (en) * 2006-12-01 2008-06-05 International Business Machines Corporation Semiconductor structure with liner
US8232196B2 (en) * 2009-10-29 2012-07-31 International Business Machines Corporation Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN209561401U (en) * 2019-01-10 2019-10-29 长鑫存储技术有限公司 Interconnection structure and semiconductor devices

Also Published As

Publication number Publication date
CN111430295A (en) 2020-07-17

Similar Documents

Publication Publication Date Title
US6509267B1 (en) Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
US10867921B2 (en) Semiconductor structure with tapered conductor
US11456211B2 (en) Method of forming interconnect structure
CN101138072B (en) Single mask MIM capacitor and resistor with in trench copper drift barrier
US6706626B2 (en) Method of fabricating contact plug
US6306732B1 (en) Method and apparatus for simultaneously improving the electromigration reliability and resistance of damascene vias using a controlled diffusivity barrier
EP2356674B1 (en) Dual metal interconnects
US6555461B1 (en) Method of forming low resistance barrier on low k interconnect
US20090020883A1 (en) Semiconductor device and method for fabricating semiconductor device
US10862030B2 (en) Semiconductor devices comprising silver
KR20050015190A (en) Metal Interconnection for avoiding void and method for fabricating the same
CN1516276A (en) Interconnection of semiconductor device with double capping layer and method of manufacturing the same
US6075293A (en) Semiconductor device having a multi-layer metal interconnect structure
US6362526B1 (en) Alloy barrier layers for semiconductors
CN111430295B (en) Interconnection structure, manufacturing method thereof and semiconductor device
US6849541B1 (en) Method of fabricating a dual damascene copper wire
US7679192B2 (en) Semiconductor device including cover layer
US7452805B2 (en) Aluminum based conductor for via fill and interconnect
WO2023116329A1 (en) Hybrid metal interconnects
US20070178690A1 (en) Semiconductor device comprising a metallization layer stack with a porous low-k material having an enhanced integrity
KR100408182B1 (en) Copper barrier layer for copper layer
KR0165379B1 (en) Layer wiring method of semiconductor device
KR20100036008A (en) Method for forming metal wiring of semiconductor device
JP2004056096A (en) Method of forming wiring structure
JP2004072074A (en) Method of forming wiring structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant