CN111769043A - Method for forming gate dielectric layer, semiconductor structure and method for forming the same - Google Patents

Abstract

A forming method of a gate dielectric layer, a semiconductor structure and a forming method of the semiconductor structure are provided, wherein the forming method of the gate dielectric layer comprises the following steps: providing a substrate, and forming a gate dielectric layer on the substrate, wherein the gate dielectric layer has a target physical thickness and a target electrical thickness; carrying out nitrogen doping treatment on the gate dielectric layer, and adjusting the doping amount of the nitrogen doping treatment to enable the electrical thickness of the gate dielectric layer to be equal to the target electrical thickness; wherein the target physical thickness of the gate dielectric layer satisfies: after the nitrogen doping treatment, the longitudinal distance of nitrogen diffusing to the surface of the substrate in the gate dielectric layer is smaller than the target physical thickness. The embodiment of the invention is beneficial to improving the interface defect at the interface between the gate dielectric layer and the substrate while ensuring that the electrical thickness of the gate dielectric layer meets the electrical requirement.

Description

Method for forming gate dielectric layer, semiconductor structure and method for forming the same

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a gate dielectric layer, a semiconductor structure and a method for forming the same.

Background technique

With the continuous improvement of the manufacturing process level of semiconductor devices and the rapid development of integrated circuits, more special requirements are placed on device processing technology. Among them, the requirement for the gate dielectric layer of the MOS device feature size entering the nano-era is an obvious challenge. The preparation process of the gate dielectric layer is a key technology in the semiconductor manufacturing process, which directly affects and determines the electrical characteristics and reliability of the device.

The key performance indicator of a MOSFET device is the drive current, which depends on the gate capacitance. Gate capacitance is proportional to gate surface area and inversely proportional to gate dielectric thickness. Therefore, the gate capacitance can be improved by increasing the gate surface area and reducing the thickness of the gate dielectric, and reducing the thickness of the gate dielectric layer has become the primary means to promote the performance improvement of MOSFET devices.

However, with the further shrinking of the device size, the traditional method of simply reducing the thickness of the gate dielectric has encountered unprecedented challenges. A current practice is to perform nitrogen doping treatment on the gate dielectric layer, thereby increasing the effective electrical thickness of the gate dielectric layer. The nitrogen doping treatment can improve the dielectric constant of the gate dielectric layer, and can effectively suppress the diffusion of gate doping atoms such as boron in the gate dielectric layer, thereby improving the reliability and stability of the device.

SUMMARY OF THE INVENTION

The problem solved by the embodiments of the present invention is to provide a method for forming a gate dielectric layer, a semiconductor structure and a method for forming the same, which can improve the gate dielectric layer and the substrate while ensuring that the electrical thickness of the gate dielectric layer meets electrical requirements. Interface defects at the interface.

To solve the above problems, embodiments of the present invention provide a method for forming a gate dielectric layer, including: providing a substrate; forming a gate dielectric layer on the substrate, the gate dielectric layer having a target physical thickness and a target electrical thickness; The gate dielectric layer is subjected to nitrogen doping treatment, and by adjusting the doping dose of the nitrogen doping treatment, the electrical thickness of the gate dielectric layer is adapted to be equal to the target electrical thickness; wherein, the target physical thickness of the gate dielectric layer is The thickness satisfies: after the nitrogen doping treatment, the longitudinal distance that nitrogen diffuses in the gate dielectric layer to the surface of the substrate is less than the target physical thickness.

Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: using the foregoing method for forming a gate dielectric layer to form a gate dielectric layer on a substrate, where the gate dielectric layer is suitable for serving as the first gate dielectric layer, Wherein, the substrate includes a peripheral area, a first core area and a second core area, and the working voltage of the second core area is greater than that of the first core area; removing the first core area on the second core area a gate dielectric layer; after removing the first gate dielectric layer on the second core region, a second gate dielectric layer is formed on the substrate of the second core region, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer. a thickness of a gate dielectric layer; after forming the second gate dielectric layer, remove the first gate dielectric layer on the substrate of the first core region; after removing the first gate dielectric layer on the substrate of the first core region, A third gate dielectric layer is formed on the substrate of the first core region, and the thickness of the third gate dielectric layer is smaller than that of the second gate dielectric layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the foregoing formation method, comprising: a substrate, the substrate includes a peripheral region, a first core region and a second core region, and the operating voltage of the second core region is greater than the operating voltage of the first core region; a first gate dielectric layer is located on the substrate of the peripheral region, the first gate dielectric layer is doped with nitrogen ions, and the nitrogen ions are located above the substrate in the first gate dielectric layer of the , located on the substrate of the first core region, and the thickness of the third gate dielectric layer is smaller than the thickness of the second gate dielectric layer.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the embodiment of the present invention, a gate dielectric layer is formed on the substrate, and the gate dielectric layer has a target physical thickness and a target electrical thickness, and then nitrogen doping is performed on the gate dielectric layer, which is suitable for increasing the thickness of the gate dielectric layer. The dielectric constant is set, so that the electrical thickness of the gate dielectric layer is equal to the target electrical thickness, wherein the preset physical thickness of the gate dielectric layer satisfies: after the nitrogen doping treatment, nitrogen in the gate dielectric layer flows to all The vertical diffusion distance of the substrate surface diffusion is smaller than the target physical thickness; in the formation process of the semiconductor structure, the step of high temperature treatment is usually included, and by making the target physical thickness of the gate dielectric layer meet the above conditions, the gate dielectric layer can be prevented from Nitrogen in the dielectric layer diffuses to the interface between the gate dielectric layer and the substrate, thereby improving the problem of interface defects. Moreover, by adjusting the doping amount of the nitrogen doping treatment accordingly, it is consistent with the target physical thickness of the gate dielectric layer. In order to make the electrical thickness of the gate dielectric layer equal to the target electrical thickness; to sum up, the embodiments of the present invention can improve the interface between the gate dielectric layer and the substrate while ensuring that the electrical thickness of the gate dielectric layer meets the electrical requirements. The interfacial defects at the location improve the performance of the semiconductor structure.

Description of drawings

1 to 6 are schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure;

FIG. 7 is a relationship diagram of saturation current and off-state leakage current of a semiconductor structure;

8 to 9 are schematic structural diagrams corresponding to each step of an embodiment of a method for forming a gate dielectric layer of the present invention;

10 to 16 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

17 is a SIMS analysis diagram of the variation of nitrogen doping concentration with depth in the semiconductor structure of the embodiment of the present invention;

FIG. 18 is a graph showing the relationship between the saturation current and the off-state leakage current of the semiconductor structure according to the embodiment of the present invention.

Detailed ways

The devices formed so far still suffer from poor performance. Now combined with a method of forming a semiconductor structure, the reasons for the poor performance of the device are analyzed.

Referring to FIG. 1 to FIG. 6 , schematic structural diagrams corresponding to each step in a method for forming a semiconductor structure are shown.

Referring to FIG. 1, a substrate 1 is provided, the substrate 1 includes a peripheral region I, a first core region II and a second core region III, and the operating voltage of the second core region III is greater than that of the first core region II ;

Continuing to refer to FIG. 1 , a first gate dielectric layer 2 is formed on the substrate 1 .

Referring to FIG. 2 , nitrogen doping treatment 3 is performed on the first gate dielectric layer 2 .

Referring to FIG. 3 , after the nitrogen doping treatment 3 is performed, the first gate dielectric layer 2 on the second core region III is removed.

Referring to FIG. 4 , after removing the first gate dielectric layer 2 on the second core region III, a second gate dielectric layer 4 is formed on the substrate 1 of the second core region III. The second gate dielectric layer 4 The thickness is smaller than the thickness of the first gate dielectric layer 2 .

Referring to FIG. 5 , after the second gate dielectric layer 4 is formed, the first gate dielectric layer 2 on the substrate of the first core region II is removed.

Referring to FIG. 6 , after removing the first gate dielectric layer 2 on the substrate of the first core region II, a third gate dielectric layer 5 is formed on the substrate 1 of the first core region II. The third gate dielectric layer The thickness of 5 is smaller than the thickness of the second gate dielectric layer 4 .

In the semiconductor field, a dual gate oxide (DGO) layer process is usually used, that is, only two devices are usually formed on a substrate: an input/output device and a core device, and the substrate accordingly only includes one peripheral district and a week core. In the formation method, a triple gate oxide (TGO) layer process is introduced due to the design requirements of some products (eg, ultra-low leakage), that is, the substrate further includes another core region (ie, the first core region). Two core regions III), and the formation of the second gate dielectric layer 4 usually includes a step of high temperature treatment, that is, compared with the conventional process, the first gate dielectric layer 2 in the formation method will undergo an additional high temperature treatment step, the first gate dielectric layer 2 is greatly affected by the high temperature treatment, and the nitrogen doped in the first gate dielectric layer 2 on the substrate 1 in the peripheral region I will diffuse during the high temperature treatment step , which not only easily causes nitrogen in the first gate dielectric layer 2 to diffuse into the air to cause a reduction in nitrogen content, but also easily causes nitrogen in the first gate dielectric layer 2 to diffuse to the surface of the substrate 1 , thereby Causes interface defects, resulting in poor performance of the resulting semiconductor device.

Referring to FIG. 7 in conjunction with FIG. 7 , a graph of saturation current (IDSAT) and off-state leakage current (IOFF) of a semiconductor structure formed using a conventional process and a semiconductor structure formed using the aforementioned formation method is shown. Wherein, DGO is a semiconductor structure formed by a conventional process, and TGO is a semiconductor structure formed by the aforementioned formation method. As can be seen from the figure, under the same process conditions and under the same saturation current, compared with the semiconductor structure formed by the traditional process, the off-state leakage current of the semiconductor structure formed by the aforementioned formation method is larger, and the formed semiconductor structure Poor performance.

To solve the above problems, the following two methods are currently proposed:

The first method is to not perform nitrogen doping treatment on the first gate dielectric layer, or to reduce the doping dose of the nitrogen doping treatment. In the method, by making the first gate dielectric layer not contain nitrogen atoms or reducing the nitrogen content, the diffusion of nitrogen atoms in the subsequent high temperature processing steps can be avoided, or the nitrogen atoms in the subsequent high temperature processing steps can be reduced. diffusion, reducing the probability of nitrogen atoms diffusing to the substrate surface. However, the first gate dielectric layer does not contain nitrogen atoms or the content of nitrogen atoms is too low, so that the electrical thickness of the first gate dielectric layer is difficult to meet the process requirements, and it is easy to reduce the reliability of the semiconductor device, such as causing: NBTI (Negative-bias temperature instability) effect.

The second method is to reduce the temperature of the high-temperature treatment in the step of forming the second gate dielectric layer, which is also beneficial to reduce the diffusion of nitrogen atoms in the first gate dielectric layer and reduce the probability of nitrogen atoms diffusing to the surface of the substrate . However, in the semiconductor field, a thermal oxidation growth process is usually used to form the second gate dielectric layer, and the thermal oxidation growth process usually requires a higher temperature, which is beneficial to improve the film quality of the second gate dielectric layer, so that the The density of the second gate dielectric layer is better. In the method, reducing the temperature of the high-temperature treatment can easily reduce the density of the second gate dielectric layer, thereby making it difficult for the film quality of the second gate dielectric layer to meet process requirements.

To sum up, there is an urgent need for a method for forming a semiconductor structure, which can improve the interface defects of the semiconductor device while ensuring that the electrical thickness of the gate dielectric layer of the input/output device meets the process requirements, and also reduce the impact on other film layer structures. , to improve process compatibility.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a gate dielectric layer, including: providing a substrate; forming a gate dielectric layer on the substrate, the gate dielectric layer having a target physical thickness and a target electrical thickness; Nitrogen doping is performed on the gate dielectric layer, and the doping dose of the nitrogen doping treatment is adjusted so that the electrical thickness of the gate dielectric layer is equal to the target electrical thickness; wherein, the gate dielectric layer has an electrical thickness equal to the target electrical thickness. The target physical thickness satisfies: after the nitrogen doping treatment, the longitudinal distance that nitrogen diffuses in the gate dielectric layer to the surface of the substrate is smaller than the target physical thickness.

In the embodiment of the present invention, a gate dielectric layer is formed on the substrate, and the gate dielectric layer has a target physical thickness and a target electrical thickness, and then nitrogen doping is performed on the gate dielectric layer, which is suitable for increasing the thickness of the gate dielectric layer. The dielectric constant is such that the electrical thickness of the gate dielectric layer is equal to the target electrical thickness, wherein the target physical thickness of the gate dielectric layer satisfies: after the nitrogen doping treatment, nitrogen in the gate dielectric layer is transferred to the The vertical diffusion distance of the diffusion on the surface of the substrate is smaller than the target physical thickness; in the formation process of the semiconductor structure, a step of high temperature treatment is usually included. By making the target physical thickness of the gate dielectric layer meet the above conditions, the gate dielectric layer can be prevented from being Nitrogen in the layer diffuses to the interface between the gate dielectric layer and the substrate, thereby improving the problem of interface defects, and by adjusting the doping amount of the nitrogen doping treatment accordingly, and matching with the target physical thickness of the gate dielectric layer , so that the electrical thickness of the gate dielectric layer is equal to the target electrical thickness; in summary, the embodiments of the present invention can improve the interface between the gate dielectric layer and the substrate while ensuring that the electrical thickness of the gate dielectric layer meets the electrical requirements. The interfacial defects can improve the performance of the semiconductor structure.

In order to make the above objects, features and advantages of the embodiments of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

8 to 9 are schematic structural diagrams corresponding to each step in an embodiment of the method for forming a gate dielectric layer of the present invention.

Referring to Figure 8, a substrate 10 is provided.

The substrate 10 is used to provide a process platform for the subsequent formation of the gate dielectric layer.

In this embodiment, the substrate 10 is used to form a planar field effect transistor, and the substrate 10 only includes a substrate (not shown). In other embodiments, when the substrate is used to form a fin field effect transistor (FinFET), the substrate correspondingly includes a substrate and a fin protruding from the substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or an insulator other types of substrates such as germanium substrates.

Continuing to refer to FIG. 8 , a gate dielectric layer 11 is formed on the substrate 10 , and the gate dielectric layer 11 has a target physical thickness and a target electrical thickness.

The physical thickness refers to the distance from the top surface of the gate dielectric layer 11 to the surface of the substrate 100 along the direction perpendicular to the surface of the substrate 100; In the nitrogen doping process, the electrical thickness refers to the equivalent oxide thickness (EOT) of the gate dielectric layer 11 after the nitrogen doping process.

The gate dielectric layer 11 has a target physical thickness and a target electrical thickness, so that the physical thickness of the gate dielectric layer 11 satisfies the miniaturization and high integration of the device, while improving the performance of the semiconductor device, for example: reducing the Through current, improve the stability and reliability of the device.

In this embodiment, the gate dielectric layer 10 is a gate oxide (GOX) layer. The material of the gate dielectric layer 10 is correspondingly silicon oxide.

It should be noted that in the field of semiconductors, the key electrical parameters of MOSFET devices (such as threshold voltage Vt, drive current, etc.) usually depend on the gate capacitance. According to the capacitance formula (C=ε ₀ εA/t), in order to ensure the gate The pole structure has the same control ability for the channel to make the electrical parameters of the MOSFET device meet the requirements. When other conditions remain unchanged, when the thickness t of the gate dielectric layer 11 is increased, the dielectric constant of the gate dielectric layer 11 material needs to be increased accordingly. ε. Among them, ε ₀ is the vacuum dielectric constant, and A is the contact area between the gate electrode and the gate dielectric layer 11 .

Subsequent steps further include performing nitrogen doping treatment on the gate dielectric layer 11 , and the nitrogen doping treatment is suitable for increasing the dielectric constant ε of the material of the gate dielectric layer 11 , that is, when increasing the physical thickness of the gate dielectric layer 11 t, the doping dose of the nitrogen doping treatment needs to be increased accordingly.

It should also be noted that the control ability of the gate structure on the channel can be characterized by the electrical thickness of the gate dielectric layer 11 , and multiple key electrical parameters of the MOSFET device can be used to characterize the target electrical thickness of the gate dielectric layer 11 . In this embodiment, the target electrical thickness is characterized by the target threshold voltage of the MOSFET device. In other embodiments, other key electrical parameters may also be used to characterize.

To this end, in this embodiment, before forming the gate dielectric layer 11, the method further includes: obtaining the functional relationship between the physical thickness of the gate dielectric layer 11 and the doping dose of the nitrogen doping treatment under the condition of the target threshold voltage; forming gate dielectric layers 11 with different thicknesses, and determine the corresponding doping doses of the gate dielectric layers 11 with different thicknesses; and detect the diffusion degree of nitrogen in the corresponding gate dielectric layers 11 under each doping dose condition. Wherein, the target threshold voltage refers to the target threshold voltage of the formed MOSFET device, and the target threshold voltage may be determined according to the performance requirements of the MOSFET device.

Specifically, obtaining the functional relationship between the physical thickness of the gate dielectric layer 11 and the doping dose of the nitrogen doping treatment under the condition of the target threshold voltage includes: firstly determining the target threshold voltage; under the condition of the target threshold voltage, for a certain The gate dielectric layer 11 of the physical thickness is subjected to multiple groups of nitrogen doping treatments with different doping doses, and the actual threshold voltage of the device corresponding to each gate dielectric layer 11 is measured, and the actual threshold voltage is selected to satisfy the condition that the actual threshold voltage is equal to the target threshold voltage. , the physical thickness of the gate dielectric layer 11 and the corresponding doping dose data; under the condition of the same target threshold voltage, changing the physical thickness of the gate dielectric layer 11, and simultaneously performing multiple groups of nitrogen doping treatments with different doping doses, The threshold voltage of the device corresponding to each gate dielectric layer 11 is measured, and the physical thickness of the gate dielectric layer 11 and the corresponding dopant dose data are selected under the condition that the actual threshold voltage is equal to the target threshold voltage.

The above steps are repeated to obtain the functional relationship between the physical thickness of the gate dielectric layer 11 and the corresponding dopant dose under multiple sets of different target threshold voltage conditions.

Gate dielectric layers 11 with different thicknesses are formed, and the corresponding doping doses of the gate dielectric layers 11 with different thicknesses are determined. Specifically, according to the functional relationship obtained above, the doping doses corresponding to the gate dielectric layers 11 with different thicknesses are determined.

The diffusion degree of nitrogen in the corresponding gate dielectric layer 11 is detected under the condition of each doping dose. Specifically, the diffusion degree of nitrogen in the corresponding gate dielectric layer 11 can be detected by detecting the concentration of nitrogen on the surface of the substrate 10 or measuring the gate leakage current. Data sets of actual threshold voltage, physical thickness of gate dielectric layer 11 and corresponding dopant dose of nitrogen doping treatment are selected that satisfy the following conditions: the actual threshold voltage is equal to the target threshold voltage, and nitrogen is not diffused to the surface of substrate 10 .

It should be noted that the threshold voltage is usually in one-to-one correspondence with the electrical thickness. By obtaining the value of the threshold voltage, the corresponding electrical thickness can be calculated, and the threshold voltage is a commonly used method in the semiconductor field to characterize the electrical properties of semiconductor structures. Therefore, in this embodiment, the relationship between the physical thickness of the gate dielectric layer 11 and the doping amount of the nitrogen doping treatment under the condition of obtaining the target threshold voltage is taken as an example. In other embodiments, the relationship between the physical thickness of the gate dielectric layer and the doping dose of the nitrogen doping treatment can also be obtained under other target electrical parameter conditions, such as driving current and the like.

Referring to FIG. 9 , nitrogen doping treatment 20 is performed on the gate dielectric layer 11 , and the doping dose of the nitrogen doping treatment 20 is adjusted so that the electrical thickness of the gate dielectric layer 11 is equal to the target electrical thickness. Wherein, the target physical thickness of the gate dielectric layer 11 satisfies that after the nitrogen doping treatment 20, the longitudinal distance that nitrogen diffuses in the gate dielectric layer 11 to the surface of the substrate 10 is smaller than the target physical thickness.

In the subsequent process, the step of high temperature treatment is usually included. By making the target physical thickness of the gate dielectric layer 11 meet the above conditions, the nitrogen in the gate dielectric layer 11 can be prevented from diffusing into the gate dielectric layer 11 and the substrate. 10 at the interface, thereby improving the problem of interface defects, and by adjusting the doping dose of the nitrogen doping treatment 20 accordingly, and matching with the target physical thickness of the gate dielectric layer 11 (for example: when increasing the When the physical thickness is increased, the doping dose of the nitrogen doping treatment 20 needs to be increased accordingly, so that the electrical thickness of the gate dielectric layer 11 is equal to the target electrical thickness; in conclusion, the embodiment of the present invention can ensure the gate dielectric layer 11 While meeting the electrical requirements, the electrical thickness of 1000 Å improves the interface defects at the interface between the gate dielectric layer 11 and the substrate 100, and improves the performance of the semiconductor structure.

It should be noted that, under the condition that the physical thickness remains unchanged, the larger the dielectric constant of the gate dielectric layer 11 is, the smaller the equivalent oxide thickness is, and the size of the transistor can be further reduced according to Moore's Law.

In this embodiment, the material of the gate dielectric layer 11 is silicon oxide, and the dielectric constant of the silicon oxide material is smaller than that of the silicon nitride material. By performing nitrogen doping on the gate dielectric layer 11 , the nitrogen content in the gate dielectric layer 11 is increased, the dielectric constant of the gate dielectric layer 11 can be increased, and the gate dielectric layer 11 has a higher dielectric constant. The electrical thickness is equal to the target electrical thickness, so as to meet the miniaturization of the device, ensure that the electrical performance of the device meets the process requirements, and improve the reliability and stability of the device.

In this embodiment, the step of performing the nitrogen doping treatment 20 on the gate dielectric layer 11 includes: determining the doping amount of the nitrogen doping treatment 20 according to the functional relationship and the target physical thickness of the gate dielectric layer 11 .

Specifically, first determine the target threshold voltage of the gate dielectric layer 11 , under the condition of the target threshold voltage, according to the aforementioned functional relationship, the target physical thickness of the gate dielectric layer 11 , and the target threshold voltage of the gate dielectric layer 11 The conditions to be met by the physical thickness are determined under the appropriate target physical thickness and the nitrogen doping dose corresponding to the target physical thickness; according to the obtained nitrogen doping dose, the gate dielectric layer 11 is subjected to nitrogen doping treatment 20 .

In this embodiment, the nitrogen doping treatment 20 is performed by a decoupled plasma nitridation (Decoupled Plasma Nitridation, DPN) process. The process temperature of the decoupling plasma nitridation process is lower, which is beneficial to reduce the probability of nitrogen diffusing to the surface of the substrate 10, and at the same time, the gate dielectric layer 11 has a higher nitrogen content, so as to obtain better EOT, which is beneficial to Improve gate leakage current and improve carrier mobility.

10 to 16 are schematic structural diagrams corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to FIG. 10 , a gate dielectric layer is formed on a substrate 100 by using the foregoing method for forming a gate dielectric layer, and the gate dielectric layer is suitable as a first gate dielectric layer 110 , wherein the substrate 100 includes a peripheral region A, a first gate dielectric layer The core region B and the second core region C, the working voltage of the second core region C is greater than the working voltage of the first core region B.

By using the foregoing method for forming a gate dielectric layer, a first gate dielectric layer 110 is formed on the substrate 100, so that the electrical thickness of the first gate dielectric layer 110 is equal to the target electrical thickness, and the first gate dielectric layer The target physical thickness of 110 satisfies: the longitudinal distance of nitrogen atoms in the first gate dielectric layer 110 diffusing to the surface of the substrate 100 in the first gate dielectric layer 110 is smaller than the target physical thickness, so that in the subsequent high temperature In the processing step, nitrogen in the first gate dielectric layer 110 can be prevented from diffusing to the interface between the first gate dielectric layer 110 and the substrate 100, so as to ensure that the electrical thickness of the first gate dielectric layer 110 satisfies While meeting the electrical requirements, the interface defects at the interface between the first gate dielectric layer 110 and the substrate 100 are improved, and the performance of the semiconductor structure is improved.

The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

For the description of the substrate 100, reference may be made to the foregoing specific description of the substrate, which is not repeated in this embodiment.

The peripheral area A is used to form input/output devices (I/O devices). Among them, the input/output device is generally a device used when the chip interacts with the external interface, and the working voltage of the input/output device is generally relatively high.

The first core region B is used to form a first core device, the second core region C is used to form a second core device, and the operating voltage of the second core device is greater than that of the first core device operating voltage. Among them, the core device generally refers to the device used inside the chip, the working voltage of the core device is generally relatively low, and the working voltage of the core device is usually much lower than that of the input/output device.

In this embodiment, the first gate dielectric layer 110 is used as a gate dielectric layer of the input/output device.

In this embodiment, the first gate dielectric layer 110 is formed by using the foregoing method for forming the gate dielectric layer, which is beneficial to make the electrical thickness of the first gate dielectric layer 110 meet the process requirements of the input/output device, and at the same time, The interface defects at the interface between the first gate dielectric layer 110 and the substrate 100 are improved, and the performance of the input/output device is improved.

In this embodiment, the first gate dielectric layer 110 is a gate oxide layer. The material of the first gate dielectric layer 110 is correspondingly silicon oxide.

In this embodiment, in the step of performing the nitrogen doping treatment, the target physical thickness of the first gate dielectric layer 110 is greater than a preset physical thickness. Wherein, the preset physical thickness refers to: when a double gate oxide layer process is adopted, that is, when the substrate only includes one kind of peripheral region and one kind of core region, the first gate dielectric The physical thickness of the layer.

By making the target physical thickness larger than the preset physical thickness, the longitudinal distance from the top surface of the first gate dielectric layer 110 to the surface of the substrate 100 is increased, thereby reducing the nitrogen concentration in the first gate dielectric layer 110 The probability of diffusing to the surface of the substrate 100 in the subsequent high temperature treatment step can improve the interface defects at the interface between the first gate dielectric layer 110 and the substrate 100 .

It should be noted that, the difference between the target physical thickness and the preset physical thickness should not be too small. If the difference is too small, the effect of reducing the probability of the diffusion of nitrogen in the first gate dielectric layer 110 to the surface of the substrate 100 is not significant, or it is difficult to reduce the diffusion of nitrogen in the first gate dielectric layer 110 to the substrate 100 The role of surface probability. Therefore, in this embodiment, the difference between the target physical thickness and the preset physical thickness is at least 20 angstroms.

In this embodiment, in order to make the formed semiconductor structure meet the requirements of device miniaturization and thinning, and save the time and cost of forming the first gate dielectric layer 110, the physical thickness of the first gate dielectric layer 110 Nor should it be too large. Specifically, the difference between the target physical thickness and the preset physical thickness is 20 angstroms to 40 angstroms.

In this embodiment, in the step of performing the nitrogen doping treatment, the doping dose of the nitrogen doping treatment is higher than the preset doping dose. Wherein, the preset doping dose refers to: when the double gate oxide layer technology is adopted, that is, when the substrate only includes one kind of peripheral region and one kind of core region, the doping amount of nitrogen doping treatment Miscellaneous doses.

In this embodiment, the target physical thickness of the first gate dielectric layer 110 is greater than the preset physical thickness. If the doping dose of the nitrogen doping treatment is not adjusted, the nitrogen content in the first gate dielectric layer 110 is likely to be low, so that the dielectric constant of the first gate dielectric layer 110 is also low. The electrical thickness of the first gate dielectric layer 110 is difficult to meet the requirements of the target electrical thickness.

By making the doping dose of the nitrogen doping treatment higher than the preset doping dose, it can be matched with the target physical thickness, and the interface defects at the interface of the first gate dielectric layer 110 and the substrate 100 can be improved at the same time. , to ensure that the electrical thickness of the first gate dielectric layer 110 is equal to the target electrical thickness, so that the electrical thickness of the first gate dielectric layer 110 meets electrical requirements.

It should be noted that, the difference between the doping dose and the preset doping dose should not be too small. If the difference is too small, since the target physical thickness of the first gate dielectric layer 110 is greater than the preset physical thickness, the nitrogen content in the first gate dielectric layer 110 is likely to be too low, which in turn causes the first gate dielectric layer 110 to have an excessively low nitrogen content. The electrical thickness of the gate dielectric layer 110 is difficult to meet electrical requirements. In this embodiment, the difference between the target physical thickness and the preset physical thickness is at least 20 angstroms. Correspondingly, the difference between the doping dose and the preset doping dose is at least 1E15 atoms per atom square centimeters.

Specifically, the difference between the target physical thickness and the preset physical thickness is 20 angstroms to 40 angstroms. If the difference is too large, the nitrogen content in the first gate dielectric layer 110 is too high, which easily increases the probability of nitrogen in the first gate dielectric layer 110 diffusing to the surface of the substrate 100 , making it difficult to improve the first gate dielectric layer 110 . The role of interface defects at the interface between the gate dielectric layer 110 and the substrate 100 . Therefore, in this embodiment, the difference between the dopant dose and the target physical thickness of the first gate dielectric layer 110 and the preset physical thickness is matched, and the difference between the dopant dose and the preset dopant dose Values range from 1E15 atoms per square centimeter to 5E15 atoms per square centimeter.

It should also be noted that, after the nitrogen doping treatment is performed, the method further includes: performing an annealing treatment on the first gate dielectric layer 110 . Through the annealing treatment, the lattice defects generated in the step of the nitrogen doping treatment are repaired, and the doped nitrogen atoms are also activated at the same time.

Wherein, by making the target physical thickness larger than the preset physical thickness, the longitudinal distance from the top surface of the first gate dielectric layer 110 to the surface of the substrate 100 is increased, and the diffusion of nitrogen to the surface of the substrate 100 is correspondingly reduced. Therefore, the process temperature of the annealing treatment can be appropriately increased to improve the process effect of the annealing treatment.

However, the process temperature of the annealing treatment should not be too low nor too high. If the process temperature of the annealing treatment is too low, the effect of the annealing treatment for repairing lattice defects and activating nitrogen atoms is poor; if the process temperature of the annealing treatment is too high, it is easy to increase the first gate dielectric Diffusion of nitrogen in layer 110 , thereby increasing the probability of nitrogen diffusing to the surface of substrate 100 . Therefore, in this embodiment, the process temperature of the annealing treatment is 1000°C to 1150°C.

In this embodiment, a rapid thermal annealing (Rapid Thermal Anneal, RTA) process is used to perform the annealing treatment.

Referring to FIG. 11 to FIG. 12 , the first gate dielectric layer 110 on the second core region C is removed.

By removing the first gate dielectric layer 110 on the second core region C, the surface of the substrate 100 of the second core region C is exposed, and a second gate is subsequently formed on the substrate 100 of the second core region C Prepare the dielectric layer.

Specifically, the step of removing the first gate dielectric layer 110 on the second core region C includes: forming a first mask layer 101 on the substrate 100 (as shown in FIG. 11 ), the first mask layer The layer 101 exposes the first gate dielectric layer 110 on the substrate 100 of the second core region C; using the first mask layer 101 as a mask, remove the first gate dielectric layer 110 on the second core region C ; After removing the first gate dielectric layer 110 on the second core region C, remove the first mask layer 101 .

In this embodiment, the material of the first mask layer 101 is photoresist. The photoresist material is a commonly used mask material in the semiconductor process, and the process for forming the first mask layer 101 is a commonly used photolithography process in the semiconductor field, with high process compatibility.

In this embodiment, the first gate dielectric layer 110 on the second core region C is removed by a wet etching process. The wet etching process has simple operation and low process cost.

Specifically, the wet etching process is performed using a dilute solution of hydrofluoric acid.

In this embodiment, the target physical thickness of the first gate dielectric layer 110 is greater than the preset physical thickness. Therefore, according to process requirements, the concentration of the hydrofluoric acid dilution solution can be appropriately increased, thereby increasing the etching rate of the wet etching process, shortening the etching time, and improving the production efficiency. In other embodiments, according to actual process requirements, the time of the wet etching process may also be appropriately increased.

After removing the first gate dielectric layer 110 on the second core region C, the method further includes: removing the first mask layer 101 by using an ashing process.

Referring to FIG. 13 , after removing the first gate dielectric layer 110 on the second core region C, a second gate dielectric layer 120 is formed on the substrate 100 of the second core region C. The second gate dielectric layer 120 is smaller than the thickness of the first gate dielectric layer 110 .

The second gate dielectric layer 120 is used as a gate dielectric layer of the second core device.

In the semiconductor field, in order to ensure that the driving current of the device meets the process requirements, as well as the reliability and stability of the breakdown voltage of the device, the larger the operating voltage of the device, the larger the required thickness of the gate dielectric layer is usually. The operating voltage of the second core device is lower than the operating voltage of the input/output device, therefore, the thickness of the second gate dielectric layer 120 is smaller than the thickness of the first gate dielectric layer 110 .

In this embodiment, the formation method introduces a triple gate oxide layer process, and the second gate dielectric layer 120 is used as a TGO layer.

In this embodiment, the second gate dielectric layer 120 is a gate oxide layer, and the material of the second gate dielectric layer 120 is silicon oxide.

In this embodiment, the second gate dielectric layer 120 is formed by a thermal oxidation growth process. The thermal oxidation growth process is usually in a high temperature environment, using the oxidation reaction between silicon and an oxidant to form a silicon oxide film on the substrate 100, the process operation is simple, and the thickness consistency and compactness of the formed silicon oxide film are good. , which is beneficial to improve the film quality of the second gate dielectric layer 120 .

In this embodiment, the first gate dielectric layer 110 is doped with nitrogen atoms, and the doped nitrogen atoms are easily diffused at high temperature. The first gate dielectric layer 110 is formed by using the aforementioned method for forming the gate dielectric layer. Therefore, after passing through the high temperature environment for forming the second gate dielectric layer 120, nitrogen in the first gate dielectric layer 110 diffuses into the The probability of the surface of the substrate 100 is low, thereby improving the interface defects at the interface between the first gate dielectric layer 110 and the substrate 100 .

Specifically, the thermal oxidation growth process may be performed by a water vapor oxidation process, a dry oxygen process or a wet oxygen process.

Referring to FIG. 14 to FIG. 15 , after the second gate dielectric layer 120 is formed, the first gate dielectric layer 110 on the substrate 100 in the first core region B is removed.

By removing the first gate dielectric layer 110 on the substrate 100 of the first core region B, the surface of the substrate 100 of the first core region B is exposed, so as to form the first gate dielectric layer 100 on the substrate 100 of the first core region B subsequently. Prepare the triple gate dielectric layer.

Specifically, the step of removing the first gate dielectric layer 110 on the substrate 100 of the first core region B includes: forming a second mask layer 102 on the substrate 100 (as shown in FIG. 14 ), the second The mask layer 102 exposes the first gate dielectric layer 110 on the substrate 100 of the first core region B; using the second mask layer 102 as a mask, the first gate dielectric layer on the first core region B is removed layer 110; after removing the first gate dielectric layer 110 on the first core region B, the second mask layer 102 is removed.

In this embodiment, the material of the second mask layer 102 is photoresist. For the detailed description of the second mask layer 102 , reference may be made to the foregoing description of the first mask layer 101 , which will not be repeated here.

In this embodiment, the first gate dielectric layer 110 on the substrate 100 of the first core region B is removed by a wet etching process. The wet etching process has simple operation and low process cost.

Specifically, the wet etching process is performed using a dilute solution of hydrofluoric acid. For the specific description of the wet etching process, reference may be made to the foregoing description of the wet etching process for removing the first gate dielectric layer 110 on the second core region C, which will not be repeated here.

In this embodiment, the process of removing the first gate dielectric layer 110 on the substrate 100 of the first core region B is the same as the process of removing the first gate dielectric layer 110 on the second core region C. This will not be repeated here.

After removing the first gate dielectric layer 110 on the substrate 100 of the first core region B, the second mask layer 102 is removed by an ashing process.

Referring to FIG. 16 , after removing the first gate dielectric layer 110 on the substrate 100 of the first core region B, a third gate dielectric layer 130 is formed on the substrate 100 of the first core region B. The third gate dielectric The thickness of the layer 130 is smaller than the thickness of the second gate dielectric layer 120 .

The third gate dielectric layer 130 is used as the gate dielectric layer of the first core device.

The working voltage of the first core device is lower than the working voltage of the second core device, to ensure that the driving current of the device meets the process requirements, and the reliability and stability of the breakdown voltage of the device, the third gate dielectric layer 130 is smaller than the thickness of the second gate dielectric layer 120 .

In this embodiment, the third gate dielectric layer 130 is a gate oxide layer, and the material of the third gate dielectric layer 130 is silicon oxide.

In this embodiment, the third gate dielectric layer 130 is formed by a thermal oxidation growth process. The thermal oxidation growth process is usually in a high temperature environment, using the oxidation reaction between silicon and an oxidant to form a silicon oxide film on the substrate 100, the process operation is simple, and the thickness consistency and density of the formed silicon oxide film are good. , which is beneficial to improve the film quality of the third gate dielectric layer 130 .

In this embodiment, the first gate dielectric layer 110 is doped with nitrogen atoms, and the doped nitrogen atoms are easily diffused at high temperature. The first gate dielectric layer 110 is formed by using the aforementioned method for forming a gate dielectric layer. Therefore, after passing through the high temperature environment for forming the third gate dielectric layer 130, nitrogen in the first gate dielectric layer 110 diffuses into the The probability of the surface of the substrate 100 is low, thereby improving the interface defects at the interface between the first gate dielectric layer 110 and the substrate 100 .

Specifically, the thermal oxidation growth process may be performed by a water vapor oxidation process, a dry oxygen process or a wet oxygen process.

Referring to FIG. 17 , the SIMS of the semiconductor structure formed by the conventional process, the semiconductor structure formed by the prior art, and the semiconductor structure formed by the embodiment of the present invention, the doping concentration of nitrogen varies with the doping depth are respectively shown (Secondary ion mass spectrometry) analysis diagram, the abscissa represents the doping depth, and the ordinate represents the nitrogen doping concentration. Among them, N-DGO is a semiconductor structure formed by a traditional process, N-TGO is a semiconductor structure formed by using the prior art, and N-TGO new is a semiconductor structure formed by an embodiment of the present invention. It can be seen from the figure that when approaching the substrate surface, in the semiconductor structure formed by the prior art, the nitrogen doping concentration is still relatively large, and the nitrogen contacts the substrate surface, which is easy to produce interface defects; while the change trend of the N-TGO new curve Similar to the change trend of the N-DGO curve, when it is close to the surface of the substrate 100, the doping concentration of N-TGO new is zero, that is to say, in the semiconductor structure formed by the embodiment of the present invention, nitrogen is not diffused into the substrate. 100 surfaces.

Referring to FIG. 18 in conjunction with FIG. 18 , a relationship diagram of saturation current (IDSAT) and off-state leakage current (IOFF) of a semiconductor structure formed by a conventional process and a semiconductor structure formed by an embodiment of the present invention is shown. Wherein, DGO is a semiconductor structure formed by a traditional process, and new TGO is a semiconductor structure formed by the embodiment of the present invention. It can be seen from the figure that, under the same saturation current, the off-state leakage current values of the semiconductor structure formed by the embodiment of the present invention and the semiconductor structure formed by the traditional process are relatively close, and the electrical performance of the semiconductor structure formed by the embodiment of the present invention can satisfy the process requirements.

Correspondingly, the present invention also provides a semiconductor structure formed by the aforementioned forming method. Referring to FIG. 16, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100, the substrate 100 includes a peripheral area A, a first core area B and a second core area C, the operating voltage of the second core area C is greater than that of the first core area B voltage; the first gate dielectric layer 110 is located on the substrate 100 in the peripheral region A, the first gate dielectric layer 110 is doped with nitrogen ions, and the nitrogen ions are located on the first gate above the substrate 100 In the dielectric layer 110; the second gate dielectric layer 120, located on the substrate 100 of the second core region C, the thickness of the second gate dielectric layer 120 is smaller than the thickness of the first gate dielectric layer 110; the third gate dielectric layer 120 The dielectric layer 130 is located on the substrate 100 of the first core region B, and the thickness of the third gate dielectric layer 130 is smaller than that of the second gate dielectric layer 120 .

The nitrogen ions are located in the first gate dielectric layer 110 above the substrate 100, and the nitrogen ions do not contact the surface of the substrate 100, so as to ensure that the electrical thickness of the first gate dielectric layer 110 satisfies the electrical properties While meeting the requirements, the interface defects at the interface between the first gate dielectric layer 110 and the substrate 100 are improved, and the electrical performance of the semiconductor structure is improved.

In this embodiment, the substrate 100 is used to form a planar field effect transistor, and the substrate 100 only includes a substrate (not shown). In other embodiments, when the substrate is used to form a fin field effect transistor, the substrate correspondingly includes a substrate and a fin protruding from the substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or an insulator other types of substrates such as germanium substrates.

The peripheral area A is used to form input/output devices. Among them, the input/output device is generally a device used when the chip interacts with the external interface, and the working voltage of the input/output device is generally relatively high.

The first core region B is used to form a first core device, the second core region C is used to form a second core device, and the operating voltage of the second core device is greater than the operating voltage of the first core device . Among them, the core device generally refers to the device used inside the chip, the working voltage of the core device is generally relatively low, and the working voltage of the core device is usually much lower than that of the input/output device.

In this embodiment, the first gate dielectric layer 110 is used as a gate dielectric layer of the input/output device.

In this embodiment, the first gate dielectric layer 110 is formed by using the foregoing method for forming the gate dielectric layer, which is beneficial to make the electrical thickness of the first gate dielectric layer 110 meet the process requirements of the input/output device, and at the same time, The interface defects at the interface between the first gate dielectric layer 110 and the substrate 100 are improved, and the performance of the input/output device is improved.

In this embodiment, the first gate dielectric layer 110 is a gate oxide layer. The material of the first gate dielectric layer 110 is correspondingly silicon oxide.

The second gate dielectric layer 120 is used as a gate dielectric layer of the second core device.

In the semiconductor field, in order to ensure that the driving current of the device meets the process requirements, as well as the reliability and stability of the breakdown voltage of the device, the larger the operating voltage of the device, the larger the required thickness of the gate dielectric layer is usually. The operating voltage of the second core device is lower than the operating voltage of the input/output device, therefore, the thickness of the second gate dielectric layer 120 is smaller than the thickness of the first gate dielectric layer 110 .

In this embodiment, the second gate dielectric layer 120 is a gate oxide layer, and the material of the second gate dielectric layer 120 is silicon oxide.

The third gate dielectric layer 130 is used as the gate dielectric layer of the first core device.

The working voltage of the first core device is lower than the working voltage of the second core device, so as to ensure that the driving current of the device meets the process requirements, and the reliability and stability of the breakdown voltage of the device, and the third gate dielectric layer The thickness of 130 is smaller than the thickness of the second gate dielectric layer 120 .

In this embodiment, the third gate dielectric layer 130 is a gate oxide layer, and the material of the third gate dielectric layer 130 is silicon oxide.

The semiconductor structure may be formed by the formation methods described in the foregoing embodiments, or may be formed by other formation methods. For the specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated in this embodiment.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (18)

1. A method for forming a gate dielectric layer, comprising: provide a base; forming a gate dielectric layer on the substrate, the gate dielectric layer having a target physical thickness and a target electrical thickness; Nitrogen doping is performed on the gate dielectric layer, and by adjusting the doping dose of the nitrogen doping treatment, the electrical thickness of the gate dielectric layer is adapted to be equal to the target electrical thickness; Wherein, the target physical thickness of the gate dielectric layer satisfies: after the nitrogen doping treatment, the longitudinal distance that nitrogen diffuses in the gate dielectric layer to the surface of the substrate is less than the target physical thickness. 2 . The method for forming a gate dielectric layer according to claim 1 , wherein before forming the gate dielectric layer, the method further comprises: obtaining, under the condition of a target threshold voltage, the physical thickness of the gate dielectric layer and the The functional relationship of the doping dose of the nitrogen doping treatment; forming gate dielectric layers with different thicknesses, and determining the corresponding doping doses of the gate dielectric layers with different thicknesses; detecting under the conditions of each doping dose, nitrogen in the corresponding gate dielectric layer the degree of diffusion in the dielectric layer; The step of performing nitrogen doping treatment on the gate dielectric layer includes: determining a dopant amount of the nitrogen doping treatment according to the functional relationship and a target physical thickness of the gate dielectric layer. 3 . The method for forming a gate dielectric layer according to claim 1 , wherein the nitrogen doping treatment is performed by a decoupling plasma nitridation process. 4 . 4. The method for forming a gate dielectric layer according to claim 1, wherein in the step of forming the gate dielectric layer, the gate dielectric layer is a gate oxide layer. 5. A method for forming a semiconductor structure, comprising: Using the method for forming a gate dielectric layer according to any one of claims 1 to 4, a gate dielectric layer is formed on a substrate, and the gate dielectric layer is suitable as the first gate dielectric layer, wherein the substrate includes a peripheral region , a first core region and a second core region, the working voltage of the second core region is greater than the working voltage of the first core region; removing the first gate dielectric layer on the second core region; After removing the first gate dielectric layer on the second core region, a second gate dielectric layer is formed on the substrate of the second core region, and the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer thickness of; after forming the second gate dielectric layer, removing the first gate dielectric layer on the substrate of the first core region; After removing the first gate dielectric layer on the substrate of the first core region, a third gate dielectric layer is formed on the substrate of the first core region, and the thickness of the third gate dielectric layer is smaller than that of the second gate dielectric layer thickness. 6 . The method for forming a semiconductor structure according to claim 5 , wherein, in the step of forming the first gate dielectric layer, the target physical thickness of the first gate dielectric layer is greater than a preset physical thickness. 7 . 7 . The method of claim 6 , wherein the difference between the target physical thickness and the preset physical thickness is at least 20 angstroms. 8 . 8 . The method of claim 6 , wherein the difference between the target physical thickness and the preset physical thickness is 20 angstroms to 40 angstroms. 9 . 9 . The method for forming a semiconductor structure according to claim 5 , wherein in the step of performing nitrogen doping treatment on the first gate dielectric layer, the doping dose of the nitrogen doping treatment is higher than a preset doping amount. 10 . dose. 10 . The method of claim 9 , wherein the difference between the dopant dose and the preset dopant dose is at least 1E15 atoms per square centimeter. 11 . 11 . The method for forming a semiconductor structure according to claim 9 , wherein the difference between the doping dose and the preset doping dose is 1E15 atoms per square centimeter to 5E15 atoms per square centimeter. 12 . 12 . The method for forming a semiconductor structure according to claim 5 , wherein a wet etching process is used to remove the first gate dielectric layer on the substrate of the first core region. 13 . 13 . The method for forming a semiconductor structure according to claim 5 , wherein the first gate dielectric layer on the second core region substrate is removed by a wet etching process. 14 . 14. The method for forming a semiconductor structure according to claim 5, wherein the second gate dielectric layer is formed by a thermal oxidation growth process. 15 . The method for forming a semiconductor structure according to claim 5 , wherein the third gate dielectric layer is formed by a thermal oxidation growth process. 16 . 16 . The method for forming a semiconductor structure according to claim 5 , wherein after the nitrogen doping treatment is performed and before removing the first gate dielectric layer on the second core region, the method further comprises: performing an annealing treatment. 17 . 17 . The method for forming a semiconductor structure according to claim 16 , wherein the process temperature of the annealing treatment ranges from 1000° C. to 1150° C. 18 . 18. A semiconductor structure formed by the forming method according to any one of claims 5 to 17, characterized in that, comprising: a substrate, the substrate includes a peripheral region, a first core region and a second core region, the working voltage of the second core region is greater than that of the first core region; a first gate dielectric layer, located on the substrate of the peripheral region, the first gate dielectric layer is doped with nitrogen ions, and the nitrogen ions are located in the first gate dielectric layer above the substrate; a second gate dielectric layer, located on the substrate of the second core region, the thickness of the second gate dielectric layer is smaller than the thickness of the first gate dielectric layer; A third gate dielectric layer is located on the substrate of the first core region, and the thickness of the third gate dielectric layer is smaller than that of the second gate dielectric layer.

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