CN112614898B - Transverse conduction type GaN mixed pn Schottky power diode and preparation method thereof - Google Patents
Transverse conduction type GaN mixed pn Schottky power diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910002704 AlGaN Inorganic materials 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229910000749 nitanium Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
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- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
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- 230000015556 catabolic process Effects 0.000 description 6
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
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- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
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- 238000001755 magnetron sputter deposition Methods 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/60—Schottky-barrier diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D8/00—Diodes
- H10D8/01—Manufacture or treatment
- H10D8/051—Manufacture or treatment of Schottky diodes
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Abstract
The invention discloses a transverse conduction type GaN mixed pn Schottky power diode and a preparation method thereof, wherein the diode comprises a substrate layer, a stress buffer layer, a GaN epitaxial layer and a p-GaN buried layer which are sequentially arranged from bottom to top, wherein a GaN channel layer is arranged at the part, uncovered by the p-GaN buried layer, of the upper surface of the GaN epitaxial layer, and the GaN channel layer also covers a part of the upper surface of the p-GaN buried layer; the upper surface of the GaN channel layer is provided with a barrier layer, both sides of the upper surface of the barrier layer are respectively provided with a p-GaN cap layer and an ohmic contact electrode, the p-GaN cap layer is positioned above the p-GaN buried layer, and Schottky electrodes are arranged on the upper surface of the p-GaN cap layer and the part of the upper surface of the p-GaN buried layer, which is not covered by the GaN channel layer. On the basis of reducing the on-voltage of the Schottky diode by the groove anode structure, the p-GaN buried layer is utilized to form the pn junction diode connected in parallel, the anti-surge current capability is improved, the on-resistance of the device is reduced, and meanwhile, the reverse voltage-withstanding capability is improved by the p-GaN cap layer.
Description
Technical Field
The invention belongs to the technical field of electronic devices, and particularly relates to a transverse conduction type GaN mixed pn Schottky power diode and a preparation method thereof.
Background
AlGaN/GaN based diodes are very promising for power switching devices due to their high electron mobility, high critical breakdown field and high saturated electron velocity caused by two-dimensional electron gas (2 DEG). In general, power rectifying diodes trade-off between two contradictory characteristics, namely high off-state withstand voltage and low forward losses. Conventional planar structure AlGaN/GaN schottky diodes (SchottkyBarrierDiode, SBD) typically exhibit a high forward turn-on voltage, which results in considerable on-state losses. The positive on-state voltage can be effectively reduced by selecting the anode metal with lower work function, but the reverse off-state leakage current can be increased at the same time.
Recent studies have shown that AlGaN/GaN based trench structure anode schottky barrier diodes can effectively balance on-voltage and off-state withstand voltage, but sharp corners at the trench bottom increase the risk of electric field concentration and early breakdown under high reverse bias. In addition, when current overshoot or oscillation occurs, power devices typically experience high inrush currents, whereas conventional schottky diodes have relatively weak inrush current resistance, and it is necessary to design new device structures.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a transverse conduction type GaN mixed pn Schottky power diode and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
One aspect of the present invention provides a lateral conduction GaN hybrid pn schottky power diode, comprising a substrate layer, a stress buffer layer, a GaN epitaxial layer, and a p-GaN buried layer sequentially disposed from bottom to top, wherein,
A GaN channel layer is arranged on the part, uncovered by the p-GaN buried layer, of the upper surface of the GaN epitaxial layer, and the GaN channel layer also covers a part of the upper surface of the p-GaN buried layer;
A barrier layer is arranged on the upper surface of the GaN channel layer;
The two sides of the upper surface of the barrier layer are respectively provided with a p-GaN cap layer and an ohmic contact electrode, and the p-GaN cap layer is positioned above the p-GaN buried layer;
The upper surface of the p-GaN cap layer and the part of the upper surface of the p-GaN buried layer, which is not covered by the GaN channel layer, are provided with Schottky electrodes.
In one embodiment of the invention, the schottky electrode has an L-shaped cross section and comprises a transverse portion and a longitudinal portion, wherein the transverse portion covers the upper surface of the p-GaN cap layer, the longitudinal portion is positioned on the upper surface of the p-GaN buried layer, and the inner side wall of the longitudinal portion is sequentially contacted with the side wall of the GaN channel layer, the side wall of the barrier layer and the side wall of the p-GaN cap layer from bottom to top.
In one embodiment of the invention, the Schottky electrode forms ohmic contact with the p-GaN buried layer and the p-GaN cap layer, and forms Schottky contact with the GaN channel layer and the barrier layer.
In one embodiment of the present invention, the substrate layer is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate or a GaN self-supporting substrate, and the stress buffer layer is any one of AlN, alGaN or GaN or a combination thereof.
In one embodiment of the invention, the p-GaN buried layer is a Mg-doped GaN material with a hole concentration of 10 14-1020cm-3.
In one embodiment of the present invention, the p-GaN cap layer is a Mg doped GaN material with a hole concentration of 10 14-1020cm-3.
In one embodiment of the present invention, the schottky electrode material Pt, ni or titanium nitride.
Another aspect of the present invention provides a method for preparing a lateral conduction GaN hybrid pn schottky power diode, for preparing a lateral conduction GaN hybrid pn schottky power diode according to any one of the foregoing embodiments, the method comprising:
s1, sequentially growing a stress buffer layer, a GaN epitaxial layer and a p-GaN buried layer on a substrate layer;
S2, carrying out selective region etching on the p-GaN buried layer to expose at least a part of the GaN epitaxial layer;
S3, sequentially growing a GaN channel layer, an AlGaN barrier layer and a p-GaN cap layer on the upper surfaces of the GaN epitaxial layer and the p-GaN buried layer;
S4, etching a selective area of the p-GaN cap layer to expose at least a part of AlGaN barrier layer;
S5, growing an ohmic contact electrode on the upper surface of the AlGaN barrier layer;
s6, etching downwards from the edge of the upper surface of the p-GaN cap layer to the upper surface of the p-GaN buried layer so as to expose at least a part of the p-GaN buried layer and form a groove anode region;
And S7, depositing metal on the upper surface of the p-GaN cap layer and in the anode region of the groove to form a Schottky electrode.
In one embodiment of the present invention, the S2 includes:
And etching the p-GaN buried layer by using a photoresist or a silicon oxide mask to expose at least a part of the GaN epitaxial layer.
Compared with the prior art, the invention has the beneficial effects that:
In the lateral conduction type GaN mixed pn Schottky power diode of the embodiment, a metal electrode is deposited on the upper surface of the p-GaN cap layer and in the anode region of the groove. Because the metal electrode and the two-dimensional electron gas channel on the side wall of the groove form Schottky contact with low barrier height, the Schottky contact is conducted at the time of low forward voltage, and therefore the conduction voltage of the whole diode is reduced. And ohmic contacts are formed by the metal electrode, the p-GaN buried layer and the p-GaN cap layer on the surface, and when the forward voltage is further increased, the p-GaN cap layer is conducted with the AlGaN/GaN and the pn junction between the p-GaN buried layer and the GaN channel layer. Compared with the traditional Schottky diode, the PN diode has better avalanche breakdown strength under surge current. Therefore, due to the introduction of the two layers of p-GaN, the device forms a composite structure of the Schottky diode and the pn junction diode, the anti-surge current capability is improved, and the on-resistance of the device is greatly reduced. In the reverse voltage state, the pn junction formed by the p-GaN cap layer and AlGaN/GaN is reversely biased to deplete the two-dimensional electron gas channel, and meanwhile, the electric field edge collecting phenomenon at the bottom part of the groove can be shielded, so that the reverse breakdown characteristic can be further enhanced. The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a lateral conduction GaN hybrid pn schottky power diode according to an embodiment of the present invention;
Fig. 2 is a flowchart of a method for preparing a lateral conduction GaN hybrid pn schottky power diode according to an embodiment of the present invention;
Fig. 3a to fig. 3g are schematic views illustrating a manufacturing process of a lateral conduction GaN hybrid pn schottky power diode according to an embodiment of the present invention.
Detailed Description
In order to further explain the technical means and effects adopted by the invention to achieve the preset aim, the following is a detailed description of a transverse conduction type GaN mixed pn schottky power diode and a preparation method thereof according to the invention with reference to the attached drawings and the specific embodiments.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in an article or apparatus that comprises the element.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a lateral conduction GaN hybrid pn schottky power diode according to an embodiment of the present invention. The power diode comprises a substrate layer 1, a stress buffer layer 2, a GaN epitaxial layer 3 and a p-GaN buried layer 4 which are sequentially arranged from bottom to top, wherein a GaN channel layer 5 is arranged on the upper surface of the GaN epitaxial layer 3 and is not covered by the p-GaN buried layer 4, the GaN channel layer 5 also covers a part of the upper surface of the p-GaN buried layer 4, a barrier layer 6 is arranged on the upper surface of the GaN channel layer 5, a p-GaN cap layer 7 and ohmic contact electrodes 8,p-GaN cap layer 7 are respectively arranged on two sides of the upper surface of the barrier layer 6 and are located above the p-GaN buried layer 4, and a Schottky electrode 9 is arranged on the upper surface of the p-GaN cap layer 7 and the part of the upper surface of the p-GaN buried layer 4, which is not covered by the GaN channel layer 5.
In this embodiment, the schottky electrode 9 has an L-shaped cross section, and includes a lateral portion 91 and a longitudinal portion 92, wherein the lateral portion 91 covers the upper surface of the p-GaN cap layer 7, the longitudinal portion 92 is located on the upper surface of the p-GaN buried layer 4, and the inner sidewall of the longitudinal portion 92 is sequentially contacted with the sidewall of the GaN channel layer 5, the sidewall of the barrier layer 6 and the sidewall of the p-GaN cap layer 7 from bottom to top, wherein the schottky electrode 9 forms ohmic contact with the p-GaN buried layer 4 and the p-GaN cap layer 7, and the schottky electrode 9 forms schottky contact with the GaN channel layer 5 and the barrier layer 6.
Further, the substrate layer 1 is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate or a GaN self-supporting substrate, the stress buffer layer 2 is any one of AlN, alGaN or GaN or a combination thereof, and the thickness of the stress buffer layer 2 is 10nm-100 μm.
Preferably, the GaN epitaxial layer 3 is an unintentionally doped GaN epitaxial layer with the thickness of 100nm-100 μm, the p-GaN buried layer 4 is a Mg doped GaN material with the thickness of 100nm-10 μm, the hole concentration is 10 14-1020cm-3, the GaN channel layer 5 is an unintentionally doped GaN epitaxial layer with the thickness of 100nm-100 μm, the barrier layer 6 is 6nm-30nm, the aluminum component concentration can be changed below 30%, the p-GaN cap layer 7 is a Mg doped GaN material with the thickness of 100nm-10 μm, and the hole concentration is 10 14-1020cm-3.
In the present embodiment, the material of the barrier layer 6 is one or a combination of any several of AlInN, inGaN, alInGaN, alN, the material of the ohmic contact electrode 8 is Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy, and the material of the schottky electrode 9 is Pt, ni or titanium nitride with good thermal stability.
The p-GaN buried layer in the conventional device is mainly used for improving reverse withstand voltage and damaging on-characteristics to some extent, and is not used for improving the capability of resisting surge current. In the lateral conduction type GaN mixed pn Schottky power diode of the embodiment, a metal electrode is deposited on the upper surface of the p-GaN cap layer and in the anode region of the groove. Because the metal electrode and the two-dimensional electron gas channel on the side wall of the groove form Schottky contact with low barrier height, the Schottky contact is conducted at the time of low forward voltage, and therefore the conduction voltage of the whole diode is reduced. And ohmic contacts are formed by the metal electrode, the p-GaN buried layer and the p-GaN cap layer on the surface, and when the forward voltage is further increased, the p-GaN cap layer is conducted with the AlGaN/GaN and the pn junction between the p-GaN buried layer and the GaN channel layer. Compared with the traditional Schottky diode, the PN diode has better avalanche breakdown strength under surge current. Therefore, due to the introduction of the two layers of p-GaN, the device forms a composite structure of the Schottky diode and the pn junction diode, the anti-surge current capability is improved, and the on-resistance of the device is greatly reduced. In the reverse voltage state, the pn junction formed by the p-GaN cap layer and AlGaN/GaN is reversely biased to deplete the two-dimensional electron gas channel, and meanwhile, the electric field edge collecting phenomenon at the bottom part of the groove can be shielded, so that the reverse breakdown characteristic can be further enhanced.
Example two
Based on the above embodiments, this embodiment provides a method for preparing a lateral conduction type GaN mixed pn schottky power diode, which is used for preparing the lateral conduction type GaN mixed pn schottky power diode in the first embodiment. Referring to fig. 2 and fig. 3a to fig. 3g, fig. 2 is a flowchart of a method for manufacturing a lateral conduction type GaN mixed pn schottky power diode according to an embodiment of the present invention, and fig. 3a to fig. 3g are schematic diagrams of a manufacturing process of a lateral conduction type GaN mixed pn schottky power diode according to an embodiment of the present invention.
The preparation method of the embodiment comprises the following steps:
s1, sequentially growing a stress buffer layer 2, a GaN epitaxial layer 3 and a p-GaN buried layer 4 on a substrate layer 1, as shown in FIG. 3 a.
In the present embodiment, the substrate layer 1 is any one of a Si substrate, a sapphire substrate, a silicon carbide substrate, or a GaN self-supporting substrate. In other embodiments, the substrate layer 1 may also be a multi-layer epitaxial substrate having different compositions.
The stress buffer layer 2 is any one or a combination of AlN, alGaN and GaN, and the thickness of the stress buffer layer 2 is 10nm-100 μm.
The GaN epitaxial layer 3 is an unintentionally doped GaN epitaxial layer with the thickness of 100nm-100 mu m, the p-GaN buried layer 4 is a Mg doped GaN material with the thickness of 100nm-10 mu m and the hole concentration of 10 14-1020cm-3.
In this embodiment, the stress buffer layer 2, the GaN epitaxial layer 3, and the p-GaN buried layer 4 may be grown by metal organic chemical vapor deposition or molecular beam epitaxy. In other embodiments, the p-GaN buried layer 4 may also be implemented using an ion implantation method.
In other embodiments, the GaN template material with the p-GaN buried layer may be directly obtained for subsequent fabrication.
And S2, carrying out selective region etching on the p-GaN buried layer 4 to expose at least a part of the GaN epitaxial layer 3, as shown in fig. 3 b.
Patterning is achieved by using a photoresist or silicon oxide mask 10 and selective area etching of the p-GaN buried layer 4. Specifically, in this embodiment, a photoresist is spun on the upper surface of the p-GaN buried layer 4 by using a spin coater, then the device sample wafer is put into a photolithography machine to expose the photoresist in the region to be etched, finally, the exposed device sample wafer is put into a developing solution to remove the photoresist in the region to be etched, the p-GaN buried layer 4 is etched to the surface of the GaN epitaxial layer 3 by adopting an ICP process, and finally, the etched sample wafer is sequentially put into an acetone solution, a stripping solution, an acetone solution and an ethanol solution to be cleaned, so that the residual photoresist is removed.
And S3, sequentially growing a GaN channel layer 5, an AlGaN barrier layer 6 and a p-GaN cap layer 7 on the upper surfaces of the GaN epitaxial layer 3 and the p-GaN buried layer 4, as shown in FIG. 3 c.
The GaN channel layer 5 is an unintentionally doped GaN epitaxial layer, the thickness of the GaN channel layer is 100nm-100 mu m, the thickness of the barrier layer 6 is 6-30nm, the concentration of an aluminum component can be changed below 30%, the p-GaN cap layer 7 is a Mg doped GaN material, the thickness of the p-GaN cap layer is 100nm-10 mu m, and the concentration of holes is 10 14-1020cm-3.
In the present embodiment, the GaN channel layer 5, alGaN barrier layer 6 and p-GaN cap layer 7 may all be grown by metal organic chemical vapor deposition or molecular beam epitaxy. In other embodiments, the p-GaN cap layer 7 may also be implemented using an ion implantation method.
S4, carrying out selective region etching on the p-GaN cap layer 7 to expose at least a part of the AlGaN barrier layer 6;
Patterning is achieved by using a photoresist 10 or a silicon oxide mask and selective area etching of the p-GaN cap layer 7. Specifically, in this embodiment, a photoresist is spun on the upper surface of the p-GaN cap layer 7 by using a spin coater, then the device sample wafer is put into a photolithography machine to expose the photoresist in the region to be etched, finally the exposed device sample wafer is put into a developing solution to remove the photoresist in the region to be etched, the p-GaN cap layer 7 is etched to the surface of the AlGaN barrier layer 6 by adopting an ICP process, and finally the etched sample wafer is sequentially put into an acetone solution, a stripping solution, an acetone solution and an ethanol solution to be cleaned, so that the residual photoresist is removed.
And S5, growing an ohmic contact electrode 8 on the upper surface of the AlGaN barrier layer 6, as shown in figure 3 e.
In this embodiment, the material of the ohmic contact electrode 8 is Ti/Al/Ni/Au alloy, ti/Al/Ti/Au alloy, ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy.
The ohmic contact electrode 8 may be prepared by magnetron sputtering, electron beam evaporation, thermal evaporation, or the like.
And S6, etching downwards from the edge of the upper surface of the p-GaN cap layer 7 to the upper surface of the p-GaN buried layer 4 so as to expose at least a part of the p-GaN buried layer 4, and forming a groove anode region as shown in fig. 3 f.
In this embodiment, the etching of the anode region of the groove may be performed using an inductively coupled plasma etching method, a reactive ion etching method, or ion milling.
And S7, depositing metal on the upper surface of the p-GaN cap layer 7 and in the anode region of the groove to form a Schottky electrode 9, as shown in figure 3 g.
Preferably, the schottky electrode 9 may be prepared by magnetron sputtering, electron beam evaporation, thermal evaporation, or the like. The material of the schottky electrode 9 is Pt, ni or titanium nitride having good thermal stability.
The schottky electrode 9 of the present embodiment has an L-shaped cross section, and includes a lateral portion 91 and a longitudinal portion 92, where the lateral portion 91 covers the upper surface of the p-GaN cap layer 7, the longitudinal portion 92 is located on the upper surface of the p-GaN buried layer 4, and the inner sidewall of the longitudinal portion 92 is sequentially contacted with the sidewall of the GaN channel layer 5, the sidewall of the barrier layer 6 and the sidewall of the p-GaN cap layer 7 from bottom to top, so that the schottky electrode 9 forms ohmic contact with the p-GaN buried layer 4 and the p-GaN cap layer 7, and the schottky electrode 9 forms schottky contact with the GaN channel layer 5 and the barrier layer 6.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (8)
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