CN112885806A - Substrate and preparation method thereof, chip packaging structure and packaging method thereof - Google Patents
Substrate and preparation method thereof, chip packaging structure and packaging method thereof Download PDFInfo
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- CN112885806A CN112885806A CN201911205380.1A CN201911205380A CN112885806A CN 112885806 A CN112885806 A CN 112885806A CN 201911205380 A CN201911205380 A CN 201911205380A CN 112885806 A CN112885806 A CN 112885806A
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- 239000000758 substrate Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000003466 welding Methods 0.000 claims abstract description 54
- 238000004891 communication Methods 0.000 claims description 36
- 230000004907 flux Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 48
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 239000000463 material Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000005476 soldering Methods 0.000 description 10
- 230000003139 buffering effect Effects 0.000 description 9
- 238000002161 passivation Methods 0.000 description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004848 polyfunctional curative Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000000976 ink Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
The invention relates to a substrate and a preparation method thereof, a chip packaging structure and a packaging method thereof, wherein the substrate comprises: a substrate body; the first bonding pad is formed on the surface of the substrate body; the second bonding pad is formed on the surface of the substrate body; the dielectric layer is formed on the surface of the substrate body and provided with a first window and a second window, the first window is exposed out of the first bonding pad, the second window is exposed out of the second bonding pad, a first vacant space is formed in the first window, a second vacant space is formed in the second window, and the volume of the first vacant space is larger than that of the second vacant space. The volume of the first vacant space of the substrate is larger than that of the second vacant space, a larger space is provided for the first solder compared with the second solder, the height difference between the first convex column and the second convex column is buffered, coplanarity is achieved, the first convex column and the first bonding pad can be well fixedly connected with each other, the second convex column and the second bonding pad can be well fixedly connected in the welding stage, and welding performance is improved.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a substrate and a preparation method thereof, a chip packaging structure and a packaging method thereof.
Background
Packaging is a process of assembling an integrated circuit into a chip final product, namely, placing an integrated circuit bare chip (Die) produced by Foundry on a substrate which plays a bearing role, leading out pins, and then fixing and packaging the integrated circuit bare chip into a whole. The flip chip packaging technology is one of bare chip packaging technologies, a metal convex column is manufactured on an electrode area of a chip, then the metal convex column is connected with the electrode area on a printed substrate in a pressure welding mode, the occupied area of the package is basically the same as the size of the chip, and the package is the smallest and thinnest one of all the packaging technologies. However, the heights of the metal posts relative to the chip are not uniform due to different positions of the metal posts, so that the lower posts cannot be connected with the substrate during pressure welding connection, and the yield of the chip is reduced.
Disclosure of Invention
In view of the above, the present invention provides a substrate and a method for manufacturing the same, a chip package structure and a method for packaging the same.
The present invention provides a substrate, comprising: a substrate body; the first bonding pad is formed on the surface of the substrate body; the second bonding pad is formed on the surface of the substrate body; the dielectric layer is formed on the surface of the substrate body and provided with a first window and a second window, the first window is exposed out of the first bonding pad, the second window is exposed out of the second bonding pad, a first vacant space is formed in the first window, a second vacant space is formed in the second window, and the volume of the first vacant space is larger than that of the second vacant space.
The volume of the first vacant space of the substrate is larger than that of the second vacant space, a larger space is provided for the first solder compared with the second solder, the height difference between the first convex column and the second convex column is buffered, coplanarity is achieved, the first convex column and the first bonding pad can be well fixedly connected with each other, the second convex column and the second bonding pad can be well fixedly connected in the welding stage, and welding performance is improved. In addition, the invention improves the substrate, and the chip does not need to be changed, so that the implementation is simple, the operation is easy, and the industrial popularization is easy.
In one embodiment, the surface area of the first pad is larger than the surface area of the second pad. The surface area of first pad is greater than the surface area of second pad, provides for first solder and compares in the bigger space of second solder to the difference in height between first projection and the second projection of buffering, in order to reach coplanarity, makes in the welding stage, first projection and first pad, second projection and second pad fixed connection that can both be fine improve welding performance.
In one embodiment, the first pad has an opening. The first pad is provided with an opening, so that part of first welding flux can enter the opening, a larger space compared with second welding flux is provided for the first welding flux, the height difference between the first convex column and the second convex column is buffered, coplanarity is achieved, the first convex column and the first pad, the second convex column and the second pad can be well fixedly connected in a welding stage, and welding performance is improved.
In one embodiment, the thickness of the first bonding pad is between 10um and 15 um. The thickness of first pad is between 10um ~ 15um, thickness makes the easy trompil of first pad for a short time, it is downthehole still to make the solder get into more easily, and can improve the stability of first pad, make first pad be difficult for the slope or drop, can also provide bigger space for first solder, with the difference in height between first projection of buffering and the second projection, in order to reach coplanarity, make in the welding stage, first projection and first pad, the second projection can both be fine fixed connection with the second pad, improve welding performance.
The present invention also provides a chip packaging structure, including: the above substrate; a chip; the communication medium layer is formed on the surface of the chip and is provided with an opening; the first convex column is formed on the surface of the communicated medium layer; the second convex column is formed in the opening and is electrically connected with the chip, and the height of the first convex column relative to the communication medium layer is higher than that of the second convex column relative to the communication medium layer; the first convex column is fixedly connected with the first bonding pad through first welding flux, and the second convex column is fixedly connected with the second bonding pad through second welding flux.
The volume of first vacant space is greater than the volume of second vacant space among the packaging structure of above-mentioned chip, provides for first solder and compares in the bigger space of second solder to the difference in height between first projection of buffering and the second projection, in order to reach coplanarity, make in the welding stage, first projection and first pad, second projection and second pad fixed connection that can both be fine improve welding performance. In addition, the invention improves the substrate, and the chip does not need to be changed, so that the implementation is simple, the operation is easy, and the industrial popularization is easy.
The invention provides a preparation method of a substrate, which comprises the following steps: providing a substrate body, and forming a first bonding pad and a second bonding pad on the surface of the substrate body; and forming a dielectric layer on the surface of the substrate body, wherein the dielectric layer is provided with a first window and a second window, the first window is exposed out of the first bonding pad, the second window is exposed out of the second bonding pad, a first vacant space is arranged in the first window, a second vacant space is arranged in the second window, and the volume of the first vacant space is larger than that of the second vacant space.
According to the preparation method of the substrate, the volume of the first vacant space of the substrate is larger than that of the second vacant space, a larger space is provided for the first solder compared with the second solder, the height difference between the first convex column and the second convex column is buffered, coplanarity is achieved, the first convex column and the first bonding pad can be fixedly connected well, and the second convex column and the second bonding pad can be fixedly connected well in the welding stage, so that the welding performance is improved. In addition, the invention improves the substrate, and the chip does not need to be changed, so that the implementation is simple, the operation is easy, and the industrial popularization is easy.
In one embodiment, the surface area of the first pad is larger than the surface area of the second pad. The surface area of first pad is greater than the surface area of second pad, provides for first solder and compares in the bigger space of second solder to the difference in height between first projection and the second projection of buffering, in order to reach coplanarity, makes in the welding stage, first projection and first pad, second projection and second pad fixed connection that can both be fine improve welding performance.
In one embodiment, the first pad has an opening. The first pad is provided with an opening, so that part of first welding flux can enter the opening, a larger space compared with second welding flux is provided for the first welding flux, the height difference between the first convex column and the second convex column is buffered, coplanarity is achieved, the first convex column and the first pad, the second convex column and the second pad can be well fixedly connected in a welding stage, and welding performance is improved.
In one embodiment, the thickness of the first bonding pad is between 10um and 15 um. The thickness of first pad is between 10um ~ 15um, thickness makes the easy trompil of first pad for a short time, it is downthehole still to make the solder get into more easily, and can improve the stability of first pad, make first pad be difficult for the slope or drop, can also provide bigger space for first solder, with the difference in height between first projection of buffering and the second projection, in order to reach coplanarity, make in the welding stage, first projection and first pad, the second projection can both be fine fixed connection with the second pad, improve welding performance.
The invention also provides a chip packaging method, which comprises the following steps: providing a chip, wherein a communication medium layer is formed on the surface of the chip, the communication medium layer is provided with an opening, a first convex column is formed on the surface of the communication medium layer, a second convex column is formed in the opening, the second convex column is electrically connected with the chip, and the height of the first convex column relative to the communication medium layer is higher than that of the second convex column relative to the communication medium layer; the preparation method of the substrate is used for preparing the substrate; and welding the first convex column on the first bonding pad through first welding flux, and welding the second convex column on the second bonding pad through second welding flux.
According to the chip packaging method, the volume of the first vacant space is larger than that of the second vacant space, a larger space is provided for the first solder compared with the second solder, the height difference between the first convex column and the second convex column is buffered, coplanarity is achieved, the first convex column and the first bonding pad can be well fixedly connected with each other, and the second convex column and the second bonding pad can be well fixedly connected with each other in the welding stage, so that the welding performance is improved. In addition, the invention improves the substrate, and the chip does not need to be changed, so that the implementation is simple, the operation is easy, and the industrial popularization is easy.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a substrate according to the present invention.
Fig. 2 to 5 are schematic structural views of steps of the method for manufacturing a substrate according to the present invention.
FIG. 5 is a cross-sectional view of a substrate according to the present invention.
FIG. 6 is a top view of a substrate according to the present invention.
Fig. 7 is a flowchart of a chip packaging method of the present invention.
Fig. 2 to 5 and fig. 8 to 9 are schematic structural views of steps of the chip packaging method according to the present invention.
Fig. 9 is a schematic structural diagram of a chip package structure according to the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
One embodiment, as shown in fig. 5 to 6, provides a substrate including: a substrate body 101; a first pad 1021 formed on the surface of the substrate body 101; a second pad 1022 formed on the surface of the substrate body 101; the dielectric layer 103 is formed on the surface of the substrate body 101, the dielectric layer 103 has a first window and a second window, the first window exposes the first pad 1021, the second window exposes the second pad 1022, a first vacant space 1031 is formed in the first window, a second vacant space 1032 is formed in the second window, and the volume of the first vacant space 1031 is greater than that of the second vacant space 1032.
In this embodiment, the volume of the first empty space 1031 of the substrate is greater than the volume of the second empty space 1032, so as to provide a larger space for the first solder 30 compared to the second solder 30, so as to buffer the height difference between the first protruding column 2031 and the second protruding column 2032, thereby achieving coplanarity, so that in the soldering stage, the first protruding column 2031 can be well fixedly connected with the first pad 1021, and the second protruding column 2032 can be well fixedly connected with the second pad 1022, thereby improving soldering performance. In addition, the substrate is improved, and the chip 201 does not need to be changed, so that the method is simple to implement, easy to operate and easy to industrially popularize.
In one embodiment, the material of the bonding pad comprises one or more of copper, aluminum, nickel, gold, silver and titanium. The material of the substrate body 101 includes one or a combination of several of resin, silicon, glass, silicon oxide, ceramic, and metal. The material of the dielectric layer 103 includes one or more of ink, a hardener, epoxy resin, silica gel, PI, PBO, PCB, silicon oxide, phosphosilicate glass, or fluorine-containing glass. The dielectric layer 103 prevents oxidation of the substrate by moisture, foreign substances, and electrolytes, prevents mechanical damage to the substrate, and prevents bridging short circuits during soldering.
In one embodiment, the surface area of the first pad 1021 is larger than the surface area of the second pad 1022. The surface area of the first pad 1021 is larger than that of the second pad 1022, so that a larger space is provided for the first solder 30 compared with the second solder 30, the height difference between the first convex column 2031 and the second convex column 2032 is buffered, coplanarity is achieved, the first convex column 2031 and the first pad 1021, and the second convex column 2032 and the second pad 1022 can be well fixedly connected in a welding stage, and welding performance is improved.
In one embodiment, the surface area of the first pad 1021 is 1.1 times to 1.5 times the surface area of the second pad 1022, for example, the surface area of the first pad 1021 is 1.3 times the surface area of the second pad 1022.
In one embodiment, the first pad 1021 has an opening 10211. The first pad 1021 has an opening 10211, so that a part of the first solder 30 can enter the opening 10211, a larger space is provided for the first solder 30 compared with the second solder 30, the height difference between the first convex column 2031 and the second convex column 2032 is buffered, coplanarity is achieved, and in a welding stage, the first convex column 2031 and the first pad 1021, and the second convex column 2032 and the second pad 1022 can be well fixedly connected, so that welding performance is improved.
In one embodiment, the shape of the aperture 10211 includes, but is not limited to, circular or rectangular.
In one embodiment, the diameter of the opening 10211 is at least 3um, for example, the diameter of the opening 10211 can be 4um, 5um, 6um, 7 um.
In one embodiment, the thickness of the first pad 1021 is between 10 um-15 um, for example, the thickness of the first pad 1021 may be 11um, 13um, 14 um. The thickness of first pad 1021 is between 10um ~ 15um, thickness is little makes easy trompil 10211 of first pad 1021, still make the solder get into in the trompil 10211 more easily, and can improve the stability of first pad 1021, make first pad 1021 be difficult for inclining or drop, can also provide bigger space for first solder 30, with the difference in height between first projection 2031 of buffering and the second projection 2032, in order to reach coplanarity, make in the welding stage, first projection 2031 and first pad 1021, second projection 2032 and the fixed connection that second pad 1022 can both be fine, improve welding performance.
In one embodiment, as shown in fig. 9, a chip package structure is provided, including: the above substrate; a chip 201; a communication dielectric layer 202 formed on the surface of the chip 201, wherein the communication dielectric layer 202 has an opening; a first convex column 2031 formed on the surface of the communication medium layer 202; a second protrusion 2032 formed in the opening and electrically connected to the chip 201, wherein a height of the first protrusion 2031 relative to the communication medium layer 202 is higher than a height of the second protrusion 2032 relative to the communication medium layer 202; the first protrusion 2031 and the first pad 1021 are fixedly connected by a first solder 30, and the second protrusion 2032 and the second pad 1022 are fixedly connected by a second solder 30.
In this embodiment, the volume of the first empty space 1031 in the package structure of the chip 201 is greater than the volume of the second empty space 1032, so as to provide a larger space for the first solder 30 compared to the second solder 30, so as to buffer the height difference between the first protrusion column 2031 and the second protrusion column 2032, thereby achieving coplanarity, so that in the soldering stage, the first protrusion column 2031 and the first pad 1021, and the second protrusion column 2032 and the second pad 1022 can be both fixedly connected well, thereby improving the soldering performance. In addition, the substrate is improved, and the chip 201 does not need to be changed, so that the method is simple to implement, easy to operate and easy to industrially popularize. The first protrusion 2031 functions to support and reduce stress.
In one embodiment, as shown in fig. 8, the communication dielectric layer 202 includes a third pad 2023, a passivation layer 2022 and a redistribution layer 2024, the passivation layer 2022 is formed on the surface of the chip 201, the passivation layer 2022 has a third window, the third pad 2023 is formed on the surface of the chip 201, the third window exposes the third pad 2023, the redistribution layer 2024 is formed on the surface of the passivation layer 2022, the surface of the redistribution layer 2024 has an opening 2021 for forming the second post 2032, the redistribution layer 2024 includes a patterned first dielectric layer 20241, a patterned metal layer 20242 and a patterned second dielectric layer 20243, and the chip 201 and the second post 2032 are electrically connected through the third pad 2023 and the metal layer 20242 in the redistribution layer 2024.
In one embodiment, the material of the communication dielectric layer 202 includes polyimide or a polymer material. The communication dielectric layer 202 can play a role in buffering and insulation, and can also prevent the chip from being damaged. The first convex column 2031 and the second convex column 2032 are made of one or a combination of copper, aluminum, nickel, gold, silver and titanium. The solder 30 is made of one or more of tin, copper, aluminum, nickel, gold, silver, and titanium.
One embodiment, as shown in fig. 1, provides a method for preparing a substrate, including: providing a substrate body 101, and forming a first pad 1021 and a second pad 1022 on the surface of the substrate body 101; forming a dielectric layer 103 on the surface of the substrate body 101, wherein the dielectric layer 103 has a first window and a second window, the first window exposes the first pad 1021, the second window exposes the second pad 1022, a first empty space 1031 is provided in the first window, a second empty space 1032 is provided in the second window, and the volume of the first empty space 1031 is greater than that of the second empty space 1032.
In this embodiment, the above-mentioned method for manufacturing a substrate makes the volume of the first empty space 1031 of the substrate larger than the volume of the second empty space 1032, so as to provide a larger space for the first solder 30 compared to the second solder 30, so as to buffer the height difference between the first convex column 2031 and the second convex column 2032, thereby achieving coplanarity, so that in the soldering stage, the first convex column 2031 and the first pad 1021, and the second convex column 2032 and the second pad 1022 can be well fixedly connected, thereby improving soldering performance. In addition, the substrate is improved, and the chip 201 does not need to be changed, so that the method is simple to implement, easy to operate and easy to industrially popularize.
S11: a substrate body 101 is provided, and a first pad 1021 and a second pad 1022 are formed on a surface of the substrate body 101.
In one embodiment, step S11 includes:
s111: as shown in fig. 2, a substrate body 101 is provided, and as shown in fig. 3, a pad material layer 102 is formed on a surface of the substrate body 101;
s112: as shown in fig. 4, the pad material layer 102 is etched using a photolithography process to form a first pad 1021 and a second pad 1022.
In one embodiment, the pad material layer 102 includes a copper foil, and further includes, before step S111: and roughening the copper foil. The roughening treatment is to slightly corrode the copper foil by using chemical liquid. The roughening treatment can increase the surface area of the copper foil, improve the binding force between the copper foil and the substrate body 101, and prevent delamination.
In one embodiment, step S112 is followed by: a nickel, gold or Organic Solderability Preservative (OSP) film is formed on the surfaces of the first pad 1021 and the second pad 1022 by electroplating or electroless plating.
In one embodiment, step S112 further comprises: the pad material layer is etched using a photolithography process to form an opening 10211 on the first pad 1021. The first pad 1021 has an opening 10211, so that a part of the first solder 30 can enter the opening 10211, a larger space is provided for the first solder 30 compared with the second solder 30, the height difference between the first convex column 2031 and the second convex column 2032 is buffered, coplanarity is achieved, and in a welding stage, the first convex column 2031 and the first pad 1021, and the second convex column 2032 and the second pad 1022 can be well fixedly connected, so that welding performance is improved.
In one embodiment, the material of the bonding pad comprises one or more of copper, aluminum, nickel, gold, silver and titanium. The method for forming the bonding pad comprises physical vapor deposition or chemical vapor deposition. The material of the substrate body 101 includes one or a combination of several of resin, silicon, glass, silicon oxide, ceramic, and metal.
In one embodiment, the shape of the aperture 10211 includes, but is not limited to, circular or rectangular.
In one embodiment, the diameter of the opening 10211 is at least 3um, for example, the diameter of the opening 10211 can be 4um, 5um, 6um, 7 um.
In one embodiment, the surface area of the first pad 1021 is larger than the surface area of the second pad 1022. The surface area of the first pad 1021 is larger than that of the second pad 1022, so that a larger space is provided for the first solder 30 compared with the second solder 30, the height difference between the first convex column 2031 and the second convex column 2032 is buffered, coplanarity is achieved, the first convex column 2031 and the first pad 1021, and the second convex column 2032 and the second pad 1022 can be well fixedly connected in a welding stage, and welding performance is improved.
In one embodiment, the surface area of the first pad 1021 is 1.1 times to 1.5 times the surface area of the second pad 1022, for example, the surface area of the first pad 1021 is 1.3 times the surface area of the second pad 1022.
In one embodiment, the thickness of the first pad 1021 is between 10 um-15 um, for example, the thickness of the first pad 1021 may be 11um, 13um, 14 um. The thickness of first pad 1021 is between 10um ~ 15um, thickness is little makes easy trompil 10211 of first pad 1021, still make the solder get into in the trompil 10211 more easily, and can improve the stability of first pad 1021, make first pad 1021 be difficult for inclining or drop, can also provide bigger space for first solder 30, with the difference in height between first projection 2031 of buffering and the second projection 2032, in order to reach coplanarity, make in the welding stage, first projection 2031 and first pad 1021, second projection 2032 and the fixed connection that second pad 1022 can both be fine, improve welding performance.
S12: as shown in fig. 5, a dielectric layer 103 is formed on a surface of the substrate body 101, the dielectric layer 103 has a first window and a second window, the first pad 1021 is located in the first window, the second pad 1022 is located in the second window, a first empty space 1031 is provided in the first window, a second empty space 1032 is provided in the second window, and a volume of the first empty space 1031 is greater than a volume of the second empty space 1032.
In one embodiment, step S12 includes:
s121: forming a dielectric layer 103 on the surface of the substrate body 101 and the surfaces of the first pad 1021 and the second pad 1022;
s122: the first and second windows are formed in a photolithography process to expose the first and second pads 1021 and 1022.
In one embodiment, the material of the dielectric layer 103 includes one or more of ink, hardener, epoxy resin, silica gel, PI, PBO, PCB, silicon oxide, phosphosilicate glass, or fluorine-containing glass. Methods of forming the dielectric layer 103 include spin-on coating or CVD. The dielectric layer 103 prevents oxidation of the substrate by moisture, foreign substances, and electrolytes, prevents mechanical damage to the substrate, and prevents bridging short circuits during soldering.
One embodiment, as shown in fig. 7, provides a chip packaging method, including: providing a chip 201, wherein a communication medium layer 202 is formed on the surface of the chip 201, the communication medium layer 202 has an opening, a first convex column 2031 is formed on the surface of the communication medium layer 202, a second convex column 2032 is formed in the opening, the second convex column 2032 is electrically connected with the chip 201, and the height of the first convex column 2031 relative to the communication medium layer 202 is higher than the height of the second convex column 2032 relative to the communication medium layer 202; the preparation method of the substrate is used for preparing the substrate; the first stud 2031 is soldered to the first pad 1021 by a first solder 30, and the second stud 2032 is soldered to the second pad 1022 by a second solder 30.
In this embodiment, the above chip 201 packaging method makes the volume of the first empty space 1031 larger than the volume of the second empty space 1032, so as to provide a larger space for the first solder 30 compared to the second solder 30, so as to buffer the height difference between the first protrusion column 2031 and the second protrusion column 2032, so as to achieve coplanarity, so that in the soldering stage, the first protrusion column 2031 and the first pad 1021, and the second protrusion column 2032 and the second pad 1022 can be well fixedly connected, thereby improving the soldering performance. In addition, the substrate is improved, and the chip 201 does not need to be changed, so that the method is simple to implement, easy to operate and easy to industrially popularize. The first protrusion 2031 functions to support and reduce stress.
S21: as shown in fig. 8, a chip 201 is provided, a communication medium layer 202 is formed on a surface of the chip 201, the communication medium layer 202 has an opening, a first protrusion 2031 is formed on a surface of the communication medium layer 202, a second protrusion 2032 is formed in the opening, the second protrusion 2032 is electrically connected to the chip 201, and a height of the first protrusion 2031 relative to the communication medium layer 202 is higher than that of the second protrusion 2032.
In one embodiment, as shown in fig. 8, the communication dielectric layer 202 includes a third pad 2023, a passivation layer 2022 and a redistribution layer 2024, the passivation layer 2022 is formed on the surface of the chip 201, the passivation layer 2022 has a third window, the third pad 2023 is formed on the surface of the chip 201, the third window exposes the third pad 2023, the redistribution layer 2024 is formed on the surface of the passivation layer 2022, the surface of the redistribution layer 2024 has an opening 2021 for forming the second post 2032, the redistribution layer 2024 includes a patterned first dielectric layer 20241, a patterned metal layer 20242 and a patterned second dielectric layer 20243, and the chip 201 and the second post 2032 are electrically connected through the third pad 2023 and the metal layer 20242 in the redistribution layer 2024.
In one embodiment, the material of the communication dielectric layer 202 includes polyimide or a polymer material. The communication dielectric layer 202 can play a role in buffering and insulation, and can also prevent the chip from being damaged. The first convex column 2031 and the second convex column 2032 are made of one or a combination of copper, aluminum, nickel, gold, silver and titanium.
S22: as shown in fig. 2 to 5, the substrate was prepared by the above-described method for preparing a substrate.
S23: as shown in fig. 9, the first stud 2031 is soldered to the first pad 1021 by a first solder 30, and the second stud 2032 is soldered to the second pad 1022 by a second solder 30.
In one embodiment, the material of the solder 30 includes one or a combination of tin, copper, aluminum, nickel, gold, silver and titanium.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A substrate, comprising:
a substrate body;
the first bonding pad is formed on the surface of the substrate body;
the second bonding pad is formed on the surface of the substrate body;
the dielectric layer is formed on the surface of the substrate body and provided with a first window and a second window, the first window is exposed out of the first bonding pad, the second window is exposed out of the second bonding pad, a first vacant space is formed in the first window, a second vacant space is formed in the second window, and the volume of the first vacant space is larger than that of the second vacant space.
2. The substrate of claim 1, wherein a surface area of the first pad is greater than a surface area of the second pad.
3. The substrate of claim 1, wherein the first pad has an opening.
4. The substrate of claim 1, wherein the first pad has a thickness between 10um and 15 um.
5. A chip package structure, comprising:
the substrate according to any one of claims 1 to 4;
a chip;
the communication medium layer is formed on the surface of the chip and is provided with an opening;
the first convex column is formed on the surface of the communicated medium layer;
the second convex column is formed in the opening and is electrically connected with the chip, and the height of the first convex column relative to the communication medium layer is higher than that of the second convex column relative to the communication medium layer;
the first convex column is fixedly connected with the first bonding pad through first welding flux, and the second convex column is fixedly connected with the second bonding pad through second welding flux.
6. A method of preparing a substrate, comprising:
providing a substrate body, and forming a first bonding pad and a second bonding pad on the surface of the substrate body;
and forming a dielectric layer on the surface of the substrate body, wherein the dielectric layer is provided with a first window and a second window, the first window is exposed out of the first bonding pad, the second window is exposed out of the second bonding pad, a first vacant space is arranged in the first window, a second vacant space is arranged in the second window, and the volume of the first vacant space is larger than that of the second vacant space.
7. The method according to claim 6, wherein a surface area of the first pad is larger than a surface area of the second pad.
8. The method for manufacturing a substrate according to claim 6, wherein the first pad has an opening.
9. The method for manufacturing a substrate according to claim 6, wherein the thickness of the first pad is between 10um and 15 um.
10. A method of chip packaging, comprising:
providing a chip, wherein a communication medium layer is formed on the surface of the chip, the communication medium layer is provided with an opening, a first convex column is formed on the surface of the communication medium layer, a second convex column is formed in the opening, the second convex column is electrically connected with the chip, and the height of the first convex column relative to the communication medium layer is higher than that of the second convex column relative to the communication medium layer;
preparing a substrate according to the method of any one of claims 6 to 9;
and welding the first convex column on the first bonding pad through first welding flux, and welding the second convex column on the second bonding pad through second welding flux.
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