CN113220107A - Power consumption management method for PCIe link, terminal device and storage medium - Google Patents
Power consumption management method for PCIe link, terminal device and storage medium Download PDFInfo
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3253—Power saving in bus
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- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The present disclosure provides a power consumption management method of a PCIe link, a terminal device, and a storage medium, where the PCIe link is used to connect a first terminal device and a second terminal device, the power consumption management method is applied to a PCIe controller of the first terminal device, and the power consumption management method includes: detecting whether the PCIe link is in an L0 state; monitoring whether the PCIe link is idle or not under the condition that the PCIe link is in an L0 state; and when monitoring that the PCIe link is idle, shutting down clocks of all target modules set for completing data transmission in the application layer of the first terminal equipment. The power consumption of the PCIe link is reduced, so that the low power consumption requirement of the terminal equipment is met.
Description
Technical Field
The present disclosure relates to the PCIe technology field, and in particular, to a power consumption management method for a PCIe link, a terminal device, and a storage medium.
Background
PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) is one of high-speed serial buses, and is widely applied to the fields of data acquisition and storage, and the like.
The power states of the terminal devices connected to the PCIe bus include device power states (D-states for short) and link power states (L-states for short). Different link Power states are switched with each other under the control of an Active State Power Management (ASPM) mechanism, and the ASPM mechanism can be started only when the device Power State is a D0 State. After the ASPM mechanism is started, the link power states of the terminal device have multiple optional states, such as L0, L0s, L1 (including L1.1 and L1.2), and L2, where L0s, L1, and L2 are low power consumption link power states, and L0 is a power state in which the PCIe link can normally operate. When the PCIe link enters the L0 state, the PCIe link may normally operate, so that the terminal device sends or receives packets such as TLP and DLLP.
With the increase of data transmission amount and the increase of transmission speed, terminal devices (such as Solid State disks (Solid State disks) used in the field of data storage) face higher and higher requirements on low power consumption design. The existing low-power consumption link management scheme is difficult to meet the low-power consumption requirement on the terminal equipment in some special scenes.
Disclosure of Invention
In order to solve the technical problem, the present disclosure provides a power consumption management method for a PCIe link, a terminal device, and a storage medium, which aim to implement dynamic management of low power consumption in an L0 state, so that a low power consumption requirement for the terminal device in a special scenario is met.
A first aspect of the present disclosure provides a power consumption management method for a PCIe link, where the PCIe link is used to connect a first terminal device and a second terminal device, and the power consumption management method is applied to a PCIe controller of the first terminal device, and the power consumption management method includes:
detecting whether the PCIe link is in an L0 state, wherein the L0 state is a power state of the PCIe link working normally;
monitoring whether the PCIe link is idle or not under the condition that the PCIe link is in an L0 state;
and when monitoring that the PCIe link is idle, shutting down clocks of all target modules set for completing data transmission in the application layer of the first terminal equipment.
Optionally, the monitoring whether the PCIe link is idle includes:
judging whether a request needs to be sent inside the PCIe link or not to obtain a first judgment result;
under the condition that the first judgment result is that the PCIe link does not request to be sent, judging whether a data receiving end of the first terminal equipment has data to be received through the PCIe link or not to obtain a second judgment result;
and determining whether the PCIe link is idle according to the second judgment result.
Optionally, the monitoring whether the PCIe link is idle further includes:
under the condition that the first judgment result is that the PCIe link does not request to be sent, judging whether the credit between the first terminal equipment and the second terminal equipment is normal or not to obtain a third judgment result;
and determining whether the PCIe link is idle according to the third judgment result and the second judgment result.
Optionally, determining whether the PCIe link is idle according to the third determination result and the second determination result includes:
monitoring a logic idle symbol within a preset time length from a target moment;
determining that the PCIe link is idle when a logic idle symbol is monitored in the preset time length;
and determining that the data receiving end has no data to receive through the PCIe link and the credit amount is normal according to the second judgment result and the third judgment result.
Optionally, the turning off the clock of each target module, which is set in the application layer of the first terminal device to complete data transmission, includes:
disconnecting a connection line between a PIPE-compliant PHY module and a CLK/RST model so as to interrupt the transmission of a pclk clock generated by the PIPE-compliant PHY module to the CLK/RST model;
the PIPE-compliant PHY module is located in a physical layer of the first terminal device, and the CLK/RST model is used for generating clocks of the target modules according to the received pclk clock.
Optionally, the turning off the clock of each target module, which is set in the application layer of the first terminal device to complete data transmission, further includes:
conducting clock connection between the PIPE-compliant PHY module and the CXPL module and the power control module respectively, so that a pclk clock generated by the PIPE-compliant PHY module is issued to the CXPL module and the power control module;
the CXPL module is a module in the first terminal device for implementing a common PCIe port physical sublayer, a data link layer, and a transport layer logic, and the power control module is configured to manage a power supply of the first terminal device.
Optionally, each of the target modules comprises: a RADM module, an XADM module, and an MSGEN module.
Optionally, after the clock of each target module set in the application layer of the first terminal device for completing data transmission is turned off, the method further includes:
and recovering the clock of each target module under the condition that a data receiving end of the first terminal device detects a non-logic idle symbol or the first terminal device sends a request on the PCIe link.
A second aspect of the present disclosure provides a terminal device, where the terminal device communicates through a PCIe link, and the terminal device includes a PCIe controller, and the PCIe controller is configured to execute any one of the power consumption management methods of the first aspect.
A third aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements any of the power consumption management methods of the first aspect.
The beneficial effects of this disclosure are:
the power consumption management method provided by the disclosure comprises the steps of firstly detecting whether a PCIe link is in an L0 state; monitoring whether the PCIe link is idle or not under the condition that the PCIe link is in an L0 state; and when monitoring that PCIe is idle, shutting off clocks of all target modules set for completing data transmission in the application layer of the first terminal device, thereby reducing the power consumption of the target modules and realizing the dynamic management of low power consumption in the L0 state; and, because of the further improvement in the L0 state, the method is a low power consumption management method based on compliance with the PCIe protocol, thus ensuring compatibility with the existing PCIe protocol.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 illustrates an application context diagram of a power consumption management method for PCIe links provided by the present disclosure;
FIG. 2 illustrates a flow chart of a method of power consumption management for a PCIe link provided by the present disclosure;
FIG. 3 illustrates a flow diagram of a method of monitoring whether a PCIe link is idle in an embodiment of the disclosure;
fig. 4 shows an architecture used by end devices communicating over a PCIe link.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
Fig. 1 is an application scenario diagram of a power consumption management method for PCIe links provided in the present disclosure. Referring to fig. 1, a first terminal device 100 and at least one second terminal device 200 are connected through a PCIe link, a PCIe controller 110 is disposed on the first terminal device 100, the PCIe controller 110 is an execution main body of the power consumption management method for the PCIe link provided in the present disclosure, and the PCIe controller 110 implements dynamic low-power consumption management of the PCIe link in an L0 state by monitoring the PCIe link, so that the power consumption of the first terminal device 100 is effectively reduced. Illustratively, the first terminal device 100 is a solid state disk, and the second terminal device 200 is a computer.
Fig. 2 is a flowchart illustrating a power consumption management method for PCIe links provided in the present disclosure. Referring to fig. 2, a power consumption management method for a PCIe link includes:
step S110, detecting whether the PCIe link is in an L0 state (the L0 state is a power state when the PCIe link works normally);
step S120, under the condition that the PCIe link is in the L0 state, monitoring whether the PCIe link is idle;
in step S130, when it is detected that the PCIe link is idle, the clocks of the target modules set in the application layer of the first terminal device 100 for completing the data transmission are turned off (hereinafter, referred to as L0 clock gating becomes effective or L0 clock gating is entered).
The above steps S110 to S130 are described in detail below.
Step S110, detecting whether the PCIe link is in an L0 state, that is, determining a link power state of the PCIe link, wherein if it is determined that the PCIe link is in any one of non-L0 states of L0S, L1, and L2, continuing to step S110 to determine whether a subsequent PCIe link is in an L0 state; if the PCIe link is determined to be in the L0 state, step S120 is executed.
Step S120, monitoring whether the PCIe link is idle, namely monitoring whether the PCIe link in the L0 state is idle, wherein if the PCIe link is not idle, the step S120 is continued to monitor whether the subsequent PCIe link in the L0 state is idle; if the PCIe link is monitored to be idle, step S130 is executed. The PCIe link is idle, which means that no data needs to be transmitted in the PCIe link.
Through the steps S110 to S130, when it is monitored that the PCIe link in the L0 state is idle, the system enters the L0 clock gating state, that is, the clocks of the target modules configured to complete data transmission are turned off, so that the power consumption of the target modules is reduced, and dynamic management of low power consumption in the L0 state is implemented.
Referring to fig. 3, in an optional embodiment, in view that the data receiving end of the first terminal device 100 receives data in a subsequent process after the request is initiated, in order to save the determination process, the step S120 of monitoring whether the PCIe link is idle includes:
step S121, judging whether a request needs to be sent in the PCIe link to obtain a first judgment result;
step S122, when the first determination result is that the PCIe link does not request to be sent, determining whether a data receiving end of the first terminal device 100 has data to receive through the PCIe link, to obtain a second determination result;
step S123, determining whether the PCIe link is idle according to the second determination result.
Exemplarily, the first terminal device 100 is a solid state disk, and the second terminal device 200 is a computer, and the types of the requests include requests for MWR, MRD, CPL, DLLP, and accessing the solid state disk.
It should be noted that: (1) the step S121 is executed to determine that no request needs to be sent inside the PCIe link, so that the first determination result indicates that there is a request for sending/not for the PCIe link, and when the first determination result indicates that there is a request for sending inside the PCIe link, it indicates that the PCIe link is not idle, the PCIe link is maintained in the L0 state, and the step S121 continues to be executed; in the case where the first determination result indicates that no request needs to be sent inside the PCIe link, step S122 is performed. (2) Step S122 is executed to determine that the data receiving end of the first terminal device 100 does not have data to be received through the PCIe link, so that the second determination result indicates that the data receiving end of the first terminal device 100 has/does not have data to be received through the PCIe link, and in the case that the second determination result indicates that the data receiving end of the first terminal device 100 has data to be received through the PCIe link, it indicates that the PCIe link is not idle, the PCIe link is maintained in the L0 state, and step S122 is continuously executed; in case the second determination result indicates that the data receiving end of the first terminal device 100 has no data to receive over the PCIe link, step S123 is executed.
In an optional embodiment, the monitoring whether the PCIe link is idle in step S120 further includes: when the first determination result is that the PCIe link does not request to be sent, determining whether a credit (credit) between the first terminal device 100 and the second terminal device 200 is normal, to obtain a third determination result; and determining whether the PCIe link is idle according to the third judgment result and the second judgment result.
Specifically, if the third determination result is that the credit between the first terminal device 100 and the second terminal device 200 is not normal, it indicates that the PCIe link is in a busy state; if the third determination result is that the credit between the first terminal device 100 and the second terminal device 200 is normal, but the second determination result is that there is data to be received at the data receiving end of the first terminal device 100, it indicates that the PCIe link is in a busy state. The PCIe link is in the idle state only when the amount of credit between the first terminal device 100 and the second terminal device 200 is normal and the data receiving end of the first terminal device 100 has no data to receive.
The following illustrates "credit normal": assuming that the initial capacity value of the buffer for receiving data in the communication terminal A is 4, and the credit of the communication terminal A in the communication terminal B is 4; after B sends 1 data packet to A, the buffer in A is occupied by 1, the credit of A in B is 3 at this time, A sends information through DLLP, and the credit of A in B is updated, and the credit is normal at this time. "normal credit" may also mean: the credits for A at B and B at A are both initial values.
In the embodiment of the present disclosure, the amount of credit between the first terminal device 100 and the second terminal device 200 is normal, and it is proved that TLPs (transaction layer packets) of both sides have been received already, so that the third determination result is combined with the second determination result to determine whether the PCIe link is idle, thereby improving the determination accuracy of whether the PCIe link is idle.
In an optional embodiment, the determining whether the PCIe link is idle according to the third determination result and the second determination result includes: monitoring a logic Idle Symbol (logic Idle Symbol) within a preset time length from a target time; determining that the PCIe link is idle when a logic idle symbol is monitored in a preset time length (which can be customized by a user in specific practice); the target time is a time when it is determined that the data receiving end of the first terminal device 100 has no data to receive through the PCIe link and the credit amount is normal according to the second determination result and the third determination result.
Specifically, the logic idle symbol is a symbol indicating that the PCIe link is idle, and the PCIe link is determined to be idle when the logic idle symbol is monitored within the preset time period; if the logic idle symbol is not monitored in the preset duration, the PCIe link is scheduled to be busy, and whether the PCIe link in the L0 state is busy is verified by executing the steps S121 to S122 and the step of judging whether the credit amount is normal.
In the embodiment of the disclosure, the logic idle symbol is adopted to further assist in judging whether the PCIe link is idle, and the PCIe link is determined to be idle only when the logic idle symbol is monitored within the preset time duration, so that the judgment precision of whether the PCIe link is idle is further ensured, wherein the preset time duration is set, on one hand, the time duration for waiting for the logic idle symbol is limited by the preset time duration and cannot be too long, so that the real-time performance and the validity of the judgment are ensured, on the other hand, the PCIe link immediately enters the L0 clock gating after being determined to be idle by the third judgment result and the second judgment result, so that the too frequent switching between the L0 clock gating and the L0 state is avoided.
Step S130, when it is monitored that the PCIe is idle, the clocks of the target modules set in the application layer of the first terminal device for completing data transmission are turned off, and then the clocks of the target modules are also recovered when the PCIe link recovers from the idle state to the busy state.
PCIe can be divided into a physical layer, a data link layer, a transport layer and an application layer according to a standard protocol. Fig. 4 shows a structure used for each of the first terminal device 100 and the second terminal device 200 in communication via a PCIe link. Referring to fig. 4, a cxpl (common Express Port logic) module X20 in the architecture includes a physical sublayer (for implementing a part of the functions of the physical layer), a data link layer, and a transport layer, and is a module for implementing a common PCIe Port physical sublayer, a data link layer, and a transport layer logic, and specifically implements most of the transport layer logic, all of the data link layer logic, and a MAC portion of the physical layer; the physical layer in the architecture further comprises a PIPE-compliant PHY module and a CLK/RST model, wherein the PIPE-compliant PHY module is used for generating a pclk clock, and the CLK/RST model is connected with the PIPE-compliant PHY module and then can receive the pclk clock generated by the PIPE-compliant PHY module and generate a plurality of normal working clocks according to the received pclk clock, so that each module (comprising a part of an application layer, a CXPL module X20 and a power supply control module (not shown in the figure)) is kept working in an L0 state through the plurality of normal working clocks; some Application layers in the architecture are provided with a RADM (Receive Application-Dependent Module) Module, an XADM (Transmit Application-Dependent Module) Module, an MSGEN (message generation) Module, a CDM Module, and the like, where the RADM Module is a data receiving Module, the XADM Module is a data transmitting Module, and the MSGEN Module is a data generating Module, which are all modules (target modules) required for completing data transmission of the Application Layer, such as for adding a transmission queue and transmitting an arbitration TLP (Transaction Layer Packet).
In an alternative embodiment, the turning off the clock of each target module in the application layer of the first terminal device 100 to complete the data transmission in step S130 includes: the connection line between the PIPE-compatible PHY module and the CLK/RST model in the first terminal device 100 is disconnected to interrupt the pclk clock generated by the PIPE-compatible PHY module from being transmitted to the CLK/RST model, so that the CLK/RST model does not regenerate the clocks of the respective target modules, i.e., the clocks of the respective target modules are disconnected, and the L0 clock gating is enabled. It is emphasized that the XADM module clock is off, but there is still a small amount of logic in operation to sense whether there is an external request.
Further, the turning off the clocks of the target modules set in the application layer of the first terminal device 100 to complete the data transmission in step S130 further includes: the clock connections of the PIPE-compliant PHY module in the first terminal device 100 and the CXPL module X20 and the power control module are conducted, respectively, so that the pclk clock generated by the PIPE-compliant PHY module is directly issued to the CXPL module X20 and the power control module, and thus the CXPL module X20 can continue to operate as a core operating module of the PCIe link without being affected, and the power control module can continue to operate as a module for managing the power of the first terminal device 100 without being affected.
In an alternative embodiment, after the step S130 is executed, the power consumption management method further includes: and in the case that the data receiving end of the first terminal device 100 detects a non-logical idle symbol or the first terminal device 200 sends a request on the PCIe link, recovering the clock of each target module, i.e., exiting the L0 clock gating, and entering the L0 state.
It is emphasized that in the L0 clock-gated state, the CXPL module X20 and the power control module remain operating normally, so that when the data receiving end of the first end device 100 detects a non-logical idle symbol or the first end device 100 sends a request on the PCIe link, the PCIe link may be rapidly tripped out of the L0 clock-gated into the L0 state.
It should be noted that the time of going out of the L0 clock gating and entering the L0 state is shorter than the time of switching the existing L0s state to the L0 state (the time of entering the L0 state from the L0s state is shorter than the time of entering the L0 state from the L1 state), so that the L0 clock gating hardly affects the normal operation of the PCIe link based on the L0 state, and the PCIe link in the L0 state can enter the low power consumption state once idle. Of course, with L0 clock gating, the PCIe link can still switch to the low power link power states L0s, L1, and L2 at the right time according to the prior art, and thus the disclosed embodiments enable a further reduction in power consumption of the PCIe link over the prior art through low power dynamic management of the L0 state.
Corresponding to the power consumption management method of the PCIe link, the embodiment of the present disclosure further provides a terminal device, where the terminal device communicates through the PCIe link, and the terminal device includes a PCIe controller, and the PCIe controller is configured to execute any one of the power consumption management methods, so that the terminal device can effectively reduce power consumption.
In response to the power consumption management method for the PCIe link, the embodiments of the present disclosure further provide a computer-readable storage medium, on which a computer program (or referred to as computer-executable instructions) is stored, and when the program is executed by a processor, the computer program is used to perform any one of the power consumption management methods described above.
The computer storage media of the disclosed embodiments may take any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for embodiments of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
Further, in this document, the contained terms "include", "contain" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, a method, an article or an apparatus including a series of elements includes not only those elements but also other elements not explicitly listed or inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (10)
1. A power consumption management method of a PCIe link is characterized in that the PCIe link is used for connecting a first terminal device and a second terminal device, the power consumption management method is applied to a PCIe controller of the first terminal device, and the power consumption management method comprises the following steps:
detecting whether the PCIe link is in an L0 state, wherein the L0 state is a power state of the PCIe link working normally;
monitoring whether the PCIe link is idle or not under the condition that the PCIe link is in an L0 state;
and when monitoring that the PCIe link is idle, shutting down clocks of all target modules set for completing data transmission in the application layer of the first terminal equipment.
2. The power consumption management method of claim 1, wherein the monitoring whether the PCIe link is idle comprises:
judging whether a request needs to be sent inside the PCIe link or not to obtain a first judgment result;
under the condition that the first judgment result is that the PCIe link does not request to be sent, judging whether a data receiving end of the first terminal equipment has data to be received through the PCIe link or not to obtain a second judgment result;
and determining whether the PCIe link is idle according to the second judgment result.
3. The power consumption management method of claim 2, wherein the monitoring whether the PCIe link is idle further comprises:
under the condition that the first judgment result is that the PCIe link does not request to be sent, judging whether the credit between the first terminal equipment and the second terminal equipment is normal or not to obtain a third judgment result;
and determining whether the PCIe link is idle according to the third judgment result and the second judgment result.
4. The power consumption management method of claim 3, wherein the determining whether the PCIe link is idle according to the third determination result and the second determination result comprises:
monitoring a logic idle symbol within a preset time length from a target moment;
determining that the PCIe link is idle when a logic idle symbol is monitored in the preset time length;
and determining that the data receiving end has no data to receive through the PCIe link and the credit amount is normal according to the second judgment result and the third judgment result.
5. The power consumption management method according to claim 1, wherein the turning off the clock of each target module in the application layer of the first terminal device, which is configured to complete data transmission, comprises:
disconnecting a connection line between a PIPE-compliant PHY module and a CLK/RST model so as to interrupt the transmission of a pclk clock generated by the PIPE-compliant PHY module to the CLK/RST model;
the PIPE-compliant PHY module is located in a physical layer of the first terminal device, and the CLK/RST model is used for generating clocks of the target modules according to the received pclk clock.
6. The power consumption management method according to claim 5, wherein the turning off the clock of each target module in the application layer of the first terminal device, which is set to complete data transmission, further comprises:
conducting clock connection between the PIPE-compliant PHY module and the CXPL module and the power control module respectively, so that a pclk clock generated by the PIPE-compliant PHY module is issued to the CXPL module and the power control module;
the CXPL module is a module in the first terminal device for implementing a common PCIe port physical sublayer, a data link layer, and a transport layer logic, and the power control module is configured to manage a power supply of the first terminal device.
7. The power consumption management method of claim 5, wherein each of the target modules comprises: a RADM module, an XADM module, and an MSGEN module.
8. The power consumption management method according to claim 1, wherein after the clock of each target module set in the application layer of the first terminal device for completing data transmission is turned off, the method further comprises:
and recovering the clock of each target module under the condition that a data receiving end of the first terminal device detects a non-logic idle symbol or the first terminal device sends a request on the PCIe link.
9. An end device, wherein the end device communicates over a PCIe link, the end device comprising a PCIe controller configured to perform the power consumption management method of any one of claims 1 to 8.
10. A computer-readable storage medium, on which a computer program is stored, wherein the program, when executed by a processor, implements a power consumption management method according to any one of claims 1-8.
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