CN113394288B - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the surface of the substrate is provided with a pseudo gate structure; forming source and drain openings in the substrates at two sides of the pseudo gate structure respectively; forming a first stress layer in the source drain opening, wherein first ions are doped in the first stress layer; forming an initial layer on the surface of the first stress layer, wherein second ions are doped in the initial layer, and the conductivity types of the first ions and the second ions are the same; and oxidizing the initial layer to form an oxide layer on the initial layer. The method is advantageous for improving the performance of the formed semiconductor structure.

Description

Semiconductor structure and method for forming the same

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof.

Background Art

With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operating speed of the entire integrated circuit can be effectively improved.

In a very large scale integrated circuit, stress is usually formed on a transistor to increase the carrier mobility of the transistor and thus increase the driving current of the transistor.

However, the performance of semiconductor devices formed by the prior art needs to be improved.

Summary of the invention

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor devices.

To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, a surface of the substrate having a pseudo gate structure; source and drain openings in the substrate respectively located on both sides of the pseudo gate structure; a first stress layer located in the source and drain openings, and the first stress layer is doped with first ions; an oxide layer located on the surface of the first stress layer, and the oxide layer is doped with second ions, and the first ions and the second ions have the same conductivity type.

Optionally, when the semiconductor to be formed is a P-type device, the material of the oxide layer includes: silicon germanium oxide; when the semiconductor to be formed is an N-type device, the material of the oxide layer includes: carbon silicon oxide.

Optionally, the doping concentration of the second ions is less than the doping concentration of the first ions.

Optionally, the first ion and the second ion are the same or different.

Optionally, the first ions and the second ions are N-type ions or P-type ions; the N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF2+.

Optionally, it also includes: a second stress layer located on the side wall surface and the bottom surface of the source and drain openings, and the first stress layer is located on the surface of the second stress layer and fills the source and drain openings.

Optionally, the second stress layer is doped with third ions, and the third ions have the same conductivity type as the first ions.

Optionally, the third ion is the same as or different from the first ion; the third ion is the same as or different from the second ion; and the doping concentration of the third ion is less than the doping concentration of the first ion.

Optionally, when the semiconductor to be formed is a P-type device, the materials of the first stress layer and the second stress layer include: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the first stress layer and the second stress layer include: carbon silicon.

Optionally, the oxide layer is further doped with stress-enhancing ions, including germanium ions, antimony ions or tin ions when the semiconductor to be formed is a P-type device; and including carbon ions when the semiconductor to be formed is an N-type device.

Optionally, the interface between the bottom of the oxide layer and the top of the first stress layer is further doped with resistance reducing ions, including gallium ions.

Optionally, it also includes: a stop barrier layer located on the surface of the oxide layer and the side wall surface of the pseudo gate structure; a dielectric layer located on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the pseudo gate structure; a conductive plug located in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, and the bottom of the conductive plug is located in the first stress layer.

Optionally, the dummy gate structure includes: a dummy gate dielectric layer located on the surface of the substrate, a dummy gate electrode layer located on the surface of the dummy gate dielectric layer, and sidewalls located on the sidewall surfaces of the dummy gate dielectric layer and the dummy gate electrode layer.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the surface of the substrate having a pseudo gate structure; forming source and drain openings in the substrate on both sides of the pseudo gate structure respectively; forming a first stress layer in the source and drain openings, and the first stress layer is doped with first ions; forming an initial layer on the surface of the first stress layer, and the initial layer is doped with second ions, and the first ions and the second ions have the same conductivity type; and oxidizing the initial layer to form an oxide layer.

Optionally, the process for forming the initial layer includes: a selective epitaxial growth process; and doping the initial layer with second ions using an in-situ ion doping process.

Optionally, when the semiconductor to be formed is a P-type device, the material of the initial layer includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the initial layer includes: carbon germanium.

Optionally, the parameters of the oxidation treatment include: a temperature range of 600 degrees Celsius to 800 degrees Celsius, a treatment time of 20 minutes to 60 minutes, and an oxygen atmosphere gas including: oxygen or ozone.

Optionally, the process for forming the first stress layer includes: a selective epitaxial growth process; and doping the first ions in the first stress layer using an in-situ ion doping process.

Optionally, it also includes: after forming the source and drain openings and before forming the first stress layer, forming a second stress layer on the side wall surfaces and bottom surfaces of the source and drain openings; after forming the second stress layer, forming the first stress layer on the surface of the second stress layer, and the first stress layer completely fills the source and drain openings.

Optionally, the process for forming the second stress layer includes: a selective epitaxial growth process; and doping third ions in the second stress layer using an in-situ ion doping process.

Optionally, it also includes: doping stress enhancement ions in the oxide layer, when the semiconductor to be formed is a P-type device, including: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, including: carbon ions.

Optionally, the method further includes: doping resistance-reducing ions, including gallium ions, at the interface between the bottom of the oxide layer and the top surface of the first stress layer.

Optionally, the method for forming the source-drain openings includes: using the dummy gate structure as a mask, etching the substrate, and forming the source-drain openings.

Optionally, it also includes: forming a stop barrier layer on the surface of the oxide layer and the side wall surface of the pseudo gate structure; forming a dielectric layer on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the pseudo gate structure; forming a conductive plug in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, and the bottom of the conductive plug is located in the first stress layer.

Optionally, the method for forming the conductive plug includes: forming a through hole in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, and exposing the first stress layer at the bottom of the through hole; forming a conductive material film in the through hole and on the surface of the dielectric layer; and flattening the conductive material film until the surface of the dielectric layer is exposed to form the conductive plug.

Optionally, the method for forming the pseudo gate structure includes: forming a pseudo gate dielectric film on the surface of the substrate; forming a pseudo gate electrode film on the surface of the pseudo gate dielectric film; patterning the pseudo gate dielectric film and the pseudo gate electrode film until the substrate surface is exposed, so that the pseudo gate dielectric film forms a pseudo gate dielectric layer, and the pseudo gate electrode film forms a pseudo gate electrode; forming a sidewall material film on the top surface and sidewall surface of the pseudo gate electrode layer, and on the sidewall surface of the pseudo gate dielectric layer; etching back the sidewall material film until the substrate surface is exposed, and forming sidewalls on the sidewall surfaces of the pseudo gate dielectric layer and the pseudo gate electrode layer.

Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

In the method for forming a semiconductor structure provided by the technical solution of the present invention, the initial layer is oxidized to form an oxide layer. On the one hand, the oxide layer formed after the oxidation treatment can still effectively protect the first stress layer, so that the stress of the first stress layer is not released during the subsequent heat treatment process. On the other hand, the second ions are not easy to diffuse in the oxide layer, and thus are not easy to diffuse into the channel under the pseudo gate structure, which effectively improves the short channel effect and makes the performance of the formed semiconductor structure better.

Furthermore, stress-enhancing ions are doped into the oxide layer, including germanium ions, antimony ions or tin ions when the semiconductor to be formed is a P-type device; and carbon ions when the semiconductor to be formed is an N-type device. By doping the stress-enhancing ions, the stress of the oxide layer can be increased, that is, the stress of the oxide layer on the channel is increased, thereby increasing the driving current of the semiconductor structure, so that the performance of the formed semiconductor structure is better.

Furthermore, resistance reducing ions are doped at the interface between the bottom of the oxide layer and the top surface of the first stress layer. Due to the doping of the resistance reducing ions, an ohmic contact can be formed between the subsequently formed conductive plug and the first stress layer located in the source and drain openings, thereby reducing the contact resistance between the first stress layer and the conductive plug, which is beneficial to improving the performance of the formed semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 4 are schematic structural diagrams of various steps of a method for forming a semiconductor structure;

5 to 13 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in an embodiment of the present invention.

DETAILED DESCRIPTION

As described in the background art, the performance of existing semiconductor structures is poor.

The reasons why the performance of the semiconductor structure is poor are described in detail below with reference to the accompanying drawings. FIG. 1 to FIG. 4 are schematic diagrams of the structures of the steps of a method for forming a semiconductor structure.

Referring to FIG. 1 , a substrate 100 is provided. A dummy gate structure 110 is formed on a surface of the substrate 100 , and sidewall spacers 120 are formed on two sides of the dummy gate structure 110 .

Referring to FIG. 2 , source and drain openings 130 are formed in the substrate 100 on both sides of the dummy gate structure 110 and the spacer 120 .

Referring to FIG. 3 , a first stress layer 140 is formed on the bottom and sidewall surfaces of the source/drain opening 130 ; and a second stress layer 150 is formed on the surface of the first stress layer 140 .

Referring to FIG. 4 , a protection layer 160 is formed on the surface of the second stress layer 150 .

In the above method, the first stress layer 140 and the second stress layer 150 together form a source-drain doped region. The protective layer 160 located on the surface of the second stress layer 150 can effectively reduce the stress release caused by the source-drain doped region, especially the second stress layer 150, being heated in the subsequent thermal process. Therefore, the protective layer 160 is conducive to maintaining the stress of the source-drain doped region.

However, the formation process of the protective layer 160 is a selective epitaxial growth process, and an in-situ ion doping process is used to dope ions in the protective layer 160. Specifically, the material of the formed protective layer 160 is silicon germanium, and the concentration of germanium in the silicon germanium material is low, and the doped ions are easy to diffuse in the protective layer 160 with a low germanium concentration, and then easily diffuse into the channel under the pseudo gate structure 110, causing a short channel effect, so that the performance of the semiconductor structure is poor.

It should be noted that the concentration of germanium in the silicon germanium material refers to the ratio of the amount of germanium to the amount of silicon.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, wherein an initial layer is formed on the surface of the first stress layer, and the initial layer is doped with second ions, and the first ions and the second ions have the same conductivity type; the initial layer is oxidized to form an oxide layer. The second ions are not easily diffused in the oxide layer, so that the formed semiconductor structure has better performance.

In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

5 to 13 are schematic structural diagrams of various steps of a method for forming a semiconductor structure in an embodiment of the present invention.

Please refer to FIG. 5 , a substrate 200 is provided, and a dummy gate structure 210 is formed on the surface of the substrate 200 .

In this embodiment, the base 200 includes a substrate and a fin located on a surface of the substrate. The dummy gate structure 210 spans across the fin and covers a portion of the top surface and sidewall surface of the fin.

In other embodiments, the substrate has no fins thereon.

In this embodiment, the method for forming the base 200 includes: providing an initial substrate (not shown); the initial substrate has a first patterned layer, and the first patterned layer exposes a portion of the surface of the initial substrate; using the first patterned layer as a mask, etching the initial substrate to form the substrate 201 and the fin located on the surface of the substrate.

In this embodiment, the material of the initial substrate is silicon. Accordingly, the material of the substrate and the fin is silicon.

In other embodiments, the material of the initial substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. Correspondingly, the material of the substrate includes: germanium, silicon germanium, silicon on insulator or germanium on insulator. The material of the fin includes: germanium, silicon germanium, silicon on insulator or germanium on insulator.

In this embodiment, the dummy gate structure 210 includes: a dummy gate dielectric layer 211 located on the surface of the substrate 200, a dummy gate electrode layer 212 located on the surface of the dummy gate dielectric layer 211, and a sidewall 213 located on the sidewall surface of the dummy gate dielectric layer 211 and the dummy gate electrode layer 212.

In other embodiments, the dummy gate structure does not include the spacer.

The method for forming the pseudo gate structure 210 includes: forming a pseudo gate dielectric film (not shown in the figure) on the surface of the substrate; forming a pseudo gate electrode film (not shown in the figure) on the surface of the pseudo gate dielectric film; patterning the pseudo gate dielectric film and the pseudo gate electrode film until the substrate surface is exposed, so that the pseudo gate dielectric film forms a pseudo gate dielectric layer 211, and the pseudo gate electrode film forms a pseudo gate electrode 212; forming a sidewall material film on the top surface and sidewall surface of the pseudo gate electrode layer 212, and on the sidewall surface of the pseudo gate dielectric layer 211; etching back the sidewall material film until the substrate surface is exposed, and forming sidewalls 213 on the sidewall surfaces of the pseudo gate dielectric layer 211 and the pseudo gate electrode layer 212.

In this embodiment, the method for forming the semiconductor structure further includes: forming a blocking layer (not shown in the figure) on the top surface of the dummy gate structure 210 .

The barrier layer is used to protect the surface of the dummy gate structure 210 from being affected by the process in subsequent process steps, thereby maintaining a good morphology.

Referring to FIG. 6 , source and drain openings 220 are formed in the substrate 200 at both sides of the dummy gate structure 210 .

The source/drain openings 220 provide space for subsequently forming a first stress layer and a second stress layer.

Specifically, in this embodiment, the source-drain openings 220 are located in the fins on both sides of the dummy gate structure 210 .

The method for forming the source-drain opening 220 includes: using the dummy gate structure as a mask and etching the substrate to form the source-drain opening 200 .

In this embodiment, the process of etching the substrate 200 includes: anisotropic dry etching.

Referring to FIG. 7 , a second stress layer 230 is formed on the sidewall surfaces and the bottom surface of the source/drain opening 220 .

The formation process of the second stress layer 230 includes: a selective epitaxial growth process; and an in-situ ion doping process to dope the second stress layer 230 with third ions.

When the semiconductor to be formed is a P-type device, the material of the second stress layer 230 includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the second stress layer 230 includes: carbon germanium.

The third ion is an N-type ion or a P-type ion; the N-type ion includes a phosphorus ion or an arsenic ion; the P-type ion includes a boron ion, an indium ion or BF ²⁺ .

In this embodiment, the semiconductor to be formed is a P-type device, the material forming the second stress layer 230 is silicon germanium, the third ion doped is boron, the germanium concentration in the silicon germanium material is 0.1-0.3, and the boron ion concentration is 1e18 atm/cm ³ -1e19atm/cm ³ .

Since the germanium concentration in the silicon germanium material is relatively low, the stress of the second stress layer 230 is relatively small, and a good buffering effect can be provided between the substrate 200 and the subsequently formed first stress layer having a relatively large stress.

Please refer to FIG. 8 . After the second stress layer 230 is formed, a first stress layer 240 is formed on the surface of the second stress layer 230 , and the first layer 240 completely fills the source/drain openings 220 (as shown in FIG. 6 ).

The first stress layer 240 and the second stress layer 230 are used together as source and drain doping regions.

The formation process of the first stress layer 240 includes: a selective epitaxial growth process; and an in-situ ion doping process to dope the first ions in the first stress layer 240 .

When the semiconductor to be formed is a P-type device, the material of the first stress layer 240 includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the first stress layer 240 includes: carbon germanium.

The first ions and the third ions have the same conductivity type.

The first ions are N-type ions or P-type ions; the N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF ²⁺ .

The first ion and the third ion are the same or different. In this embodiment, the first ion and the third ion are the same, that is, boron ions.

In this embodiment, the material of the first stress layer 240 is silicon germanium, the first doped ions are boron ions, the concentration of germanium in the silicon germanium material is 0.4-0.6, and the concentration of the boron ions is 1e20atm/cm ³ -1e21atm/cm ³ .

The germanium concentration in the silicon germanium material of the first stress layer 240 is relatively high, and the first stress layer 240 occupies the main volume of the source-drain opening 220. The first stress layer 240 exerts a relatively large stress on the channel, so that the first stress layer 240 and the second stress layer 230 located in the source-drain opening 220 jointly serve as source-drain doping regions and exert a relatively large stress on the channel, which is beneficial to enhancing the migration rate of carriers, increasing the driving current of the semiconductor device, and improving the response speed of the circuit.

Referring to FIG. 9 , an initial layer 250 is formed on the surface of the first stress layer 240 , and second ions are doped in the initial layer 250 . The first ions and the second ions have the same conductivity type.

The initial layer 250 can protect the first stress layer 240 located at the bottom of the initial layer 250 , and effectively prevent the first stress layer 240 from being heated and causing the stress to be released during the subsequent thermal process.

When the semiconductor to be formed is a P-type device, the material of the initial layer 250 includes: silicon germanium; when the semiconductor to be formed is an N-type device, the material of the initial layer 250 includes: carbon germanium.

In this embodiment, the material of the initial layer 250 is silicon germanium.

The second ion is an N-type ion or a P-type ion.

The N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF ²⁺ .

The second ion and the first ion are the same or different.

In this embodiment, the first ions and the second ions are the same, that is, boron ions.

In this embodiment, the material of the initial layer 250 is silicon germanium, the first ions doped are boron ions, the concentration of germanium in the silicon germanium material is 0.1-0.2, and the concentration of the boron ions is 5e19atm/cm ³ -5e20atm/cm ³ .

The doping concentration of the second ions is lower than the doping concentration of the first ions.

Referring to FIG. 10 , the initial layer 250 is oxidized to form an oxide layer 260 .

The parameters of the oxidation treatment include: a temperature range of 600 degrees Celsius to 800 degrees Celsius, a treatment time of 20 minutes to 60 minutes, and an oxygen atmosphere gas including: oxygen or ozone.

Through the oxidation process, the material of the initial layer 250 is oxidized.

When the semiconductor to be formed is a P-type device, the material of the oxide layer includes: silicon germanium oxide; when the semiconductor to be formed is an N-type device, the material of the oxide layer includes: carbon silicon oxide.

In this embodiment, the material of the oxide layer 260 is silicon germanium oxide, and the oxide layer 260 is doped with second ions, namely boron ions.

The initial layer 250 is oxidized to form an oxide layer 260. On the one hand, the oxide layer 260 formed after the oxidation treatment can still effectively protect the first stress layer 240, so that the stress of the first stress layer 240 is not released during the subsequent heat treatment process. On the other hand, the second ions are not easy to diffuse in the oxide layer 260, and then are not easy to diffuse into the channel under the pseudo gate structure 210, which effectively improves the short channel effect and makes the formed semiconductor structure have better performance.

Please refer to Figure 11. Stress enhancing ions are doped in the oxide layer 260. When the semiconductor to be formed is a P-type device, they include: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, they include: carbon ions; resistance reducing ions are doped at the interface between the bottom of the oxide layer 260 and the top surface of the first stress layer, including: gallium ions.

By doping the stress enhancement ions, the stress of the oxide layer 260 can be increased, that is, the stress of the oxide layer 260 on the channel is increased, thereby improving the driving current of the semiconductor structure, so that the performance of the formed semiconductor structure is better.

Resistance reducing ions are doped at the interface between the bottom of the oxide layer 260 and the top surface of the first stress layer 240. Due to the doping of the resistance reducing ions, an ohmic contact can be formed between the subsequently formed conductive plug and the first stress layer 240 located in the source and drain openings, thereby reducing the contact resistance between the first stress layer 240 and the conductive plug, which is beneficial to improving the performance of the formed semiconductor structure.

In this embodiment, the process of doping stress-enhancing ions and the process of doping resistance-reducing ions are achieved by simultaneously performing ion implantation processes.

In this embodiment, after doping the stress enhancing ions and doping the resistance reducing ions, a heat treatment is further included. The heat treatment is used to activate the stress enhancing ions and the resistance reducing ions on the one hand, and to repair lattice damage on the other hand.

12 , a stop barrier layer 271 is formed on the surface of the oxide layer 260 and the sidewall surface of the dummy gate structure 210 ; a dielectric layer 272 is formed on the surface of the stop barrier layer 271 , and the top surface of the dielectric layer 272 is higher than or flush with the top surface of the dummy gate structure 210 .

The stop barrier layer 271 is used as a stop layer for subsequent etching.

The dielectric layer 272 is used to provide support for subsequent device formation.

The material of the stop barrier 271 is different from the material of the dielectric layer 272. In this embodiment, the material of the stop barrier layer 271 is silicon nitride; the material of the dielectric layer 272 is silicon oxide.

Referring to FIG. 13 , a conductive plug 280 is formed in the dielectric layer 272 , the stop barrier layer 271 , the oxide layer 260 and the first stress layer 250 , and the bottom of the conductive plug 280 is located in the first stress layer 250 .

The conductive plug 280 is used to electrically connect the source and drain doped regions with the peripheral circuit.

The method for forming the conductive plug 280 includes: forming a through hole (not shown in the figure) in the dielectric layer 272, the stop barrier layer 271, the oxide layer 260 and the first stress layer 240, and exposing the first stress layer 240 at the bottom of the through hole; forming a conductive material film (not shown in the figure) in the through hole and on the surface of the dielectric layer 272; and planarizing the conductive material film until the surface of the dielectric layer 272 is exposed to form the conductive plug 280.

Since the interface between the bottom of the oxide layer 260 and the top surface of the first stress layer 240 is doped with resistance-reducing ions, an ohmic resistance is formed between the conductive plug 280 and the first stress layer 240 and the contact surface of the oxide layer 260, which effectively reduces the contact resistance and makes the formed semiconductor structure have better performance.

Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above method, please continue to refer to Figure 13, including: a substrate 200, the surface of the substrate 200 has a pseudo gate structure 210; source and drain openings 220 (as shown in Figure 6) in the substrate 200 respectively located on both sides of the pseudo gate structure 210; a first stress layer 240 located in the source and drain openings 220, and the first stress layer 240 is doped with first ions; an oxide layer 250 located on the surface of the first stress layer 240, and the oxide layer 250 is doped with second ions, and the first ions and the second ions have the same conductivity type.

The following is a detailed description with reference to the accompanying drawings.

In this embodiment, the base 200 includes a substrate and a fin located on a surface of the substrate, and the dummy gate structure 210 spans across the fin and covers a portion of the top surface and sidewall surface of the fin.

In other embodiments, the substrate has no fins thereon.

In this embodiment, the dummy gate structure 210 includes: a dummy gate dielectric layer 211 located on the surface of the substrate 200, a dummy gate electrode layer 212 located on the surface of the dummy gate dielectric layer 211, and a sidewall 213 located on the sidewall surface of the dummy gate dielectric layer 211 and the dummy gate electrode layer 212.

When the semiconductor to be formed is a P-type device, the material of the oxide layer 260 includes: silicon germanium oxide; when the semiconductor to be formed is an N-type device, the material of the oxide layer 260 includes: carbon silicon oxide.

The doping concentration of the second ions is lower than the doping concentration of the first ions.

The first ion and the second ion are the same or different.

The first ions and the second ions are N-type ions or P-type ions; the N-type ions include phosphorus ions or arsenic ions; the P-type ions include boron ions, indium ions or BF ²⁺ .

In this embodiment, the first ions and the second ions are the same, both being boron ions.

The semiconductor structure further includes: a second stress layer 230 located on the sidewall surface and the bottom surface of the source/drain opening 220 ; and a first stress layer 240 located on the surface of the second stress layer 230 and completely filling the source/drain opening 220 .

The second stress layer 230 is doped with third ions, and the third ions have the same conductivity type as the first ions.

The third ion is the same as or different from the first ion; the third ion is the same as or different from the second ion; the doping concentration of the third ion is less than the doping concentration of the first ion.

When the semiconductor to be formed is a P-type device, the materials of the first stress layer 240 and the second stress layer 230 include: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the first stress layer 240 and the second stress layer 230 include: carbon silicon.

The oxide layer 260 is also doped with stress-enhancing ions, including germanium ions, antimony ions or tin ions when the semiconductor to be formed is a P-type device; and including carbon ions when the semiconductor to be formed is an N-type device.

The interface between the bottom of the oxide layer 260 and the top of the first stress layer 240 is also doped with resistance reducing ions, including gallium ions.

The semiconductor structure also includes: a stop barrier layer 271 located on the surface of the oxide layer 260 and the side wall surface of the dummy gate structure 210; a dielectric layer 272 located on the surface of the stop barrier layer 271, and the top surface of the dielectric layer 272 is higher than or flush with the top surface of the dummy gate structure 210; a conductive plug 280 located in the dielectric layer 272, the stop barrier layer 271, the oxide layer 260 and the first stress layer 240, and the bottom of the conductive plug 280 is located in the first stress layer 240.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (26)

1. A semiconductor structure, comprising:

The substrate is provided with a pseudo gate structure on the surface;

source and drain openings respectively located in the substrate at two sides of the pseudo gate structure;

the first stress layer is positioned in the source-drain opening and is doped with first ions; the oxide layer is positioned on the surface of the first stress layer, second ions are doped in the oxide layer, the conductivity types of the first ions and the second ions are the same, and resistance reducing ions are doped at the interface between the bottom of the oxide layer and the top of the first stress layer.

2. The semiconductor structure of claim 1, wherein when the semiconductor to be formed is a P-type device, the oxide layer comprises a material comprising: silicon germanium oxide; when the semiconductor to be formed is an N-type device, the oxide layer comprises the following materials: and a carbon-silicon oxide.

3. The semiconductor structure of claim 1, wherein a doping concentration of the second ion is less than a doping concentration of the first ion.

4. The semiconductor structure of claim 1, wherein the first ion and the second ion are the same or different.

5. The semiconductor structure of claim 1, wherein the first ions and the second ions are N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include: boron ions, indium ions, or BF ²⁺.

6. The semiconductor structure of claim 1, further comprising: and the first stress layer is positioned on the surface of the second stress layer and fills the source-drain opening.

7. The semiconductor structure of claim 6, wherein the second stress layer is doped with a third ion, the third ion being of the same conductivity type as the first ion.

8. The semiconductor structure of claim 7, wherein the third ion is the same as or different from the first ion; the third ion is the same as or different from the second ion; the doping concentration of the third ion is smaller than the doping concentration of the first ion.

9. The semiconductor structure of claim 6, wherein when the semiconductor to be formed is a P-type device, the materials of the first stress layer and the second stress layer comprise: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the first stress layer and the second stress layer include: carbon silicon.

10. The semiconductor structure of claim 1, wherein said oxide layer is further doped with stress enhancing ions, when the semiconductor to be formed is a P-type device, comprising: germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method comprises: and (3) carbon ions.

11. The semiconductor structure of claim 1, wherein the resistance-reducing ions comprise: gallium ions.

12. The semiconductor structure of claim 1, further comprising: the stop barrier layer is positioned on the surface of the oxide layer and the surface of the side wall of the pseudo gate structure; the dielectric layer is positioned on the surface of the stop barrier layer, and the top surface of the dielectric layer is higher than or flush with the top surface of the pseudo gate structure; a conductive plug in the dielectric layer, stop barrier layer, oxide layer and first stress layer, and the bottom of the conductive plug is positioned in the first stress layer.

13. The semiconductor structure of claim 1, wherein the dummy gate structure comprises: the device comprises a dummy gate dielectric layer positioned on the surface of a substrate, a dummy gate electrode layer positioned on the surface of the dummy gate dielectric layer, and a side wall positioned on the side wall surfaces of the dummy gate dielectric layer and the dummy gate electrode layer.

14. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the surface of the substrate is provided with a pseudo gate structure;

forming source and drain openings in the substrates at two sides of the pseudo gate structure respectively;

forming a first stress layer in the source drain opening, wherein first ions are doped in the first stress layer;

Forming an initial layer on the surface of the first stress layer, wherein second ions are doped in the initial layer, and the conductivity types of the first ions and the second ions are the same;

oxidizing the initial layer to form an oxide layer;

doping resistance reducing ions at the interface of the oxide layer bottom and the first stress layer top surface.

15. The method of forming a semiconductor structure of claim 14, wherein the initial layer forming process comprises: a selective epitaxial growth process; and doping second ions in the initial layer by adopting an in-situ ion doping process.

16. The method of forming a semiconductor structure of claim 14, wherein when the semiconductor to be formed is a P-type device, the material of the initiation layer comprises: silicon germanium; when the semiconductor to be formed is an N-type device, the materials of the initial layer include: carbon germanium.

17. The method of forming a semiconductor structure of claim 14, wherein the parameters of the oxidation process comprise: the temperature range is 600-800 ℃, the treatment time is 20-60 minutes, and the oxygen atmosphere comprises: oxygen or ozone.

18. The method of forming a semiconductor structure of claim 14, wherein the first stress layer forming process comprises: a selective epitaxial growth process; and doping first ions in the first stress layer by adopting an in-situ ion doping process.

19. The method of forming a semiconductor structure of claim 14, further comprising: forming a second stress layer on the side wall surface and the bottom surface of the source-drain opening after forming the source-drain opening and before forming the first stress layer; after the second stress layer is formed, the first stress layer is formed on the surface of the second stress layer, and the source and drain openings are filled with the first stress layer.

20. The method of forming a semiconductor structure of claim 19, wherein the process of forming the second stress layer comprises: a selective epitaxial growth process; and doping third ions in the second stress layer by adopting an in-situ ion doping process.

21. The method of forming a semiconductor structure of claim 14, further comprising: doping stress enhancement ions in the oxide layer, when the semiconductor to be formed is a P-type device, the method comprises the following steps:

germanium ions, antimony ions or tin ions; when the semiconductor to be formed is an N-type device, the method comprises: and (3) carbon ions.

22. The method of forming a semiconductor structure of claim 14, wherein the resistance-reducing ions comprise: gallium ions.

23. The method of forming a semiconductor structure of claim 14, wherein the method of forming a source drain opening comprises: and etching the substrate by taking the pseudo gate structure as a mask to form the source drain opening.

24. The method of forming a semiconductor structure of claim 14, further comprising: forming a stop barrier layer on the surface of the oxide layer and the surface of the side wall of the pseudo gate structure; forming a dielectric layer on the surface of the stop barrier layer, wherein the top surface of the dielectric layer is higher than or flush with the top surface of the pseudo gate structure; and forming a conductive plug in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, wherein the bottom of the conductive plug is positioned in the first stress layer.

25. The method of forming a semiconductor structure of claim 24, wherein the method of forming a conductive plug comprises: forming a through hole in the dielectric layer, the stop barrier layer, the oxide layer and the first stress layer, wherein the bottom of the through hole exposes the first stress layer; forming a conductive material film in the through hole and on the surface of the dielectric layer; and flattening the conductive material film until the surface of the dielectric layer is exposed, and forming the conductive plug.

26. The method of forming a semiconductor structure of claim 14, wherein the method of forming a dummy gate structure comprises: forming a pseudo gate dielectric film on the surface of the substrate; forming a pseudo gate electrode film on the surface of the pseudo gate dielectric film; patterning the dummy gate dielectric film and the dummy gate electrode film until the substrate surface is exposed, so that the dummy gate dielectric film forms a dummy gate dielectric layer and the dummy gate electrode film forms a dummy gate electrode; forming a side wall material film on the top surface and the side wall surface of the pseudo gate electrode layer and the side wall surface of the pseudo gate dielectric layer; and etching the side wall material film until the substrate surface is exposed, and forming side walls on the side wall surfaces of the pseudo gate dielectric layer and the pseudo gate electrode layer.