CN113505063B - FPGA logic test method and device - Google Patents

Abstract

The invention belongs to the technical field of integrated circuits, and specifically provides an FPGA logic testing method and device. The method includes: determining the required resource storage amount required for testing the logic source code to be tested based on the bandwidth of the signal to be tested and the sampling depth of the logic source code to be tested; if the required resource storage amount is less than the remaining storage amount of the FPGA on-chip memory, Then determine the storage mode as on-chip storage, otherwise determine the storage mode as off-chip storage; among them, the memory corresponding to the on-chip storage is the FPGA on-chip memory, and the memory corresponding to the off-chip storage is the external memory; The test logic source code is tested, and the sampled data generated by the test is stored in the corresponding memory according to the determined storage mode. The present application can avoid the problem of low sampling depth caused by internal storage space during FPGA testing, thereby effectively improving the sampling depth during testing.

Description

FPGA logic testing method and device

technical field

The present invention relates to the technical field of integrated circuits, in particular to a method and device for FPGA logic testing.

Background technique

FPGA (Field Pragrammable Gate Array, Field Programmable Gate Array) is a general-purpose device that contains a large number of repetitive programmable logic blocks (CLB), input and output units (IOB), programmable interconnect lines (PI) and other basic units. It is especially suitable for the development of new products of integrated circuits and the production of small batches of ASIC circuits. With its rapid development, it has been widely used in many fields. With the wide application of FPGA, the requirements for its accuracy are getting higher and higher, so it is necessary to verify the FPGA reasonably through testing.

Currently, there are usually two methods for FPGA logic testing: one is a method using an external oscilloscope or logic analyzer, and the other is a method using an embedded logic analyzer. The method of using an external oscilloscope or logic analyzer requires routing the internal signal to be tested to the unused pins of the FPGA, and then connecting it to an external oscilloscope or logic analyzer for observation. This method can provide deeper memory, However, the number of pins dedicated to debugging must be increased, occupying additional I/O pins.

The method of using the embedded logic analyzer is based on the embedded logic analyzer core of the FPGA manufacturer, obtains the internal resources of the FPGA to realize signal sampling and storage, and transmits the captured data to the PC for display through the JTAG interface. This method is limited by the internal storage resources of the FPGA, which results in the limited sampling depth (sampling data storage) of the signal, and cannot meet the requirements of the test scenarios that require a high number of test samples.

SUMMARY OF THE INVENTION

In view of the defects in the prior art, the present invention provides an FPGA logic testing method and device, electronic equipment and medium to solve the problem of limited signal sampling depth when using an embedded logic analyzer for FPGA logic testing.

A first aspect, a kind of FPGA logic testing method provided by the present invention, comprises:

Determine the required resource storage amount required for testing the logic source code to be tested based on the bandwidth of the signal to be tested and the sampling depth of the logic source code to be tested;

If the required resource storage amount is less than the remaining storage amount of the FPGA on-chip memory, the storage method is determined to be on-chip storage, otherwise, the storage method is determined to be off-chip storage; wherein, the memory corresponding to the on-chip storage is the FPGA on-chip memory, and the on-chip storage The memory corresponding to the external storage is the external memory;

The logic source code to be tested is tested based on the embedded logic analyzer core, and the sampled data generated by the test is stored in the corresponding memory according to the determined storage mode.

It can be seen from the above technical solutions that the FPGA logic testing method provided by the present invention determines the storage mode according to the relationship between the required resource storage and the remaining on-chip storage. When the required resource storage is greater than the remaining on-chip storage, the Selecting an appropriate storage method for data storage can effectively increase the sampling depth and make full use of existing resources without additional design overhead.

Optionally, when the storage mode is off-chip storage, the sampling data generated by the test is stored in the corresponding memory according to the determined storage mode, including:

Write the sampled data generated by the test into the FPGA on-chip memory;

When the data amount of the sampled data written into the FPGA on-chip memory satisfies a preset condition, the sampled data in the FPGA on-chip memory is stored in the external memory.

Optionally, the method further includes:

Record the number of times of writing sampling data into the FPGA on-chip memory;

If the number of writes is not less than the data transfer threshold, it is determined that the data amount of the sampled data written in the FPGA on-chip memory meets a preset condition, and the number of writes is cleared, wherein the data transfer threshold is It is determined based on the required resource storage amount and the bandwidth of the signal to be tested.

其中，Y为所述FPGA片内存储器的剩余存储量，K为待测试信号带宽，n为大于1的数值。Optionally, the data transfer threshold is

Wherein, Y is the remaining storage capacity of the on-chip memory of the FPGA, K is the bandwidth of the signal to be tested, and n is a value greater than 1.

Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the storing of the sampled data in the FPGA on-chip memory into the external memory includes:

The sampled data to be stored in the external memory in the FPGA on-chip memory is sequentially stored in the data write buffer, the data width of the sampled data in the data write buffer is modified to C, and the data width in the data write buffer Store the sampled data for C into the external memory.

Optionally, the method further includes:

X为所述需求资源存储量，R为所述FPGA片内存储器的数据宽度，L为所述FPGA片内存储器剩余的数据深度；According to the required resource storage amount, a part of the space is selected in the external memory, and the part of the space is divided into N data blocks, wherein,

X is the required resource storage amount, R is the data width of the FPGA on-chip memory, and L is the remaining data depth of the FPGA on-chip memory;

The storing of the sampled data in the FPGA on-chip memory into the external memory includes:

The sampling data in the on-chip memory of the FPGA is sequentially stored in the data blocks of the external memory.

Optionally, after the embedded logic analyzer is tested, the method further includes:

The data blocks storing the sampled data in the external memory are sequentially written into the FPGA on-chip memory;

After each data block is read out, the next data block is written into the on-chip memory to refresh the on-chip memory until the data block is read out.

Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the sequential writing of the data blocks stored in the external memory to the FPGA on-chip memory includes:

The data blocks in the external memory are stored in the data read buffer in turn, the data width of the data blocks in the data read buffer is modified to C, and the data blocks with a data width of C in the data read buffer are stored in the data read buffer. FPGA on-chip memory.

Optionally, the external memory is an FPGA configuration chip, wherein the FPGA configuration chip is a chip used to store the FPGA program when the FPGA is powered off, and when the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program to the FPGA, At this time, the FPGA configuration chip is in an idle state.

In the second aspect, a FPGA logic test device provided by the present invention includes:

a storage capacity determination module, configured to determine the required resource storage capacity required for testing the logic source code to be tested based on the bandwidth of the signal to be tested and the sampling depth of the logic source code to be tested;

The storage mode determination module is used to determine that the storage mode is on-chip storage if the required resource storage amount is less than the remaining storage capacity of the FPGA on-chip memory, otherwise, the storage mode is determined to be off-chip storage; wherein, the memory corresponding to the on-chip storage It is the on-chip memory of the FPGA, and the memory corresponding to the off-chip memory is the external memory;

The test storage module is used to test the logic source code to be tested based on the embedded logic analyzer core, and store the sampled data generated by the test into the corresponding memory according to the determined storage mode.

Optionally, when the storage mode is off-chip storage, the test storage module is specifically used for:

Write the sampled data generated by the test into the FPGA on-chip memory;

When the data amount of the sampled data written into the FPGA on-chip memory satisfies a preset condition, the sampled data in the FPGA on-chip memory is stored in the external memory.

Optionally, the device also includes a counting module:

Record the number of times of writing sampling data into the FPGA on-chip memory;

If the number of writes is not less than the data transfer threshold, it is determined that the data amount of the sampled data written in the FPGA on-chip memory meets a preset condition, and the number of writes is cleared, wherein the data transfer threshold is It is determined based on the required resource storage amount and the bandwidth of the signal to be tested.

其中，Y为所述FPGA片内存储器的剩余存储量，K为待测试信号带宽，n为大于1的数值。Optionally, in the counting module, the data transfer threshold is

Wherein, Y is the remaining storage capacity of the on-chip memory of the FPGA, K is the bandwidth of the signal to be tested, and n is a value greater than 1.

Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the test storage module is specifically used for:

The sampled data to be stored in the external memory in the FPGA on-chip memory is sequentially stored in the data write buffer, the data width of the sampled data in the data write buffer is modified to C, and the data width in the data write buffer Store the sampled data for C into the external memory.

Optionally, the device further includes a space selection module, which is specifically used for:

X为所述需求资源存储量，R为所述FPGA片内存储器的数据宽度，L为所述FPGA片内存储器剩余的数据深度；According to the required resource storage amount, a part of the space is selected in the external memory, and the part of the space is divided into N data blocks, wherein,

X is the required resource storage amount, R is the data width of the FPGA on-chip memory, and L is the remaining data depth of the FPGA on-chip memory;

The test storage module is also specifically used for:

The sampling data in the on-chip memory of the FPGA is sequentially stored in the data blocks of the external memory.

Optionally, the device further includes a data migration module, which is specifically used for:

After the embedded logic analyzer test is completed, the data blocks storing the sampled data in the external memory are sequentially written into the FPGA on-chip memory;

After each data block is read out, the next data block is written into the on-chip memory to refresh the on-chip memory until the data block is read out.

Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the test memory module is also used for:

The data blocks in the external memory are stored in the data read buffer in turn, the data width of the data blocks in the data read buffer is modified to C, and the data blocks with a data width of C in the data read buffer are stored in the data read buffer. FPGA on-chip memory.

Optionally, the external memory specifically used by the test module is an FPGA configuration chip, wherein the FPGA configuration chip is a chip used to store the FPGA program when the FPGA is powered off, and when the FPGA is powered on, the FPGA configuration chip will store the FPGA program. The FPGA program is sent to the FPGA, and the FPGA configuration chip is in an idle state at this time.

In a third aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements any of the above when executing the computer program steps of the method.

In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the steps of any one of the above methods are implemented.

Adopt the above-mentioned technical scheme, have the following beneficial effects:

1) This application proposes an FPGA logic testing method. By converting the sampling signal from internal RAM storage to external memory storage, it solves the problem of insufficient sampling depth due to limited internal storage resources in the FPGA without adding additional storage. space, increasing the sampling depth of the test. At the same time, the present application adopts an embedded logic analyzer, which is different from an external oscilloscope or analyzer, and does not need to lead out all the signals to be tested to the FPGA pins, so it is not limited by the number of spare IO pins of the FPGA.

2) For the FPGA logic testing method proposed in the present application, data can be exchanged between the on-chip memory and the external memory, so that the logic testing is not limited by on-chip memory resources, and the sampling depth during FPGA logic testing is improved.

3) The present application utilizes an external memory to store the logic code to be tested, wherein the external memory can be a configuration chip, and the sampling depth is improved without additional external memory, thereby reducing the cost.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that are required to be used in the description of the specific embodiments or the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. In the drawings, each element or section is not necessarily drawn to actual scale.

1 shows a schematic diagram of an application scenario of the FPGA logic testing method provided by an embodiment of the present invention;

2 shows a flowchart of an FPGA logic testing method provided by an embodiment of the present invention;

3 shows a space mapping diagram of an on-chip memory and an external memory provided by an embodiment of the present invention;

4 shows a schematic structural diagram of an FPGA logic testing device provided by an embodiment of the present invention;

FIG. 5 shows a schematic structural diagram of an electronic device provided by an embodiment of the present invention.

Detailed ways

Embodiments of the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only used to illustrate the technical solutions of the present invention more clearly, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art to which the present invention belongs.

When using an embedded logic analyzer to test FPGA logic, it often occurs that the data volume of the logic source code to be tested is larger than the internal storage space and the sampling depth is not high. When this problem is encountered, an external memory is often used to store the logic source code to be tested. This will bring additional external memory cost to the test process, and will prolong the logic test time and reduce the test efficiency.

Referring to FIG. 1, FIG. 1 is a schematic diagram of an application scenario of an FPGA logic testing method provided by an embodiment of the present invention. By setting an embedded logic analyzer core, a signal to be tested is set as a sampling signal, and the logic code to be tested is sampled. At the same time, the sampled signal will be written to the internal RAM for storage, and the logic analyzer will send the signal to the display through the JTAG interface. When the internal RAM does not meet the depth requirements of the sampling signal, the internal RAM can be connected to an external memory, and the sampling signal can be stored through the external memory. This method has a good effect when the demand for storage is large, but when the demand for storage is very small. , direct storage through the external memory will prolong the test time and cause the problem of low test efficiency. Based on this, the present application proposes a logic testing method, which is determined according to the demand of the sampling signal. When the FPGA on-chip memory is not enough to store the sampling signal, the FPGA logic testing device is used to realize the data from the FPGA on-chip memory to the external memory. After migration, the data is processed in blocks and migrated to the FPGA on-chip memory one by one to realize the display of test signals.

Based on the above technical problems, an FPGA logic testing method specifically involved in the embodiments of the present application will be described below, referring to FIG. 2 , including:

S101. Determine the required resource storage amount required for testing the logic source code to be tested based on the bandwidth and sampling depth of the signal to be tested of the logic source code to be tested.

Specifically, the logic source code to be tested is mainly used for logic testing of the FPGA. In order to arrange the storage space, the required resource storage amount of the logic source code to be tested is first determined. The required resource storage amount is determined by the bandwidth of the signal to be tested and the sampling depth of the source code. OK, the specific calculation method is as follows:

X=K×S,

Among them, X is the required resource storage amount, K is the signal bandwidth to be tested of the logic source code to be tested, and S is the sampling depth, that is, the number of samples. According to the above calculation method, the required resource storage amount of the logic source code to be tested can be obtained.

S102. If the required resource storage amount is less than the remaining storage amount of the FPGA on-chip memory, determine the storage mode as on-chip storage, otherwise determine the storage mode as off-chip storage; wherein, the memory corresponding to the on-chip storage is the FPGA on-chip memory, and the on-chip storage The memory corresponding to the external storage is the external memory.

In this step, since there is a size inconsistency between the required resource storage and the remaining on-chip storage, the storage mode of the logic source code to be tested is determined under different circumstances, and the logic source code to be tested is stored according to the determined storage mode. On-chip storage refers to storing the sampled data generated in the testing process into the FPGA on-chip memory, and off-chip storage refers to storing the sampled data generated during the testing process in the FPGA on-chip memory.

S103 , test the logic source code to be tested based on the embedded logic analyzer core, and store the sampled data generated by the test in the corresponding memory according to the determined storage mode.

Before testing, the embedded logic analysis core should be set first. The specific setting method is as follows:

Let the trigger width be equal to the bandwidth K of the logic source code to be tested; the settings of the data depth include two cases, as follows:

表示

向下取整为2的倍数，其余内核保持不变。Among them, D is the data depth, S is the sampling depth, Y is the remaining resource storage on-chip, X is the required resource storage, K is the bandwidth of the logic source code to be tested,

express

Round down to a multiple of 2, leaving the rest of the kernel unchanged.

By setting the embedded logic analyzer core and setting the logic code signal to be tested as the core sampling signal, the signal to be tested can be tested. Due to the inconsistency between the required resource storage and the remaining on-chip storage, the storage mode of the logic source code to be tested is determined under different circumstances, and the logic source code to be tested is stored according to the determined storage mode.

Through the above-mentioned FPGA logic testing method, the function of automatically selecting the appropriate storage mode based on the required resource storage and remaining on-chip storage is realized. When the logic source code to be tested does not meet the storage capacity of the on-chip memory, the call The external memory is used for storage, and the idle resources of the external memory are fully utilized, thereby increasing the amount of storable data for FPGA logic testing and effectively increasing the sampling depth; when the source code of the logic to be tested can meet the storage capacity of the on-chip memory, select The FPGA on-chip memory stores sampled data to ensure data storage and reading efficiency. By judging the storage method according to the required amount of data to be stored, when the required amount of data to be stored is less than the remaining storage capacity of the FPGA chip, the storage method is directly stored in the FPGA on-chip memory without transferring to an external memory for storage, thereby shortening the test time.

Specifically, for the case that the logic source code to be tested can be stored in the FPGA on-chip memory, the logic source code to be tested is directly stored in the on-chip memory, that is, the selected storage mode is on-chip storage. That is, the above-mentioned storage amount of the resource in response to the demand is less than the remaining storage amount on the chip, and the test logic source code is stored in the FPGA on-chip memory.

When the on-chip memory of the FPGA does not meet the storage requirements, the selected storage mode is off-chip storage. At this time, in step S103, the sampled data generated by the test is stored in the corresponding memory according to the determined storage mode, including: storing the sampled data generated by the test. Write into the FPGA on-chip memory; when the data amount of the sampled data written into the FPGA on-chip memory satisfies the preset condition, store the sampled data in the FPGA on-chip memory into the external memory.

The preset condition may be that the amount of sampled data written into the FPGA on-chip memory reaches a preset value, and the preset value may be determined according to the remaining storage capacity of the FPGA on-chip memory obtained in step S102, and the preset value is not Exceeds the remaining storage capacity of the FPGA on-chip memory. That is, the sampled data generated by the test is first stored in the FPGA on-chip memory. When the data volume of the sampled data in the FPGA on-chip memory reaches the preset value, the sampled data in the FPGA on-chip memory will be sequentially transferred to the external memory. , until the test is completed.

Because the reading and writing process of the FPGA on-chip memory is fast and the data transfer path is short, the FPGA on-chip memory is used as a buffer area for sampled data. In the on-chip memory of the FPGA, the internal storage space of the FPGA is fully utilized, and then the sampled data in the on-chip memory of the FPGA is sequentially transferred to the external memory, which can improve the data storage efficiency compared with the method of directly storing it in the external memory. When the required storage data amount of the test data is less than the remaining storage amount of the FPGA on-chip memory, the storage time of the on-chip storage can be effectively shortened and the data processing process can be simplified.

In a possible implementation manner, the data amount of the sampled data written into the FPGA on-chip memory can be counted by the following method: record the number of times of writing the sampled data into the FPGA on-chip memory; if the number of writes is not less than The data transfer threshold is to determine that the amount of sampled data written into the FPGA on-chip memory meets the preset conditions, and the number of writes is cleared to zero, where the data transfer threshold is determined based on the required resource storage and the bandwidth of the signal to be tested. .

During specific implementation, before data sampling, set an appropriate data transfer threshold according to the required resource storage and the bandwidth of the signal to be tested, determine the conditions for data transfer into the external memory, and ensure that the FPGA on-chip memory is sufficient to cache the sampled data; and design and write Counter, the write counter counts according to the trigger clock, records the current number of writes to the RAM, and reads the value of the write counter to obtain the number of writes. After starting data sampling, write a sampled data into the FPGA on-chip memory, and the value of the write counter will increase by 1. When the count value of the write counter is greater than or equal to the data transfer threshold, the external write signal WR_ex will be valid, and the on-chip memory will be changed to The sampled data is written into the external memory, and the value of the write counter is cleared, and the above operations are repeated until the sampling ends.

其中，Y为FPGA片内存储器的剩余存储量，K为待测试信号带宽,n为大于1的数值。In a possible implementation, the data transfer threshold is

Among them, Y is the remaining storage capacity of the FPGA on-chip memory, K is the bandwidth of the signal to be tested, and n is a value greater than 1.

开始向外部存储器转移FPGA片内存储器内存储的数据。其中，

为本申请可实现的一个数据转移阈值示例，不作为本申请的具体限制。The data transfer threshold in this application is the condition for transferring data from the FPGA on-chip memory to the external memory. Taking n=2 as an example, when the on-chip data storage amount reaches

Start transferring data stored in FPGA on-chip memory to external memory. in,

This is an example of a data transfer threshold that can be implemented by this application, and is not a specific limitation of this application.

Optionally, referring to FIG. 3, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the sampling data in the FPGA on-chip memory is stored in the external memory, which specifically includes the following steps: The sampled data in the internal memory to be stored in the external memory are sequentially stored in the data write buffer. In order to match the data width, the data width of the sampled data in the data write buffer is modified to C, and the data width in the data write buffer is C The sampled data is stored in external memory.

In this step, in the process of storing the sampled data in the FPGA on-chip memory into the external memory, in order to match the data width of the FPGA on-chip memory and the data width of the external memory, in order to match the data width of the FPGA on-chip memory and the external memory The application provides a FPGA logic test device, the FPGA logic test device can be used for the exchange of control data between external memory and FPGA on-chip memory, and the test storage module in the FPGA logic test device can be used for data buffering. Width reorganization. Among them, the test memory module includes a data write buffer and a data read buffer. When the data of the FPGA on-chip memory is stored in the external memory, the data width of the FPGA on-chip memory and the external memory are inconsistent, and the data is stored in the test memory module. The data write buffer reorganizes the data so that the data width meets the data width to be stored in the FPGA on-chip memory or external memory. When the data width is the same, the data in the on-chip memory of the FPGA is directly migrated to the storage space of the external memory in sequence without data buffering; when the data width is inconsistent, data buffering is performed in the data write buffer area to reorganize the data, The data width of the data is organized as the data width of the external memory to realize data migration. The data write buffer area can be the storage space used by the on-chip memory of the FPGA as a data buffer.

The data write buffer and data read buffer provide data buffering between the FPGA on-chip memory and the external memory, no matter whether the data is written from the FPGA on-chip memory to the external memory or the external memory is written to the FPGA on-chip memory, when the two When the data width is inconsistent between them, it is necessary to buffer the data, reorganize the data, and change the data width of the signal to the data width of the target memory.

The data in the FPGA on-chip memory can be stored in the external memory, which improves the sampling depth during logic testing.

Optionally, after it is determined that the storage mode is off-chip storage, the storage space of the external memory can also be divided to facilitate data storage, which specifically includes the following steps:

X为需求资源存储量，R为FPGA片内存储器的数据宽度，L为FPGA片内存储器剩余的数据深度，R×L等于FPGA片内存储器剩余存储量Y；数据块的数量取决于FPGA片内存储器的存储量。当数据块的数量确定以后，将采样数据分块处理，为此，将FPGA片内存储器内的采样数据存入外部存储器的具体步骤包括：将FPGA片内存储器内的采样数据依次存入外部存储器的数据块中。According to the required resource storage amount, select a part of the space in the external memory, and divide the part of the space into N data blocks, among which,

X is the required resource storage amount, R is the data width of the FPGA on-chip memory, L is the remaining data depth of the FPGA on-chip memory, R×L is equal to the remaining storage amount Y of the FPGA on-chip memory; the number of data blocks depends on the FPGA on-chip memory The amount of storage in the memory. After the number of data blocks is determined, the sampled data is processed in blocks. To this end, the specific steps of storing the sampled data in the FPGA on-chip memory into the external memory include: sequentially storing the sampled data in the FPGA on-chip memory into the external memory in the data block.

In the specific implementation, according to the required resource storage, a part of the space is selected in the external memory, and the part of the space is divided into several data blocks, wherein the total storage capacity of the data blocks is equal to the storage capacity of the FPGA on-chip memory. Memory data is migrated sequentially into data blocks. And, the required resource storage amount is equal to the total data amount stored in the data block.

By using the external memory to store the logic signal to be tested, the idle space of the external memory is fully utilized, the storage capacity of the test signal is increased, the depth of the sampled signal is increased, and the efficiency of the logic test is accelerated.

Optionally, after the embedded logic analyzer is tested, the FPGA logic testing method of the embodiment of the present application further includes the following steps:

The data is stored in the external memory in blocks. After the test is completed, in order to transfer the data for display through the external display, first write the data blocks of the sampled data stored in the external memory into the FPGA on-chip memory in sequence; The sequence of out or FIFO is written into the FPGA on-chip memory from the external memory. When the first data block is stored in the FPGA on-chip memory, the second data block will then be written into the FPGA on-chip memory to refresh the FPGA chip. For the data in the internal memory, the first data block is the first data block stored in the external memory from the data buffer of the FPGA on-chip memory. After the second data block is written into the FPGA on-chip memory, the data stored in the FPGA on-chip memory will be refreshed to the data of the second data block, and the data blocks will be stored into the FPGA on-chip memory one by one. After the data block is read, the next data block is written into the FPGA on-chip memory to refresh the FPGA on-chip memory until the data block is read out, that is, when the last data block is written into the FPGA on-chip memory.

Specifically, when the storage space of the FPGA on-chip memory does not meet the test requirements, after using the external memory for storage, in order to display and observe the sampled signal, it is necessary to write the sampled data into the FPGA on-chip memory, and connect it to the display through the JTAG interface. display, so the external memory also needs to be written to the FPGA on-chip memory.

At this time, the data of the external memory is written into the FPGA on-chip memory in sequence according to the data blocks divided when writing data from the FPGA on-chip memory. When the first data block is completely written into the FPGA on-chip memory, the second data block It will then write to the FPGA on-chip memory to refresh the data in the FPGA on-chip memory.

时，由于需求资源存储量与片内存储量一致的情况，片内存储器只存储R×L大小的数据量，为一个数据块。同时，数据块会被依次一个个的写入FPGA片内存储器，采用这种方法，使采样信号不局限于FPGA片内存储器和外部存储器的数据宽度的要求，扩大了适用的外部存储器的范围。When the sampled signal is stored in the external memory, in order to display the sampled signal, after the sampled signal is stored in the external memory, the sampled signal will still be written to the FPGA on-chip memory in sequence according to the data block format when writing to the external memory. However, due to the size of the storable amount of FPGA on-chip memory, when

When the required resource storage amount is consistent with the on-chip storage amount, the on-chip memory only stores the data amount of R×L size, which is one data block. At the same time, the data blocks will be written into the FPGA on-chip memory one by one. Using this method, the sampling signal is not limited to the data width requirements of the FPGA on-chip memory and the external memory, and the scope of the applicable external memory is expanded.

Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the data stored in the external memory still needs to be written into the FPGA on-chip memory for storage. The specific steps of sequentially writing the data blocks in the memory into the FPGA on-chip memory include: sequentially storing the data blocks in the external memory into the data read buffer, modifying the data width of the data blocks in the data read buffer to R, The data block whose data width is R in the data read buffer is stored in the FPGA on-chip memory.

Specifically, when the external memory is equal to the data width of the FPGA on-chip memory, there is no need to correct the data width from the external memory to the FPGA on-chip memory, and the external memory is directly written into the FPGA on-chip memory. However, when the data width is inconsistent, the data read buffer of the data cache unit in the FPGA logic test device performs data buffering, reorganizes the data, converts the data width of the data to the data width of the FPGA on-chip memory, and then converts the external memory data to the data width. Blocks are written to the FPGA on-chip memory sequentially.

When the external memory stores the sampled signal, the stored data in the external memory also needs to be written into the FPGA on-chip memory before it can be sent to the display for display. In the specific signal display process, first the stored data of the external memory is written into the on-chip memory in blocks, and after the first data block is written into the on-chip memory, the signal oscilloscope is performed through the external display connected by JTAG; The data of one data block is gradually read out, and the second data block is gradually written into the FPGA on-chip memory to refresh the data in the FPGA on-chip memory. Until the data is displayed by the external display. By buffering in the test storage module, the data width can be adapted through reorganization, which avoids the inconsistent data width and expands the applicable scenarios of the test method.

In a possible implementation, the external memory is an FPGA configuration chip, where the FPGA configuration chip is a chip used to store the FPGA program when the FPGA is powered off, and when the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program to In the FPGA, the FPGA configuration chip is in an idle state at this time.

Specifically, the external memory may be an FPGA configuration chip, and the FPGA configuration chip is a chip used to store the FPGA program when the FPGA is powered off. When the FPGA is powered off, the program when powered on will not be stored, and the FPGA configuration chip is used to store the program that will be lost when the FPGA is powered off. When the FPGA is powered on again, the FPGA configuration chip will be reconfigured to the FPGA hardware in a short time. After the configuration is completed, the off-chip configuration chip will be in an idle state. When the embedded logic analyzer is used to test the logic source code to be tested, It can be used to store signals to be tested that cannot be stored by on-chip memory resources.

Since the FPGA on-chip memory is volatile, the FPGA configuration chip will be used to store the program in the FPGA on-chip memory after the FPGA is powered off. Therefore, the sampling depth of the test can be effectively improved, and the idle resources in the FPGA can be fully utilized without adding external memory, which reduces the equipment cost.

An FPGA logic testing device 30 provided by the present invention, referring to FIG. 4 , includes:

A storage amount determination module 301, configured to determine the required resource storage amount required for testing the logic source code to be tested based on the bandwidth of the signal to be tested and the sampling depth of the logic source code to be tested;

The storage mode determination module 302 is configured to determine that the storage mode is on-chip storage if the required resource storage amount is less than the remaining storage capacity of the FPGA on-chip memory, otherwise, determine that the storage mode is off-chip storage; wherein, the corresponding on-chip storage The memory is the FPGA on-chip memory, and the memory corresponding to the off-chip memory is the external memory;

The test storage module 303 is configured to test the logic source code to be tested based on the embedded logic analyzer core, and store the sampled data generated by the test in the corresponding memory according to the determined storage mode.

Optionally, when the storage mode is off-chip storage, the test storage module 303 is specifically used for:

Write the sampled data generated by the test into the FPGA on-chip memory;

When the data amount of the sampled data written into the FPGA on-chip memory satisfies a preset condition, the sampled data in the FPGA on-chip memory is stored in the external memory.

Optionally, the device also includes a counting module:

Record the number of times of writing sampling data into the FPGA on-chip memory;

If the number of writes is not less than the data transfer threshold, it is determined that the data amount of the sampled data written in the FPGA on-chip memory meets a preset condition, and the number of writes is cleared, wherein the data transfer threshold is It is determined based on the required resource storage amount and the bandwidth of the signal to be tested.

其中，Y为所述FPGA片内存储器的剩余存储量，K为待测试信号带宽，n为大于1的数值。Optionally, in the counting module, the data transfer threshold is

Wherein, Y is the remaining storage capacity of the on-chip memory of the FPGA, K is the bandwidth of the signal to be tested, and n is a value greater than 1.

Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the test storage module 303 is specifically used for:

The sampled data to be stored in the external memory in the FPGA on-chip memory is sequentially stored in the data write buffer, the data width of the sampled data in the data write buffer is modified to R, and the data width in the data write buffer Store the sampled data for R into the external memory.

Optionally, the device further includes a space selection module, which is specifically used for:

X为所述需求资源存储量，R为所述FPGA片内存储器的数据宽度，L为所述FPGA片内存储器剩余的数据深度；According to the required resource storage amount, a part of the space is selected in the external memory, and the part of the space is divided into N data blocks, wherein,

X is the required resource storage amount, R is the data width of the FPGA on-chip memory, and L is the remaining data depth of the FPGA on-chip memory;

The test storage module 303 is also specifically used for:

The sampling data in the on-chip memory of the FPGA is sequentially stored in the data blocks of the external memory.

Optionally, after the embedded logic analyzer is tested, the device further includes a data migration module, which is specifically used for:

The data blocks storing the sampled data in the external memory are sequentially written into the FPGA on-chip memory;

After each data block is read out, the next data block is written into the on-chip memory to refresh the on-chip memory until the data block is read out.

Optionally, when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the test storage module 303 is also used for:

The data blocks in the external memory are stored in the data read buffer in turn, the data width of the data blocks in the data read buffer is modified to C, and the data blocks with a data width of C in the data read buffer are stored in the data read buffer. FPGA on-chip memory.

Optionally, the external memory specifically used by the test module 303 is an FPGA configuration chip, wherein the FPGA configuration chip is a chip used to store the FPGA program when the FPGA is powered off. When the FPGA is powered on, the FPGA configuration chip will store the FPGA program. The stored FPGA program is sent to the FPGA, and the FPGA configures the chip to be in an idle state at this time.

The FPGA logic testing apparatus 30 provided in the embodiment of the present application adopts the same inventive concept as the above-mentioned FPGA logic testing method, and can achieve the same beneficial effects, which will not be repeated here.

Based on the same inventive concept as the above-mentioned FPGA logic testing method, an embodiment of the present application further provides an electronic device 40 , as shown in FIG. 5 , the electronic device 40 may include a processor 401 and a memory 402 .

The processor 401 may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array) , FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components, which can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the methods disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

As a non-volatile computer-readable storage medium, the memory 402 can be used to store non-volatile software programs, non-volatile computer-executable programs and modules. The memory may include at least one type of storage medium, for example, may include flash memory, hard disk, multimedia card, card-type memory, random access memory (Random Access Memory, RAM), static random access memory (Static Random Access Memory, SRAM), Programmable Read Only Memory (PROM), Read Only Memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Magnetic Memory, Disk, CD and so on. Memory is, but is not limited to, any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory 402 in this embodiment of the present application may also be a circuit or any other device capable of implementing a storage function, for storing program instructions and/or data.

Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by program instructions related to hardware, the aforementioned program can be stored in a computer-readable storage medium, and when the program is executed, execute Including the steps of the above-mentioned method embodiments; the above-mentioned computer storage medium can be any available medium or data storage device that can be accessed by a computer, including but not limited to: mobile storage device, random access memory (RAM, Random Access Memory), magnetic memory (eg floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical memory (eg CD, DVD, BD, HVD, etc.), and semiconductor memory (eg ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH) , Solid State Drive (SSD)) and other media that can store program codes.

Alternatively, if the above-mentioned integrated units of the present application are implemented in the form of software function modules and sold or used as independent products, they may also be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence or in the parts that make contributions to the prior art. The computer software products are stored in a storage medium and include several instructions for A computer device (which may be a personal computer, a server, or a network device, etc.) is caused to execute all or part of the methods described in the various embodiments of the present application. The aforementioned storage media include: removable storage devices, random access memory (RAM, Random Access Memory), magnetic storage (such as floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical storage (such as CD, DVD, BD, etc.) , HVD, etc.), and semiconductor memories (eg, ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state disk (SSD), etc.) various media that can store program codes.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. The scope of the invention should be included in the scope of the claims and description of the present invention.

Claims (5)

1. An FPGA logic test method is applied to an FPGA which does not additionally increase an external memory and only utilizes idle resources, and is characterized by comprising the following steps:

determining the required resource storage amount required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested;

if the required resource storage amount is less than the residual storage amount of the FPGA on-chip memory, determining that the storage mode is on-chip storage, otherwise, determining that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage; the external memory is an FPGA configuration chip, wherein the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off, and after the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program into the FPGA, and is in an idle state at the moment;

when the storage mode is off-chip storage, the step of storing the sampling data generated by the test into the corresponding memory according to the determined storage mode comprises the following steps:

writing sampling data generated by testing into the FPGA on-chip memory;

when the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, storing the sampling data in the FPGA on-chip memory into the external memory;

when the data width C of the external memory is not equal to the data width R of the FPGA on-chip memory, the step of storing the sampling data in the FPGA on-chip memory into the external memory comprises the following steps:

sequentially storing the sampling data to be stored into the external memory in the FPGA on-chip memory into a data writing buffer area, modifying the data width of the sampling data in the data writing buffer area to R, and storing the sampling data with the data width of R in the data writing buffer area into the external memory;

testing the logic source code to be tested based on the embedded logic analyzer kernel, and storing sampling data generated by testing into a corresponding memory according to a determined storage mode;

the method further comprises the following steps:

recording the writing times of writing sampling data into the FPGA on-chip memory;

if the writing times are not less than a data transfer threshold value, determining that the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, and clearing the writing times, wherein the data transfer threshold value is determined based on the required resource storage amount and the bandwidth of the signal to be tested; the data transferShift the threshold value to

Y is the residual memory space of the FPGA on-chip memory, K is the bandwidth of the signal to be tested, and n is a numerical value larger than 1.

2. The method of claim 1, further comprising:

selecting a partial space in the external memory according to the demand resource storage amount, and dividing the partial space into N data blocks,

x is the storage amount of the required resources, R is the data width of the FPGA on-chip memory, and L is the residual data depth of the FPGA on-chip memory;

the storing the sampling data in the FPGA on-chip memory into the external memory comprises:

and sequentially storing the sampling data in the FPGA on-chip memory into the data block of the external memory.

3. The method of claim 1, further comprising, after the embedded logic analyzer test is completed:

writing the data blocks storing the sampling data in the external memory into the FPGA on-chip memory in sequence;

and after the reading of each data block is finished, writing the next data block into the on-chip memory to realize the refreshing of the on-chip memory until the reading of the data block is finished.

4. The method according to claim 3, wherein when the data width C of the external memory and the data width R of the FPGA on-chip memory are not equal, the writing the data blocks stored in the external memory into the FPGA on-chip memory in sequence comprises:

and sequentially storing the data blocks in the external memory into a data reading buffer area, modifying the data width of the data blocks in the data reading buffer area into C, and storing the data blocks with the data width of C in the data reading buffer area into the FPGA chip memory.

5. An FPGA logic test device, comprising:

the memory space determining module is used for determining the required resource memory space required by testing the logic source code to be tested based on the bandwidth and the sampling depth of the signal to be tested of the logic source code to be tested;

the storage mode determining module is used for determining that the storage mode is on-chip storage if the storage capacity of the required resources is less than the residual storage capacity of the FPGA on-chip storage, or determining that the storage mode is off-chip storage; the storage corresponding to the on-chip storage is an FPGA on-chip storage, and the storage corresponding to the off-chip storage is an external storage; the external memory is an FPGA configuration chip, wherein the FPGA configuration chip is a chip for storing an FPGA program when the FPGA is powered off, and after the FPGA is powered on, the FPGA configuration chip sends the stored FPGA program to the FPGA, and the FPGA configuration chip is in an idle state;

when the storage mode is off-chip storage, the step of storing the sampling data generated by the test into the corresponding memory according to the determined storage mode comprises the following steps:

writing sampling data generated by testing into the FPGA on-chip memory;

when the data volume of the sampled data written into the FPGA on-chip memory meets a preset condition, storing the sampled data in the FPGA on-chip memory into the external memory;

when the data width C of the external memory is not equal to the data width R of the FPGA on-chip memory, the step of storing the sampling data in the FPGA on-chip memory into the external memory comprises the following steps:

sequentially storing the sampling data to be stored into the external memory in the FPGA on-chip memory into a data writing buffer area, modifying the data width of the sampling data in the data writing buffer area to R, and storing the sampling data with the data width of R in the data writing buffer area into the external memory;

the test storage module is used for testing the logic source code to be tested based on the embedded logic analyzer kernel and storing the sampling data generated by the test into the corresponding memory according to the determined storage mode;

the apparatus is further configured to:

recording the writing times of writing sampling data into the FPGA on-chip memory;

if the writing times are not less than a data transfer threshold value, determining that the data volume of the sampling data written into the FPGA on-chip memory meets a preset condition, and clearing the writing times, wherein the data transfer threshold value is determined based on the required resource storage amount and the bandwidth of the signal to be tested; the data transfer threshold is

And Y is the residual memory space of the FPGA on-chip memory, K is the bandwidth of a signal to be tested, and n is a numerical value larger than 1.

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