CN1862830A - Power semiconductor device with L shaped source - Google Patents
Power semiconductor device with L shaped source Download PDFInfo
- Publication number
- CN1862830A CN1862830A CN 200510071202 CN200510071202A CN1862830A CN 1862830 A CN1862830 A CN 1862830A CN 200510071202 CN200510071202 CN 200510071202 CN 200510071202 A CN200510071202 A CN 200510071202A CN 1862830 A CN1862830 A CN 1862830A
- Authority
- CN
- China
- Prior art keywords
- source area
- shaped source
- tagma
- power semiconductor
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
本发明为一种具L形源极区的功率半导体器件，其结构包含：一衬底；一阱区，形成于该衬底内；一本体区，形成该阱区之上；一沟槽栅极，形成于该阱区的两侧，其中该沟槽栅极的侧壁及底面更具有一栅极氧化层；一L形源极区，其具有一平顶区及一直侧区，分别形成于该本体区的部分顶面及两侧；一电介质绝缘层，形成于该沟槽栅极区及部分该L形源极区之上，并定义有一接触窗；以及一金属层，形成于该电介质绝缘层、该本体区及该L形源极区之上，并经由该接触窗与该L形源极区连接，以形成该具L形源极区的埋入式沟槽栅极的功率半导体器件。
The present invention is a power semiconductor device with an L-shaped source region, and its structure includes: a substrate; a well region formed in the substrate; a body region formed on the well region; a trench gate Pole, formed on both sides of the well region, wherein the side wall and bottom surface of the trench gate further have a gate oxide layer; an L-shaped source region, which has a flat top region and a straight side region, respectively formed in Part of the top surface and both sides of the body region; a dielectric insulating layer formed on the trench gate region and part of the L-shaped source region, and defining a contact window; and a metal layer formed on the dielectric On the insulating layer, the body region and the L-shaped source region, and connected to the L-shaped source region through the contact window, to form the power semiconductor of the buried trench gate with the L-shaped source region device.
Description
Technical field
The present invention relates to a kind of power semiconductor device structure, refer to the power semiconductor device structure of the L shaped source area of a kind of tool especially.
Background technology
In recent years, power semiconductor, mos field effect transistor (metaloxide semiconductor field effect transistor for example, MOSFET), insulated gate isolation-type bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), junction field effect transistor (Junction FieldEffect Transistor, JFET) or rectifier diode (Rectifier) etc., on its operating characteristics and manufacturing process, all obtained extremely good progress.Yet in order further to improve Devices Characteristics and to reduce manufacturing cost, a kind of main trend wherein promptly is to utilize so-called trench-gate technology (trench-gatedtechnology) to finish.Yet when utilizing this trench-gate technology, unit born of the same parents' spacing (cellpitch) can be dwindled in this device, and the gully density of device (device channel density) can increase significantly.The power loss of like this one low conducting state can be by forming low on-resistance (on-resistance) or hanging down forward pressure drop (forward drop voltage) and reach.
Yet unfortunately in case the gully density that increases power semiconductor just can cause usually this device the safety operation scope (safe operation area, SOA) and durability (Ruggedness) reduce.In order to solve this negative effect, must design with a point-device manufacturing process management and control at source area (source) (as the N+ zone of N type raceway groove) and this tagma (body) (P+ zone of N type raceway groove), and carry out suitable injecting program.This tagma of the N+ type source area of perfect condition and P+ type is in conjunction with causing this tagma/well region of P+ type (as the p type island region of N type raceway groove) to obtain a minimum resistance, and (bipolar junction transistors BJT) can obtain a low-down common emitter current gain (common emitter current gain) by parasitism (parasitic) bipolar junction transistor that a N+ type source area, this tagma of P+ type/P type well region and N type epitaxial loayer are constituted.Yet in order to obtain above-mentioned characteristic, this N+ type source area must be entirely that this tagma of P+ type coats and the threshold voltage (threshold voltage) that do not increase device, and this this tagma of P+ type also need have enough degree of depth under the prerequisite of the puncture voltage that does not reduce device (breakdown voltage).
See also Fig. 1, it discloses a known flush type trench-gate power semiconductor device structure.As shown in the figure, the structure of this power semiconductor comprises N-type epitaxial substrate 11, P type well region 12, this tagma 13 of P+ type, trench-gate 14, grid oxic horizon 15, N+ type source area 16, dielectric insulation layer 17 and metal level 18.Wherein, P type well region 12 is formed in the N-type epitaxial substrate 11, and this tagma 13 of P+ type is formed on the P type well region 12.In addition, trench-gate 14 is formed at the both sides of P type well region 12, and wherein the sidewall of this trench-gate 14 and bottom surface also form this grid oxic horizon 15.In addition, N+ type source area 16 is formed at the both sides in this tagma 13 of P+ type.Dielectric insulation layer 17 is formed on trench-gate 14 and the part N+ type source area 16, and definition has a contact hole.Metal level 18 is formed on dielectric insulation layer 17, this tagma 13 of P+ type and the N+ type source area 16, and is connected with this N+ type source area 16 via this contact hole, to form this power semiconductor.Wherein, this tagma 13 of P+ type all has the darker degree of depth than N+ type source area 16, and this tagma 13 of P+ type also has enough width to coat N+ type source area 16 as much as possible.
Similarly Fig. 2 and Fig. 3 also disclose other known power semiconductor device structure.Device architecture shown in Figure 2 is similar haply to device architecture shown in Figure 1, has only N+ type source area 16 to be formed on this tagma 13 of P+ type and on the part P type well region 12.In addition, device architecture shown in Figure 3 is also similar haply to device architecture shown in Figure 1, has only N+ type source area 16 to be formed on this tagma 13 of part P+ type and the part P type well region 12.In Fig. 2 and device architecture shown in Figure 3, this tagma 13 of P+ type also has the darker degree of depth than N+ source area 16, and this tagma 13 of P+ type also has enough width to coat N+ type source area 16 as much as possible.Above-mentioned three kinds of different N+ type source areas 16 and these tagma 13 configurations of P+ type all can be existing trench-gate technology (trench-gated technology) make.Yet these known technologies but have two shortcomings.At first, because this tagma 13 of P+ type gets deeply than N+ type source area 16, this channel region is exposed to this tagma 13 of P+ type, and then the alloy in P+ zone will enter this raceway groove easily and cause threshold voltage (threshold voltage) higher and that can't control.On the other hand, depletion region (depletionregion) distribution in the P+ zone will be limited in dark this tagma 13 of P+ type of injecting.Therefore when the degree of depth in this tagma 13 of P+ type increases, the puncture voltage of device (breakdown voltage) will be limited, even be reduced.
In view of known power semiconductor, its puncture voltage (breakdown voltage) is can be because of the degree of depth in this tagma limited even reduce, and its threshold voltage (threshold voltage) also can influence raceway groove because of the alloy of P+ type regional structure, cause integral device electrically thereby be affected.Therefore, how under the prerequisite that does not increase equipment cost, carry out the change and the adjustment of device architecture,, just become the problem of solution that those skilled in the art press for to improve the shortcoming of known technology.
Summary of the invention
Main purpose of the present invention is for providing the flush type trench-gate power semiconductor device structure of the L shaped source area of a kind of tool.Importing by a L shaped source configuration, can avoid device electric breakdown strength (breakdownvoltage) limited even reduce because of the degree of depth in this tagma, and the threshold voltage (thresholdvoltage) that can avoid device causes electrically being affected of integral device because of the alloy of P+ type regional structure influences raceway groove.
Another object of the present invention is for providing the flush type trench-gate power semiconductor device structure of the L shaped source area of a kind of tool.This structure can make that the spacing (cell pitch) of unit born of the same parents in the device is effectively dwindled, gully density (device channel density) increases, and does not influence that it is electrical.
For reaching above-mentioned purpose, of the present invention one implements the sample attitude for the power semiconductor of the L shaped source area of a kind of tool is provided than broad sense, and its structure comprises a substrate; One well region is formed in this substrate; One this tagma forms on this well region; One trench-gate is formed at the both sides of this well region, and wherein the sidewall of this trench-gate and bottom surface also have a grid oxic horizon; One L shaped source area, it has a flat-top district and reaches lateral areas always, is formed at the part end face and the both sides in this this tagma respectively; One dielectric insulation layer be formed on this trench-gate and this L shaped source area of part, and definition has a contact hole; And a metal level, be formed on this dielectric insulation layer, this this tagma and this L shaped source area, and be connected, with the power semiconductor of the flush type trench-gate that forms the L shaped source area of this tool via the L shaped source area of this contact hole and this.
According to conception of the present invention, wherein this power semiconductor can be a mos field effect transistor (metal oxide semiconductor field effect transistor, MOSFET).
According to conception of the present invention, wherein this substrate can be N-type epitaxial substrate.
According to conception of the present invention, wherein this grid oxic horizon can be a thermal oxide layer.
According to conception of the present invention, wherein this trench-gate can be made of a polysilicon layer.
According to conception of the present invention, wherein this well region can be a P type well region.
According to conception of the present invention, wherein this this tagma can be this tagma of P+ type.
According to conception of the present invention, wherein this L shaped source area can be made of a N+ type implanted layer.
According to conception of the present invention, wherein this dielectric insulation layer can be a deposited oxide layer.
According to conception of the present invention, wherein the degree of depth in this front district of this L shaped source area is more than or equal to the degree of depth in this this tagma.
For reaching above-mentioned purpose, of the present invention another implemented the sample attitude for the power semiconductor of the L shaped source area of a kind of tool is provided than broad sense, and it comprises: a drain region; One this tagma forms on this drain region; One trench-gate is formed at the both sides in this this tagma, and wherein the sidewall of this trench-gate and bottom surface also have a grid oxic horizon; One L shaped source area, it has a flat-top district and reaches lateral areas always, is formed at the part end face and the both sides in this this tagma respectively; One dielectric insulation layer is formed on this trench-gate; And a metal level, be formed on this dielectric insulation layer, this this tagma and this L shaped source area, and be connected, to form the power semiconductor of the L shaped source area of this tool with this L shaped source area.
According to conception of the present invention, wherein this dielectric insulation layer can be a BPSG deposited oxide layer.
According to conception of the present invention, wherein this power semiconductor can be a metal oxide semiconductcor field effect transistor.
According to conception of the present invention, wherein this drain region can be made of a N-type epitaxial loayer.
According to conception of the present invention, wherein this grid oxic horizon can be a thermal oxide layer.
According to conception of the present invention, wherein this trench-gate can be made of a polysilicon layer.
According to conception of the present invention, wherein this this tagma can be made of a P+ type implanted layer and a P type well region.
According to conception of the present invention, wherein the degree of depth in this front district of this L shaped source area is more than or equal to the degree of depth of this P+ type implanted layer in this this tagma.
According to conception of the present invention, wherein this L shaped source area can be made of a N+ type implanted layer.
In sum, the invention provides the flush type trench-gate power semiconductor device structure of the L shaped source area of a kind of tool, (metal oxidesemiconductor field effect transistor MOSFET) waits on the device for example to can be applicable to mos field effect transistor.By the importing of flush type trench gate structure and L shaped source area structure, the spacing (cell pitch) of unit born of the same parents in the semiconductor device is effectively dwindled, gully density (device channel density) obviously increases, and it is electrical not influence device.
Description of drawings
Fig. 1 discloses the flush type trench-gate and the source configuration schematic diagram of known power semiconductor.
Fig. 2 discloses the flush type trench-gate and the source configuration schematic diagram of another known power semiconductor.
Fig. 3 discloses the flush type trench-gate and the source configuration schematic diagram of a known power semiconductor again.
Fig. 4 discloses the flush type trench-gate power semiconductor device structural representation of the L shaped source area of tool of preferred embodiment of the present invention.
Fig. 5 A-5C discloses the processing procedure structural representation of device architecture shown in Figure 4.
Fig. 6 discloses the flush type trench-gate power semiconductor device structural representation of the L shaped source area of tool of another preferred embodiment.
Wherein, description of reference numerals is as follows:
11:N-type epitaxial substrate 12:P type well region
This tagma 14 of 13:P+ type: trench-gate
15: grid oxic horizon 16:N+ type source area
17: dielectric insulation layer 18: metal level
21: substrate 22: well region
23: this tagma 24: trench-gate
25: grid oxic horizon 26:L shape source area
261: flat-top district 262: the front district
27: dielectric insulation layer 28: contact hole
29: metal level 3: groove structure
41: drain region 411:N+ type substrate
412:N-type epitaxial loayer 42: this tagma
421:P type well region 422:P+ type implanted layer
43: trench-gate 44: grid oxic horizon
45:L shape source area 451: flat-top district
452: front district 46: dielectric insulation layer
47: metal level
Embodiment
Some exemplary embodiments that embody feature of the present invention and advantage will be described in detail in the explanation of back segment.Be understood that the present invention can have various variations on different aspects, its neither departing from the scope of the present invention, and explanation wherein and the accompanying drawing usefulness that should explain in itself, but not in order to restriction the present invention.
See also Fig. 4, it discloses the flush type trench-gate power semiconductor device structure of the L shaped source area of tool of a preferred embodiment of the present invention.As shown in the figure, the flush type trench-gate power semiconductor device structure of the L shaped source area of tool of the present invention mainly comprises substrate 21, well region 22, this tagma 23, trench-gate 24, grid oxic horizon 25, L shaped source area 26, dielectric insulation layer 27 and metal level 29.Wherein, well region 22 is formed in the substrate 21, and this tagma 23 forms on the well region 22.Trench-gate 24 is formed at the both sides of well region 22, and wherein the sidewall of trench-gate 24 and bottom surface also have this grid oxic horizon 25.L shaped source area 26 has a flat-top district 261 and reaches lateral areas 262 always, and it is formed at the part end face and the both sides in this tagma 23 respectively.Dielectric insulation layer 27 is formed on trench-gate 24 and the partial L shape source area 26, and definition has a contact hole 28.Metal level 29 is formed on dielectric insulation layer 27, this tagma 23 and the L shaped source area 26, and is connected with the flat-top district 261 of this L shaped source area 26 via this contact hole 28, to form the flush type trench-gate power semiconductor device of the L shaped source area of this tool.
Conception of the present invention can be applied to a mos field effect transistor, and (metaloxide semiconductor field effect transistor is in structure MOSFET).When practical application, this substrate 21 can be N-type epitaxial substrate, for the usefulness of doing the drain region, the flush type trench gate structure that the trench-gate 24 that is positioned at groove structure then can be polysilicon and constituted, the grid oxic horizon 25 that trench-gate 24 bottom surfaces and sidewall coat then can be a thermal oxide layer, can make by the thermal oxidation processing procedure.In addition, this well region 22 can be a P type well region, and this tagma 23 then can be this tagma of P+ type.Then can be constituted as for these L shaped source area 26 structures by a N+ type implanted layer.
Yet the flush type trench-gate power semiconductor device structure of the disclosed L shaped source area of tool is not limited to particular process.Flush type trench-gate power semiconductor device structure with the L shaped source area of tool in the previous embodiment is an example, its processing procedure can be earlier by substrate 21 beginnings that a tool N-type epitaxial loayer is provided, then carry out the injection of P type, the injection of P+ type and N+ type respectively and inject, distribute with the different injection regions such as P type well region 22, this tagma 23 of P+ type and N+ type source area 26 that form as shown in Fig. 5 A.Subsequently, utilize mask lithography etch process definition groove structure 3, shown in Fig. 5 B.And form a thermal oxide layer 25 with a thermal oxidation processing procedure in these groove structure 3 walls, insert polysilicon layer again in this groove structure 3, and carry out an etch-back processing procedure, get final product trench-gate 24 structures shown in Fig. 5 C.At last, deposit a BPSG oxide layer, and define required dielectric insulation layer 27 structures.Then, form contact hole 28 by the mask lithography etch process, and utilize deposition manufacture process to form required metal level 29, and make it pass through contact hole 28 and contact with N+ type source area 26, can obtain the flush type trench-gate power semiconductor device structure of the L shaped source area of tool as shown in Figure 4.
Certainly the flush type trench-gate power semiconductor device structure of the L shaped source area of tool of the present invention is not limited to above-mentioned method for making.The present invention also can form required structure by the variation of other processing procedure, characteristic wherein of the present invention is that the degree of depth in this front district 262 of this L shaped source area 26 is more than or equal to the degree of depth in this this tagma 23, as shown in Figure 4, so disclosed power semiconductor device structure, its puncture voltage (breakdown voltage) can be as not limited or reduce because of the degree of depth in this tagma in the known technology, and its threshold voltage (threshold voltage) also can not influence raceway groove because of the alloy of P+ type regional structure, cause integral device electrically thereby be affected.So disclosed structure can make that the spacing (cell pitch) of unit born of the same parents in the semiconductor device is effectively dwindled, gully density (device channel density) obviously increases, it is electrical and do not influence.
See also Fig. 6, it discloses the present invention, and another implements the flush type trench-gate power semiconductor device structure of the L shaped source area of tool of aspect, and its structure comprises drain region 41, this tagma 42, trench-gate 43, grid oxic horizon 44, L shaped source area 45, dielectric insulation layer 46 and metal level 47.Wherein, this tagma 42 is formed on the drain region 41.Trench-gate 43 is formed at the both sides in this tagma 42, and wherein the sidewall of trench-gate 43 and bottom surface also have a grid oxic horizon 44.In addition, L shaped source area 45 has a flat-top district 451 and reaches lateral areas 452 always, is formed at the part end face and the both sides in this tagma 42 respectively.Dielectric insulation layer 46 is formed on this trench-gate 43, and metal level 47 is formed on this dielectric insulation layer 46, this tagma 42 and the L shaped source area 45, with the power semiconductor of the flush type grid that forms the L shaped source area of this tool.
When practical application, this dielectric insulation layer 46 can be a BPSG deposited oxide layer, and this L shaped source area 45 can be made of a N+ type implanted layer.This drain region 41 can be made of a N-type epitaxial loayer 412 and a N+ type substrate 411 again, and this this tagma 42 can be a P+ type implanted layer 422 and a P type well region 421 constitutes.Similarly, in embodiments of the present invention, the degree of depth in this front district 452 of this L shaped source area 45 is more than or equal to the degree of depth of this P+ type implanted layer 422 in this this tagma 42.Whereby, unit born of the same parents' spacing in this semiconductor device (cell pitch) can effectively be dwindled, gully density (devicechannel density) also can obviously increase, and it is electrical and do not influence.
In sum, the invention provides the flush type trench-gate power semiconductor device structure of the L shaped source area of a kind of tool, (metal oxidesemiconductor field effect transistor MOSFET) waits on the device for example to can be applicable to mos field effect transistor.By the importing of flush type trench gate structure and L shaped source area structure, the spacing (cell pitch) of unit born of the same parents in the semiconductor device is effectively dwindled, gully density (device channel density) obviously increases, and it is electrical not influence device.
The present invention is described in detail by the foregoing description, and can carry out various modifications by those of ordinary skill in the art, but the scope that its neither disengaging claim is protected.
Claims (9)
1. the power semiconductor of the L shaped source area of tool, it comprises:
One substrate;
One well region is formed in this substrate;
One this tagma is formed on this well region;
One trench-gate is formed at the both sides of this well region, and wherein the sidewall of this trench-gate and bottom surface also have a grid oxic horizon;
One L shaped source area, it has a flat-top district and reaches lateral areas always, is formed at the part end face and the both sides in this this tagma respectively;
One dielectric insulation layer be formed on this trench-gate and this L shaped source area of part, and definition has a contact hole; And
One metal level is formed on this dielectric insulation layer, this this tagma and this L shaped source area, and is connected via the L shaped source area of this contact hole and this, to form the power semiconductor of the L shaped source area of this tool.
2. the power semiconductor of the L shaped source area of tool as claimed in claim 1, it is characterized in that this power semiconductor is that a mos field effect transistor, substrate are that N-type epitaxial substrate, this grid oxic horizon are a thermal oxide layer, and this trench-gate is made of a polysilicon layer.
3. the power semiconductor of the L shaped source area of tool as claimed in claim 1, it is characterized in that this well region be a P type well region, this this tagma by this tagma of P+ type, this L shaped source area by a N+ type implanted layer constituted, this dielectric insulation layer is a deposited oxide layer, and the degree of depth in this front district of this L shaped source area is more than or equal to the degree of depth in this this tagma.
4. the power semiconductor of the L shaped source area of tool, it comprises:
One drain region;
One this tagma is formed on this drain region;
One trench-gate is formed at the both sides in this this tagma, and wherein the sidewall of this trench-gate and bottom surface also have a grid oxic horizon;
One L shaped source area, it has a flat-top district and reaches lateral areas always, is formed at the part end face and the both sides in this this tagma respectively;
One dielectric insulation layer is formed on this trench-gate; And
One metal level is formed on this dielectric insulation layer, this this tagma and this L shaped source area, and is connected with this L shaped source area, to form the power semiconductor of the L shaped source area of this tool.
5. the power semiconductor of the L shaped source area of tool as claimed in claim 4, it is characterized in that this dielectric insulation layer is a BPSG deposited oxide layer, and this power semiconductor is a mos field effect transistor, and this drain region is made of a N-type epitaxial loayer.
6. the power semiconductor of the L shaped source area of tool as claimed in claim 4 it is characterized in that this grid oxic horizon is a thermal oxide layer, and this trench-gate is made of a polysilicon layer.
7. the power semiconductor of the L shaped source area of tool as claimed in claim 4 is characterized in that this this tagma is made of a P+ type implanted layer and a P type well region.
8. the power semiconductor of the L shaped source area of tool as claimed in claim 7, the degree of depth in this front district that it is characterized in that this L shaped source area is more than or equal to the degree of depth of this P+ type implanted layer in this this tagma.
9. the power semiconductor of the L shaped source area of tool as claimed in claim 4 is characterized in that this L shaped source area is made of a N+ type implanted layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510071202 CN1862830A (en) | 2005-05-13 | 2005-05-13 | Power semiconductor device with L shaped source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510071202 CN1862830A (en) | 2005-05-13 | 2005-05-13 | Power semiconductor device with L shaped source |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1862830A true CN1862830A (en) | 2006-11-15 |
Family
ID=37390205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510071202 Pending CN1862830A (en) | 2005-05-13 | 2005-05-13 | Power semiconductor device with L shaped source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1862830A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104638007A (en) * | 2013-11-14 | 2015-05-20 | 万国半导体股份有限公司 | Method to manufacture short channel trench MOSFET |
-
2005
- 2005-05-13 CN CN 200510071202 patent/CN1862830A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104638007A (en) * | 2013-11-14 | 2015-05-20 | 万国半导体股份有限公司 | Method to manufacture short channel trench MOSFET |
| CN104638007B (en) * | 2013-11-14 | 2017-08-18 | 万国半导体股份有限公司 | Short channel trench MOSFET and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1215570C (en) | MOS transistor assembly block | |
| US10763351B2 (en) | Vertical trench DMOSFET having integrated implants forming enhancement diodes in parallel with the body diode | |
| CN1205658C (en) | Method for manufacturing trench semiconductor device with multi-thickness gate oxide layer | |
| JP3742400B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN1227722C (en) | Method of Fabricating Trench Gate DMOS Transistors | |
| US9716152B2 (en) | Semiconductor device with electric field relaxation portion in insulating layer between lower and upper trench electrodes | |
| JP2013125827A (en) | Semiconductor device and method of manufacturing the same | |
| CN106920848B (en) | Charge-coupled power MOSFET device and manufacturing method thereof | |
| CN106876472B (en) | A charge-coupled power MOSFET device and its manufacturing method | |
| CN1738057A (en) | Metal Oxide Semiconductor Devices with Enhanced Shielding Structure | |
| CN1552102A (en) | Trench Field Effect Transistor with Self-Aligned Source and Contact | |
| US8471331B2 (en) | Method of making an insulated gate semiconductor device with source-substrate connection and structure | |
| CN104064470B (en) | Semiconductor device and its manufacture method | |
| JP2013115225A (en) | Power semiconductor device and method of manufacturing the same | |
| CN1941416A (en) | Ldmos device and method for manufacturing the same | |
| CN103311242A (en) | Semiconductor device | |
| CN101621031A (en) | Structure and method of forming a Thick Bottom Dielectric (TBD) for trench-gate devices | |
| CN1799145A (en) | Semiconductor device having an edge termination structure and method of manufacture thereof | |
| CN1589499A (en) | Trench MOSFET device with polycrystalline silicon source contact structure | |
| CN107123684A (en) | One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor | |
| CN102842502B (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN104319287A (en) | Trench gate type semiconductor device structure and manufacturing method thereof | |
| CN1658400A (en) | Semiconductor device and manufacturing method thereof | |
| CN110047935B (en) | Double split gate power MOSFET device and preparation method thereof | |
| CN102386220A (en) | IGBT with back reinforcing structure and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20061110 Address after: Taiwan Province, Taipei Applicant after: TAIDA ELECTRONICS INDUSTRY Co.,Ltd. Address before: The Cayman Islands Sikediya George town center 4 floor 2804 mailbox Applicant before: DAJING HOLDING Co.,Ltd. |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: TAIDA ELECTRONIC INDUSTRY CO LTD Free format text: FORMER OWNER: DAJING SEMICONDUCTOR CO., LTD. Effective date: 20080516 Owner name: OLNEY ZEUK ELECTRON CO., LTD. Free format text: FORMER OWNER: TAIDA ELECTRONIC INDUSTRY CO LTD Effective date: 20080516 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20080516 Address after: Hongkong Tongluowan 1 hysanavenue 17 f Applicant after: This group of Electronic Co.,Ltd. Address before: Burghardt Road, Neihu district in Taiwan city of Taipei province No. 186 post encoding: 114 Applicant before: DELTA ELECTRONICS, Inc. Effective date of registration: 20080516 Address after: Burghardt Road, Neihu district in Taiwan city of Taipei province No. 186 post encoding: Applicant after: DELTA ELECTRONICS, Inc. Address before: Taipei, Taiwan, China Applicant before: TAIDA ELECTRONICS INDUSTRY Co.,Ltd. |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |