DE102007063786B3 - Process for producing a doping zone in a semiconductor body - Google Patents

Abstract

Method for producing a doping zone in a semiconductor body, comprising:- providing a semiconductor body (1);- introducing at least one dopant (2) into the semiconductor body (1), the dopant (2) being selected from the group consisting of sulfur and selenium and mixtures thereof;- carrying out at least one short-term first temperature treatment (7) at a temperature T1; and- carrying out a second temperature treatment (8) which is longer than the first temperature treatment (7) at a temperature T2 to form a doping zone (6), with T1 being higher than T2.

Description

BACKGROUND OF THE INVENTION

Semiconductor components have a multiplicity of differently doped semiconductor regions which are formed, for example, by implanting a suitable dopant into a semiconductor body. Following the implantation, a temperature step typically takes place, as a result of which the dopant is activated and implantation damage that occurred during the implantation is healed. The formation of semiconductor regions by implantation is, for example, in the references U.S. 6,426,248 B2 , US 2002/0 060 353 A1 , US 2002/0009841 A1 such as U.S. 4,151,008 A described.

In some cases, power semiconductor components make special demands on the doping profile and the dopant concentration of semiconductor regions, since this allows the performance of power semiconductor components to be adjusted in a targeted manner. For example, IGBTs and diodes require a so-called field stop layer in front of their rear contact, the doping of which is high enough to completely dissipate the electric field that forms in the drift zone in front of the rear emitter or the rear metallization in the off state. If the field stop layer is not sufficiently dimensioned, the electric field in IGBTs penetrates very close to the emitter arranged on the back of the IGBT or to defects or spikes that were induced, for example, by the backside metallization in the semiconductor body of the IGBT. This can lead to increased leakage currents and even failure of the power semiconductor component. In the case of diodes, there is also the fact that inhomogeneous rear sides - particularly in the case of high-voltage diodes - lead to inhomogeneous current distributions when switching off. This favors the phenomenon of rounding of the blocking characteristic after a high switching load.

Power semiconductor components with a felstop layer are, for example, in DE 100 53 445 A1 , U.S. 6,610,572 B1 and DE 10 2004 013 932 A1 described. Out of U.S. 6,482,681 B1 and U.S. 6,707,111 B2 it is known to produce felstopp layers by implanting protons. Out of U.S. 6,441,408 B2 , WO 00/04596 A2 and WO 00/04598 A2 on the other hand, it is known to use sulfur or selenium to form field stop layers. Sulfur or selenium can also be used to form edge terminations, such as in U.S. 6,455,911 B1 described.

the US 2007/0 020 901 A1 describes a method of fabricating a gate electrode using a boron implantation. the US 2002/0 146 868 A1 describes the production of a thin-film transistor by depositing an amorphous silicon layer with subsequent thermal treatment. the US 2004/0 188 767 A1 describes the production of deep source/drain regions with an arsenic doping with a subsequent spike anneal and an RTP anneal.

As shown in the publications mentioned above, field stop layers can be produced in various ways. A frequent application is n-doped field stop layers, since IGBTs with an n-doped drift path, for example, are used in the majority of cases. In order to form the field stop layers at a certain depth in the semiconductor body, it is necessary to introduce the dopant used for this purpose deep into the semiconductor body. In the case of an n-doped field stop layer, however, the deep implantation or diffusion of dopants is often ruled out for manufacturing reasons, because the long thermal treatments at high temperatures required for this are generally not compatible with the doped glasses arranged on the front side of the semiconductor body and the source and are body regions of a MOS cell. Alternatively, the semiconductor body could be thinned to avoid very deep implantations and long diffusion processes. However, this would entail the handling of thin semiconductor bodies or wafer disks over many process steps, combined with a very high risk of disk breakage.

One method for producing deep field stops with a low temperature budget is proton doping with a subsequent annealing step. However, the doping profile of protons closely follows the implantation profile, ie the resulting doping is peak-shaped with very steep flanks. This leads to a "harder" field stop behavior, which is not always desirable. To mitigate the "hard" field stop behavior and to simulate "softer" profiles, several implantation steps, such as in the above publication U.S. 6,482,681 B1 shown to be carried out. However, this increases the manufacturing costs to a not inconsiderable extent.

Another variant for producing field stop layers is doping with rapidly diffusing donors such as selenium and sulfur. The diffusion temperatures are below about 1000°C with a maximum diffusion time of a few hours, which is still compatible with the cell structure of power semiconductor components. The problem with these dopants, however, is that the achievable doses of electrically active dopant in the semiconductor body are in the range of a few 10 ¹² /cm ² lies because at high implantation doses, the outdiffusion of selenium in particular increases sharply. Ultimately, only a small proportion of the implanted atoms in the semiconductor body remain electrically active. This proportion even decreases with increasing implantation dose.

SUMMARY OF THE INVENTION

In one embodiment, a method for producing a doping zone in a semiconductor body is provided. The method has the following steps: providing a semiconductor body; introducing at least one dopant into the semiconductor body, the dopant being selected from the group consisting of sulfur and selenium and mixtures thereof; Carrying out at least one short-term first temperature treatment at a temperature T1; and performing a second temperature treatment, which is longer than the first temperature treatment, at a temperature T2 to form a doping zone, with T1 being higher than T2.

The method makes it possible to produce a semiconductor body from a semiconductor material with a doping zone that has at least one dopant selected from the group consisting of sulfur, selenium, and mixtures thereof, with the concentration of the electrically active dopant in the doping zone being greater than 10 ¹⁶ /cm ² and in particular greater than 5*10 ¹⁶ /cm ² .

character list

The invention is described below with reference to the embodiments shown in the attached figures, from which further advantages and modifications result. However, the invention is not limited to the concretely described embodiments but can be modified and altered as appropriate. It is within the scope of the invention to suitably combine individual features and combinations of features of one embodiment with features and combinations of features of another embodiment in order to arrive at further embodiments according to the invention.

• 1A bis 1C zeigen einzelne Verfahrensschritte eines Verfahrens zur Herstellung einer Dotierungszone gemäß einer ersten Ausführungsform.
• 2A zeigt eine Emitterstruktur eines Leistungshalbleiterbauelements mit einer Feldstoppschicht gemäß einer weiteren Ausführungsform.
• 2B zeigt eine Emitterstruktur eines vertikalen Leistungshalbleiterbauelements mit einer Feldstoppschicht sowie hochdotierten Dotierstoffinseln gemäß einer weiteren Ausführungsform.
• 3A zeigt eine Kathodenstruktur eines IGBTs (Insulated Gate Bipolar Transistor).
• 3B zeigt eine Kathodenstruktur eines MCTs (MOS-controlled Thyristor).
• 3C zeigt eine Kathodenstruktur eines GTOs (Gate turn-off Thyristor).
• 4 zeigt eine Struktur einer Leistungsdiode gemäß einer weiteren Ausführungsform.
• 5 zeigt den schematischen Verlauf der elektrischen Feldstärke entlang einer vertikalen Linie durch die in 4 gezeigte Struktur.
• 6 zeigt das Nettodotierstoffprofil eines IGBTs mit einer Feldstoppschicht gemäß einer Ausführungsform.
• 7 zeigt das schematische Nettodotierstoffprofil eines IGBTs gemäß einer weiteren Ausführungsform.
• 8 zeigt die SIMS- und SRP-Analyse eines mit Selen implantierten Halbleiterkörpers nach einem erfolgten Laseranneal.
• 9 zeigt die Festkörpersättigungskonzentration verschiedener Dotierstoffe in Silizium als Funktion der Temperatur.
• 10A und 10B zeigen die Abhängigkeit der Diffusionskonstante verschiedener Dotierstoffe in Silizium in Abhängigkeit von der Temperatur.

Embodiments generally relate to semiconductor devices. In particular, they relate to power semiconductor components and in particular power semiconductor components with at least partially vertical current flow. Furthermore, embodiments relate to methods for manufacturing a semiconductor device.

• 1A until 1C show individual method steps of a method for producing a doping zone according to a first embodiment.
• 2A FIG. 1 shows an emitter structure of a power semiconductor component with a field stop layer according to a further embodiment.
• 2 B shows an emitter structure of a vertical power semiconductor component with a field stop layer and highly doped dopant islands according to a further embodiment.
• 3A shows a cathode structure of an IGBT (Insulated Gate Bipolar Transistor).
• 3B shows a cathode structure of an MCT (MOS-controlled thyristor).
• 3C shows a cathode structure of a GTO (gate turn-off thyristor).
• 4 12 shows a structure of a power diode according to another embodiment.
• 5 shows the schematic progression of the electric field strength along a vertical line through the in 4 structure shown.
• 6 12 shows the net doping profile of an IGBT with a field stop layer according to an embodiment.
• 7 12 shows the schematic net dopant profile of an IGBT according to a further embodiment.
• 8th shows the SIMS and SRP analysis of a semiconductor body implanted with selenium after a completed laser anneal.
• 9 shows the solid-state saturation concentration of various dopants in silicon as a function of temperature.
• 10A and 10B show the dependence of the diffusion constants of various dopants in silicon as a function of temperature.

DETAILED DESCRIPTION

Some embodiments will be explained below. The same structural features are identified in the figures with the same reference symbols. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs parallel to the lateral extent of a semiconductor material or a semiconductor body. Typically, a semiconductor body is in the form of a thin wafer or chip and comprises two surfaces located on opposite sides, one surface of which is referred to as the main surface. The lateral direction thus extends parallel to these surfaces. In contrast, the term "vertical" or "vertical direction" understood a direction that runs perpendicular to the main surface and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the wafer or chip.

The structures shown in the figures are not drawn to scale, but are only provided for a better understanding of the embodiments. Individual elements are shown enlarged compared to other elements in order to be able to show their structure more clearly.

Regarding 1A until 1C individual method steps of a manufacturing method according to one embodiment will first be described. The starting point is, for example, a semiconductor body 1 which has a first surface 3 and a second surface 4 lying opposite the first surface 3 . The semiconductor body 1 can consist of a monocrystalline silicon semiconductor material, for example. Other semiconductor materials such as silicon carbide (SiC) or compound semiconductors can also be used.

The semiconductor body 1 can be weakly n-doped, for example, with the dopant concentration being between approximately 1*10 ¹² /cm ³ and approximately 1*10 ¹⁵ /cm ³ . A dopant 2 in the region of the first surface 3 is introduced into regions of the semiconductor body 1 close to the surface, for example by means of implantation. The implanted dopants are, in particular, selenium, sulfur and mixtures thereof. The dopant can also be introduced as a compound or compounds containing selenium or sulfur. The dopant can be added with a dose of about 1*10 ¹¹ /cm ² to about 1*10 ¹⁵ /cm ² , in particular with a dose of up to about 1*10 ¹² /cm ² to about 1*10 ¹⁴ /cm ² , and an energy of about IkeV to about 10MeV, in particular with an energy of about 10keV to about 500keV, are implanted in the semiconductor body 1. Typically, the dopant 2 is implanted shallowly, for example to a depth of about 0.01 µm to about 3 µm, and more preferably about 0.02 µm to about 0.3 µm. The position of the implanted dopant 2 is in 1A indicated by the dashed line 5.

After the implantation has taken place, at least a first short-term temperature treatment is carried out ( 1B) . During the first temperature treatment, a short energy pulse typically acts essentially on the first surface 3 of the semiconductor body 1 . This can be, for example, a laser anneal or an RTA step (rapid thermal anneal). The aim of the first heat treatment is to eliminate damage caused by the implantation in the crystal lattice of the semiconductor body 1 as quickly as possible. Investigations have shown that crystal defects can be healed very effectively in particular if the first heat treatment is carried out very briefly and at very high temperatures becomes. The first temperature treatment should therefore be shorter than 10 seconds and in particular shorter than 5 seconds. In order to achieve particularly good recrystallization, the first heat treatment can also be shorter than 1 second and, in particularly favorable cases, even in the range from a few msec (for example less than 100 msec) to a few μsec and even below 1 μsec. Such short times can be achieved in particular when using a pulsed laser. The pulse duration of lasers can, for example, be set to times below 1 μsec, for example 200 nsec. In contrast to this, flash lamps, which are used for example in RTA methods, have a flash duration of a few msec. In the context of the present description, the “duration” of the first thermal treatment is understood to mean the duration, in particular, of an energy pulse acting on the semiconductor body 1 .

The use of very short-pulsed, short-wave lasers with a maximum pulse duration of, for example, 1000 nsec has proven to be particularly advantageous. Without intending to be limiting, the reason for this is understood as follows. The electromagnetic radiation of the laser light is almost completely absorbed in layers of the semiconductor body 1 that are very close to the surface. The laser light only penetrates a few nm into the semiconductor body 1 since the absorption coefficient of UV radiation, for example, with photon energy of around 3 to 5 eV is in the range of 3*10 ⁴ /cm to around 3*10 ⁶ /cm with crystalline silicon as the solid body . With a wavelength of the laser light in the range of about 300 nm, the radiated light power I ₀ has therefore dropped to 1/e*I ₀ within about 5 to 10 nm. The radiated energy leads to the formation of a “heat wave” that penetrates the semiconductor body 1 from the first surface 3 . If the energy supplied is correspondingly high, this heat wave leads to the melting of regions of the semiconductor body 1 near the surface. The semiconductor body 1 can thereby melt down to a depth of approximately 200 to 300 nm. Observations have shown that the speed at which the heat wave and the associated “melting wave” penetrates into the semiconductor body 1 depends on the duration of the exposure, with the speed being higher the shorter the exposure time is. It is also known from comparisons that short and rapid melting leads to better recrystallization of the semiconductor body.

As has surprisingly been shown, cluster formation of the introduced dopant can be reduced and in some cases even largely avoided by the brief first heat treatment. The problem of cluster formation will be described below, without wishing to be restricted, using the example of selenium implanted in a silicon semiconductor body.

Selenium has a comparatively low solid state saturation concentration in silicon, such as that made of 9 is evident. The solid-state saturation solubility describes the concentration of foreign atoms in a semiconductor lattice up to which the foreign atoms can be incorporated into the lattice without disturbing the solid-state lattice. If the concentration of foreign atoms, in this case selenium, is increased above the saturation concentration of the solid, selenium is eliminated from the lattice in the form of clusters. The cluster formation preferably takes place at condensation nuclei in the silicon lattice, with crystal defects playing a particular role here. However, crystal defects inevitably occur as a result of implantation. With correspondingly high implantation doses, amorphization of the semiconductor body can even occur. During a subsequent heat treatment to heal the crystal lattice, the selenium atoms diffuse and segregate at the existing crystal defects. The segregation leads to the formation of selenium clusters. Since selenium has a high diffusion constant in silicon, a large amount of selenium is concentrated in the clusters comparatively quickly.

However, the brief first temperature treatment leads to a significant reduction in the segregation of selenium. In this case, the first temperature treatment is carried out so briefly that there is essentially no diffusion of the selenium, or only a small one, in the semiconductor body. At the same time, the crystal lattice damage and thus the "condensation nuclei" are eliminated by the first temperature treatment. If the first temperature treatment is carried out in such a way that regions of the semiconductor body near the surface are melted, these regions are even cleaned by the melting, comparable to a floating zone method. Since selenium cannot diffuse appreciably due to the shortness of the first temperature treatment, selenium cannot collect in clusters either. The selenium atoms therefore remain largely evenly distributed in the silicon crystal lattice.

As a result, the formation of polyatomic selenium clusters, which act as a dopant source to a much lesser extent than implanted individual atoms, is avoided by the first heat treatment. As a result, cluster formation can be reduced or even significantly reduced even if the crystal lattice is clearly disturbed by the implantation of selenium, with the amorphization dose being approximately 2*10 ¹⁴ /cm ² , and even with doses that go beyond this.

One or more laser pulses can be used per irradiated area to carry out the first temperature treatment. A typical pulse duration is about 100 nsec to 300 nsec, which can lead to a melting duration of about 100 nsec to 800 nsec, depending on the power of the laser pulse. The energy surface density radiated in can be in the range from about 0.5 to 10 J/cm ² and in particular in a range greater than 3 J/cm ² . For example, XeCl eximer lasers with a laser light wavelength of 308 nm or Nd-YAG lasers with a wavelength of 532 nm can be used as the light source. Other suitable excimer lasers with other gas compositions are F ₂ (157 nm), Xe (172 nm), ArF (193 nm), KrF (248 nm), XeBr (282 nm) and XeF (351 nm) lasers, in particular the Excimer lasers with a very short emission wavelength are suitable for near-surface absorption. The maximum temperature during melting is around 1400°C. In some exemplary embodiments, the maximum temperature T1 reached during the first temperature treatment is at values above approximately 700°C. In other exemplary embodiments, the maximum temperature T1 reached during the first temperature treatment can even reach values above 1000° C. or even 1100° C. and above. The higher the maximum temperature T1 of the first temperature treatment, the shorter its duration can be, so that the formation of the clusters can be better avoided as a result.

In the case of the dopants usually used, such as boron, phosphorus and arsenic, only very little cluster formation is observed. Also, the solid state saturation solubility of these dopants, such as 9 can be removed is comparatively high, so that the concentration of electrically active dopant is also very high in the case of the dopants that are usually used. In this context, electrically active dopant is understood to mean the dopant atoms which are built into the lattice of the semiconductor body and can therefore be electrically activated, ie they act as donors or acceptors. In contrast, the dopant atoms concentrated in clusters are not built into the lattice and therefore cannot act as donors or acceptors.

Disturbing segregation can also occur with sulphur, indium and antimony. Indium in particular also shows a relatively low saturation solid solubility and a strong Ten denz to precipitation or segregation from the silicon lattice.

To carry out the first temperature treatment, for example, the beam cross section of a laser beam 7 can be concentrated in such a way that the desired energy density is achieved. The maximum area to be exposed therefore depends on the performance of the laser used. The exposed area can be cuboid with an edge length of about 15 mm, for example. For example, the semiconductor body 1 is melted on its first surface 3 with one pulse each time. Then the semiconductor body 1 or the imaging optics of the laser is offset relative to one another and a further surface area is melted by a further laser pulse. The offset is selected in such a way that there is a slight overlap between exposed areas, so that complete melting of all desired surface areas is ensured. If the implantation only takes place in individual surface areas, for example when using implantation masks, it is sufficient to only subject these areas to the first temperature treatment, i. H. to irradiate.

It should be noted that during the first temperature treatment, the energy is essentially only supplied to the first surface 3, so that the first temperature treatment only leads to melting or heating of the first surface 3 of the semiconductor body 1, particularly when short laser pulses are used. On the other hand, when flash lamps are used, the pulse duration of which is in the range of milliseconds, the second surface 4 can also heat up significantly. The effect of temperature is essentially limited to this upper side, so that structures located on the second surface 4 are not or only slightly thermally stressed. Since the radiated energy is dissipated relatively quickly, the heat treatment on the first surface 3 leads to only a slight warming up of the second surface 4. As a result, structures can even be present on the second surface 4, for example metallizations, which are produced at temperatures between 400° C. and 500 melting °C.

After the first temperature treatment, a second temperature treatment is carried out, the maximum temperature T2 of which is below the maximum temperature T1 of the first temperature treatment. The second temperature treatment is shown schematically in 1C shown. Typically, the second temperature treatment is a furnace process, through which the introduced dopant diffuses out and thus the spatial expansion of the doping zone, which is 1C denoted by 6 is adjusted. The second temperature treatment is shown schematically in 1C indicated by the wavy line 8. In addition to the dopant 2, the doping zone 6 can also be doped with other dopants, for example those of the basic doping of the semiconductor body. However, dopant 2 should be the dominant doping.

In a typical furnace process, the semiconductor body 1 can be introduced into a furnace that has been preheated to approximately 600° C., for example. After the semiconductor body 1 has heated up to this temperature, it is heated up in a controlled manner to, for example, 900° C. with a temperature gradient of approximately 1 to 10° C./min. Depending on the desired diffusion depth, the semiconductor body 1 is tempered at the target temperature for at least 1 minute and in particular for more than 5 minutes. Typical times are even at least 10 to 15 minutes, with an average tempering time at the target temperature being around 30 minutes. The duration of the second temperature treatment is the duration of the tempering at the target temperature T2. The semiconductor body is then cooled to temperatures below 600° C., for example with a temperature gradient of approximately 1 to 10° C./min and in particular approximately 5° C./min, and then removed from the furnace.

The target temperature or maximum temperature T2 of the second temperature treatment is below 1000° C. in some embodiments. In other exemplary embodiments, on the other hand, the target temperature T2 only reaches values in the range of up to 950°C. Typically, the target temperature T2 is approximately in the range of 700°C to 950°C.

The two-stage temperature treatment makes it possible to increase the concentration of the electrically active dopant to such an extent that it is above the solid-state saturation solubility in the semiconductor material of the semiconductor body. Therefore, in one embodiment, the dopant is introduced with a dose that is selected such that the concentration of the dopant in the semiconductor body is at least in regions higher than the solid-state saturation solubility of the semiconductor material of the semiconductor body.

The increase in the concentration of the electrically active dopant compared to the solid-state saturation solubility can be understood as follows, without wishing to be restricted. In melted semiconductor material, the dopant can be present in a concentration that can significantly exceed the solid-state saturation solubility. Rapid melting and, in particular, rapid cooling ensure that more dopant atoms are incorporated into the crystal lattice beyond the solid-state saturation solubility. Is the cooling to sufficient low temperatures so quickly that the dopant atoms are largely immobile, segregation is also suppressed to a certain extent or even largely. However, if the concentration of the dopant atoms is increased above the solid-state saturation solubility, this can lead to strains within the crystal. However, the built-in foreign atoms are electrically active, ie they sit at lattice sites. Strained semiconductor lattices can be tolerated in particular when they are in the form of thin layers, for example. The concentration of the electrically active dopant can therefore be higher than the solid-state saturation solubility in the semiconductor material of the semiconductor body, in particular in certain areas, for example in thin layers. For example, the concentration of the electrically active selenium in the doping zone 6 can be greater than 10 ¹⁶ /cm ³ and in particular greater than 5*10 ¹⁶ /cm ³ . This also applies to sulphur. With indium an even higher concentration can be achieved, for example about 1*10 ¹⁸ /cm ³ to about 3*10 ¹⁸ /cm ³ .

According to one embodiment, an optional barrier layer 9 can be formed at least in regions on the first surface 3 of the semiconductor body 1 . The barrier layer 9, which is 1C shown in broken lines can be formed, for example, by oxidizing the first surface 3 of the semiconductor body 1 and/or by depositing a layer on the first surface 3 . The barrier layer 9 is intended to prevent or significantly reduce evaporation of the introduced dopant from the first surface 3 . Examples of suitable materials for the barrier layer 9 are silicon oxide and silicon nitrite. Silicon oxide can be formed, for example, by thermal oxidation or deposition of a TEOS layer. Silicon nitride is typically deposited or formed by nitriding silicon. A combination of these materials is also possible.

If diffusion acceleration is desired when driving in the dopant by means of the second temperature treatment, silicon interstitial atoms, e.g. B. be introduced into the semiconductor body 1 by implanting an implantation substance different from the dopant 2 . The dose should still be well below the amorphization limit in order to avoid clustering of the introduced dopant 2. The implantation substance is typically introduced after the first temperature treatment. In contrast, the barrier layer 9 can be produced before or after the first temperature treatment. Atoms that are not doping with respect to the semiconductor material of the semiconductor body 1 are particularly suitable as the implant material. In the case of the silicon semiconductor body, these are in particular silicon atoms. However, silicon interstitial atoms are also injected by oxidation of the semiconductor surface, so that the formation of a thermally produced silicon oxide barrier layer 9 leads to the formation of interstitial atoms and thus to an acceleration of diffusion.

In a further embodiment, several short first temperature treatments can be carried out. In this case, further dopant 2 can be introduced into the semiconductor body 1 between the temperature treatments. It is thus possible, for example, to dispense with the second thermal treatment when using a plurality of laser pulses or higher-energy pulses to anneal the first surface 3 . This is of particular interest when a metallization or passivation has already been applied to the second top side 4 of the semiconductor body 1, since the extremely short energy pulses of the laser can keep the temperature on the second top side below approximately 400 to 450°C and thus the metallization and passivation located there remains in a compatible temperature range.

By using several melting laser pulses, the implanted dopant atoms are already slightly out-diffused. Since the melting also removes particles lying on the first surface 3, a number of implantations can also take place between which, for example, at least one laser annealing step (a first temperature treatment) is carried out in order to reduce the influence of masking. Disturbing masking is caused, for example, by contamination on the first surface 3, for example by particles. There is no implantation of dopant in the areas shaded by the particles lying thereon. However, the melting by the laser annealing steps also has an effect on the outdiffusion of the dopant into the shadowed regions, since the dopant atoms have a relatively long lateral diffusion length in the semiconductor body melted on the surface.

It is therefore possible to divide the first temperature treatment into at least two separate temperature steps, which are each very short and lead to heating of the first surface to a temperature T1, which can reach the melting temperature of the semiconductor material of the semiconductor body 1. It is also possible to introduce the dopant by at least two separate implantation steps, with a short temperature step following each implantation step. On a subsequent second temperature treatment, if after the last implants tion step, for example connecting several temperature steps, can also be dispensed with.

Regarding 2 until 5 Some semiconductor components will be described below in which the method outlined above for forming semiconductor regions, for example field stop layers, can be used. However, the method is not limited to the formation of field stop layers.

2A and 2 B show differently designed emitter structures, each of which can be arbitrarily combined with the in 3A until 3C cell structures shown can be combined. This is done by mentally combining one of the in 2A and 2 B structures shown with one of the in 3A until 3C structures shown, where the 2A until 2 B then the bottom of the semiconductor device and the 3A until 3C show the upper part of the semiconductor device. The combination occurs at the dashed line.

A semiconductor body 10 has, in the region of its first surface 11 (rear side in the present case), an emitter region 18 which is p-conductive, for example. A field stop layer 16 is arranged between the emitter region 18 and a drift region 13 which typically extends in a central region of the semiconductor body 10 . The drift region 13 is weakly n-doped, for example. The field stop layer 16 is also n-doped but has a higher dopant concentration than the drift region 13 . The field stop layer 16 can be formed, for example, by the method described above by introducing, for example by implantation, a dopant into the first surface 11 of the semiconductor body 10 with subsequent short first and longer second temperature treatment. The second temperature treatment then serves in particular to drive in the dopant, so that the field stop layer 16 extends further into the semiconductor body 10 than the emitter region 18, as seen from the first surface 11.

A backside metallization 31 connected to a backside connection 30 can be formed on the first surface 11 . It is also possible to use highly doped p-type dopant islands 17, as in 2 B shown to train. By using highly doped dopant islands 17, the on-state resistance of the semiconductor component can be further reduced. Alternatively, the dopant islands 17 can also be n-doped, in order to enable reverse conductivity of the component. A sequence of n- and p-doped dopant islands alternating in the lateral direction is also possible.

At the in 3A In the cell structure of an IGBT (Insulated Gate Bipolar Transistor) shown, p-conducting body regions 14, for example, are diffused in the region of the second surface 12 (in the present case the front side or main surface) of the semiconductor body 10. N-conducting source regions 15 are embedded in the body regions 14 on the second surface 12 . Conductive channels, in the present case n-channels, are formed in the body regions 14 on the second surface 12 below gate electrodes 20 . The base zone or the drift region 13 of the IGBT can thereby be controlled by means of the gate electrodes 20 . The gate electrodes 20 are electrically insulated by a gate dielectric 21 from the semiconductor body 10 and from a front-side metallization 41 applied to the second surface 12 and connected to a front-side connection 40 .

In circuit technology, on the other hand, the front side of the IGBT is referred to as the emitter and the back side as the cathode, although this does not correlate with the physical component structures of the IGBT.

In the 3B In contrast, the cathode structure shown of an MCT (MOS-controlled thyristor) has a p-conducting base region 24 with n-conducting emitter regions 23 embedded therein. P-type islands 22 are embedded in the emitter regions 23. FIG. Conductive channels 28 are formed between islands 22 and base 24 in emitter region 23 beneath gate electrodes 20 .

Instead of in the 3A and 3B In the planar cell structures shown with a planar gate, the gate can of course also be implemented in a trench in the semiconductor material, with the channel being formed being formed in a direction approximately perpendicular to the second surface 12 . Such arrangements are often referred to as trench gates.

In the 3C In contrast, the cathode structure shown of a GTO (gate turn-off thyristor) has a p-conducting base region 25 in which n-conducting cathode regions 26 are formed. Only the cathode regions 26 carry the cathode metallization 41. Gate electrodes 27 are arranged between the cathode regions 26. FIG.

4 1 shows the structure of a power diode with an emitter region 18 formed in the region of the first surface 11 and covered with an anode metallization 31 . Between the emitter region 18 (anode emitter) and the second surface 12 on the back here, which is covered with the cathode metallization 41, the drift region 13 extends, which is adjoined to the second surface 12 by a field stop layer 16. The effect of the field stop layer with respect to the electric field is in 5 implied. As can be seen from this, the electric field in the field stop layer 16 is reduced to a much greater extent than in the drift zone 13, so that the electric field and thus the blocking pn junction between the emitter region 18 and the drift zone 13 cannot penetrate through to the cathode metallization 41 on the rear can take action.

In the case of the in 2A and 2 B In the structures shown, the semiconductor component therefore generally comprises a first semiconductor region of the first conductivity type (here n-conducting), a second semiconductor region of the first conductivity type and a third semiconductor region of the second conductivity type that is complementary to the first conductivity type, the second semiconductor region lying between the first and third semiconductor regions and forms a transition area with each of these areas. The second semiconductor region is 2A and 2 B formed by the field stop layer 16, which is more highly doped than the drift region 13 forming the first semiconductor region. The third semiconductor region is formed by the emitter region 18 here.

In contrast, with the in 4 structure shown, the first semiconductor region is arranged between the second and third semiconductor regions.

The second semiconductor region (field stop layer 16) can be produced in all structures using the method described above and is in particular doped with sulfur or selenium, the concentration of the electrically active dopant being greater than 5*10 ¹⁵ /cm ³ .

The use of sulfur and in particular selenium to form the field stop layer 16 offers particular advantages with regard to the electrical behavior of semiconductor components. This is to be described using an IGBT as an example. An exemplary structure of an IGBT is obtained by combining the in 2A and 3A structures shown. An associated doping profile along a vertical line through the IGBT is in 6 shown. 50 designates the vertical extent of the source region 15, 51 the vertical extent of the body region 14, 52 that of the drift region 13, 53 that of the field stop layer 16 and 54 that of the emitter region 18.

Sulfur and selenium are dopants which, with respect to a silicon base material, each have at least two energy levels which lie within the band gap of the silicon and are at least 200 meV away from the conduction and valence bands of the silicon. As a result, these dopant atoms are only partially electrically active at room temperature. However, if the area doped with selenium or sulfur is covered by a space charge zone, the dopant atoms become fully active as double donors, ie they act as donors with two charge carriers released, so that a sulfur or selenium atom is doubly charged. The energy levels of sulfur and selenium are so deep in the silicon band gap that they are only fully electrically activated when a space charge zone is created. For example, one energy level of sulfur is 260 meV below the conduction band in silicon and a second energy level is 480 meV above the valence band. The band gap of silicon is 1120 meV. In the case of selenium, the two energy levels are about 310 meV and 590 meV, respectively, below the conduction band of silicon. The electrically active dopant profile therefore changes as a function of the extent of the space charge zone, with considerably more dopants being electrically active in the blocking case. In 6 the different behavior of sulfur and selenium is indicated, with the electrically effective dopant profile in the forward direction being indicated at 55 and the electrically effective dopant profile in the reverse direction being indicated at 56 . The sharp drop in the profile progression 56 is due to the fact that the space charge zone in the blocking case extends only approximately to the middle of the field stop layer 16 and the selenium or sulfur defects are therefore only fully activated in this area.

The field stop layer doped with selenium or sulfur can also be combined with proton doping. In this case, the deeper dopings seen from the first surface 1 or 11 are produced by means of proton implantations, while the comparatively shallow dopings are produced by means of selenium or sulfur implantations. Such combined field stop layers are particularly suitable for IGBTs. In 7 , which schematically shows the net dopant profile of an IGBT, two buried proton implantations 57 and a selenium doping 58 that is somewhat flatter in comparison thereto (in relation to the first surface 11) are shown as an example. More or fewer proton implantations can also be provided. The proton implantations each lead to comparatively sharp peaks in the doping profile. The proton-induced doping regions 57, which are deeper than the selenium doping 58, positively influence the switching behavior in the direction of softer switching if the penetration depths and the dopant concentrations or dopant doses are suitably dimensioned. As a result, there is no need for a flat and relatively highly doped proton doping to achieve the blocking capability, which has often been used up to now.

This is because a flat and relatively highly doped proton doping can worsen the short-circuit behavior. In addition, in the event of a short circuit, the electron density and thus the negative charge in the space charge zone is so high that the positive fixed charge of the dopant atoms is overcompensated. The electric field can therefore dynamically tilt with flat proton doping and then no longer has its highest field strength at the pn junction between body region 51 and drift path 52, but at the so-called nn+ junction at the rear field stop. The component dynamically loses its blocking capability and is destroyed. This problem can be reduced by using sulfur or selenium as a deep donor, since it is not completely ionized in thermal equilibrium and the electric field of the space charge zone initially penetrates deeper. This means that the IGBT's vertical pnp transistor has a smaller neutral base width (outside the space charge region) and thus has a higher current gain. More holes are thus injected from the rear p-emitter 54, which stabilize the electric field in its gradient and thus ensure the blocking capability.

8th shows measurement results of a selenium-doped doping zone that was produced using the method described above. Curve 60 shows the selenium measured with an SRP measurement (spreading resistance probing), which was implanted with a dose of 7*10 ¹³ /cm ² at an acceleration voltage of 90 keV. Only one laser annealing step with a pulse having an energy density of 3.8 J/cm ² was performed. As can be seen, the dopant concentration is in some areas even above 10 ¹⁷ /cm ³ and thus above the solid-state saturation solubility of selenium in silicon. The relatively sharp fall-off of profile 60 suggests the use of laser annealing. The selenium profile can also be determined with SIMS measurements (Secondary Ion Mass Spectroscopy), the measurement results of which are given in 8th are indicated by curve 61.

The significant reduction in selenium clusters and crystal defects could be verified by TEM analyses.

By using other measuring methods, for example DLTS measurements (deep level transient spectroscopy) or glow discharge mass spectroscopy, the incorporation of selenium or the other dopants can also be detected, from which conclusions can be drawn for the targeted setting of process parameters for the production of the doping zone.

The invention was essentially described on the basis of semiconductor power components and in particular power semiconductor components. However, the invention is not limited to this. However, the method described above can also be used to produce doping zones for CMOS semiconductor components, for example. Indium in particular is of interest here for setting the threshold voltage of a MOS transistor.

Reference List

1

semiconductor body

2

dopant

3

first surface

4

second surface

5

implanted dopant

6

Doping zone / doping area

7

Laser beam / first temperature treatment

8th

Furnace process / second temperature treatment

9

barrier layer

10

semiconductor body

11

first surface

12

second surface

13

Drift region / base zone / first semiconductor region

14

body area

15

source area

16

Doping zone / field stop layer / second semiconductor region

17

dopant islands

18

Emitter area / third semiconductor area

20

gate electrode

21

gate dielectric

22

Island

23

emitter area

24

base area

25

base area

26

cathode area

27

gate electrode

28

canal area

30

rear connector

31

Back metallization / anode metallization

40

front connector

41

Front side metallization / cathode metallization

50

source area

51

body area

52

drift area

53

stop layer

54

emitter area

55

Forward bias dopant profile

56

Reverse direction dopant profile

57

proton implantation

58

selenium implantation

60

SRP profile

61

SIMS profile

Claims (20)

Method for producing a doping zone in a semiconductor body, comprising: - Providing a semiconductor body (1); - Introduction of at least one dopant (2) in the semiconductor body (1), wherein the dopant (2) is selected from the group consisting of sulfur and selenium and mixtures thereof; - Carrying out at least one short-term first temperature treatment (7) at a temperature T1; and - Carrying out a second temperature treatment (8) which is longer than the first temperature treatment (7) at a temperature T2 to form a doping zone (6), with T1 being higher than T2. procedure after claim 1 , The first temperature treatment (7) being carried out in such a way that essentially no diffusion of the dopant (2) takes place in the semiconductor body (1). procedure after claim 1 or 2 , wherein the duration of the first temperature treatment (7) is shorter than 10 seconds and in particular shorter than 5 seconds. Method according to one of the preceding claims, wherein the duration of the second temperature treatment (8) is longer than 1 minute and in particular longer than 5 minutes. Method according to one of the preceding claims, wherein - the semiconductor body (1) has a first surface (3) and a second surface (4) opposite the first surface (3); - the dopant is introduced at least into a partial area in the area of the first surface (3); and - The first thermal treatment (7) is carried out in such a way that the energy for heating the semiconductor body (1) is supplied essentially only to its first surface (3). procedure after claim 5 , wherein the first thermal treatment (7) is carried out in such a way that the semiconductor body (1) at least partially melts on its first surface (3). A method according to any one of the preceding claims, wherein the first temperature treatment is an RTA step or a laser annealing step. Method according to one of the preceding claims, wherein the dopant (2) is introduced with a dose which is selected such that the concentration of the dopant in the semiconductor body (1) is at least in regions higher than the solid-state saturation solubility of the dopant in the semiconductor material of the semiconductor body. Method according to any one of the preceding claims, further comprising: - Forming a barrier layer (9) at least on a portion of the first surface (3) of the semiconductor body (1). procedure after claim 9 , wherein the barrier layer (9) is formed by oxidizing the first surface (3) of the semiconductor body (1) and/or by depositing a layer on the first surface (3). procedure after claim 9 or 10 , wherein the barrier layer (9) comprises a material or a combination of materials selected from the group consisting of silicon nitride and silicon oxide. Method according to any one of the preceding claims, further comprising: - Implanting one of the dopant (2) different implantation substance in the semiconductor body (1). procedure after claim 12 , wherein the implantation substance is implanted through the barrier layer (9). procedure after claim 12 or 13 , wherein the implantation material is non-doping with respect to the semiconductor material of the semiconductor body (1). Method according to one of the preceding claims, wherein the first temperature treatment comprises: - Carrying out at least two short temperature steps. procedure after claim 15 , wherein further dopant (2) is introduced into the semiconductor body (1) between the temperature steps. Method according to any one of the preceding claims, further comprising: - Implanting protons in the semiconductor body (1). Method according to one of the preceding claims, wherein T1 is in the range above 700°C and in particular above 1000°C and T2 in the range below 1000°C and in particular below 950°C. Method according to one of the preceding claims, wherein the semiconductor body consists of silicon. A method for producing a power semiconductor component or a CMOS semiconductor component, the production of a doping zone in a semiconductor body of the power semiconductor component or the CMOS semiconductor component using a method according to one of Claims 1 until 19 he follows.

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