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JP2000036515A - Bare chip mounting structure - Google Patents

Bare chip mounting structure

Info

Publication number
JP2000036515A
JP2000036515A JP10202245A JP20224598A JP2000036515A JP 2000036515 A JP2000036515 A JP 2000036515A JP 10202245 A JP10202245 A JP 10202245A JP 20224598 A JP20224598 A JP 20224598A JP 2000036515 A JP2000036515 A JP 2000036515A
Authority
JP
Japan
Prior art keywords
chip
film
mounting structure
conductive particles
anisotropic conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10202245A
Other languages
Japanese (ja)
Other versions
JP3486346B2 (en
Inventor
Masao Saito
雅男 斉藤
Yukio Yamada
幸男 山田
Motohide Takechi
元秀 武市
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dexerials Corp
Original Assignee
Sony Chemicals Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Chemicals Corp filed Critical Sony Chemicals Corp
Priority to JP20224598A priority Critical patent/JP3486346B2/en
Publication of JP2000036515A publication Critical patent/JP2000036515A/en
Application granted granted Critical
Publication of JP3486346B2 publication Critical patent/JP3486346B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To connect a bump-less IC chip with the terminal of a circuit board at low costs, by using an anisotropic conductive bounding material, and to maintain the high operation stability of the IC chip. SOLUTION: A bump-less chip IC1 in which an organic insulating film 6 is formed on a passivation film 4 and a circuit board 10 are connected by an anisotropic conductive bonding material 20 including hard conductive particles 23, at least whose surfaces are metal in this bare chip mounting structure. It is desired that the hardness of the hard conductive particles 23 is 300 kgf/mm2 or more as compressed hardness K value.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ICチップを、バ
ンプを形成することなく安価にフリップチップ実装する
ベアチップ実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bare chip mounting structure for flip-chip mounting an IC chip at low cost without forming bumps.

【0002】[0002]

【従来の技術】近年、電子機器に対する高機能化、軽量
化、薄型化、小型化の市場ニーズの高まりに伴い、ベア
チップをプリント配線板、その他の基板に直接的に実装
するフリップチップ実装がなされている。
2. Description of the Related Art In recent years, as market needs for electronic devices with higher functionality, lighter weight, thinner, and smaller sizes have increased, flip-chip mounting in which bare chips are directly mounted on printed wiring boards and other substrates has been performed. ing.

【0003】このフリップチップ実装においては、一般
に、図2に示したように、予め、ICチップ1のAl電
極パッド2上に、必要に応じてTi等のバリア層を介し
て、金、半田等でバンプ3を形成し、これと回路基板1
0の端子11とを、導電性粒子21と絶縁性接着剤22
からなる異方性導電接着材20で接続することがなされ
ている。
In this flip chip mounting, generally, as shown in FIG. 2, gold, solder or the like is previously placed on an Al electrode pad 2 of an IC chip 1 through a barrier layer such as Ti if necessary. To form bumps 3 and circuit board 1
0 terminal 11 and conductive particles 21 and insulating adhesive 22
The connection is made with an anisotropic conductive adhesive 20 made of.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、ICチ
ップ1へのバンプ3の形成には時間とコストがかかるの
で、図2のような実装構造を有する製品は生産性を向上
させることができず、コストアップがもたらされる。ま
た、バンプ3の形成は、通常、専門業者に委ねられるの
で、ICチップ1を回路基板10に実装して電子機器を
製造するメーカーにとっては、そのICチップ1に関す
る機密の外部への漏れが問題となる。
However, since it takes time and cost to form the bumps 3 on the IC chip 1, a product having a mounting structure as shown in FIG. 2 cannot improve the productivity. The cost is increased. In addition, since the formation of the bumps 3 is usually entrusted to a specialized trader, a maker who mounts the IC chip 1 on the circuit board 10 and manufactures an electronic device has a problem that the secret of the IC chip 1 is leaked to the outside. Becomes

【0005】このような問題に対しては、図3に示すよ
うに、ICチップ1のAl電極パッド2にバンプを形成
することなく、Al電極パッド2と回路基板10の端子
11とを直接に異方性導電接着材20で接続することが
考えられる。
To solve such a problem, as shown in FIG. 3, the Al electrode pad 2 is directly connected to the terminal 11 of the circuit board 10 without forming a bump on the Al electrode pad 2 of the IC chip 1. Connecting with an anisotropic conductive adhesive 20 is conceivable.

【0006】このようにAl電極パッド2にバンプを形
成しないICチップ1においては、Al電極パッド2の
表面にAl酸化被膜が生じるので、これを異方性導電接
着材20を用いて回路基板10と接続するためには、異
方性導電接着材20に使用する導電性粒子として、接続
時にAl電極パッド2の表面のAl酸化被膜を破って導
通をとれるようにする硬い粒子(硬質導電性粒子23)
を使用する必要がある。そこで、この硬質導電性粒子2
3としては、Ni等の金属粒子が使用される。
In the IC chip 1 in which no bump is formed on the Al electrode pad 2 as described above, an Al oxide film is formed on the surface of the Al electrode pad 2. In order to make connection, the conductive particles used for the anisotropic conductive adhesive 20 are hard particles (hard conductive particles) that break the Al oxide film on the surface of the Al electrode pad 2 to enable electrical conduction during connection. 23)
You need to use Therefore, the hard conductive particles 2
As 3, metal particles such as Ni are used.

【0007】しかし、導電性粒子として金属粒子等の硬
質導電性粒子23を使用すると、バンプの無い分、IC
チップ1のパッシベーション膜4と回路基板10あるい
はその端子11との間隔が狭まる。そのため、ICチッ
プ1と回路基板10とを異方性導電接着材20を用いて
接続する際に、異方性導電接着材20中の硬質導電性粒
子23の作用によりパッシベーション膜4にクラック5
が入り、パッシベーション膜4下の回路が腐食しやすく
なり、ICチップ1の動作安定性が低下するという問題
がある。
However, when the hard conductive particles 23 such as metal particles are used as the conductive particles, the amount of the bumps is reduced by the absence of bumps.
The distance between the passivation film 4 of the chip 1 and the circuit board 10 or its terminals 11 is reduced. Therefore, when connecting the IC chip 1 and the circuit board 10 using the anisotropic conductive adhesive 20, cracks 5 are formed on the passivation film 4 by the action of the hard conductive particles 23 in the anisotropic conductive adhesive 20.
And the circuit under the passivation film 4 is easily corroded, and the operation stability of the IC chip 1 is reduced.

【0008】本発明は、以上のようなベアチップを基板
にフリップチップ実装する際の問題に対し、バンプレス
ICチップと回路基板の端子とを異方性導電接着材を用
いて安価に接続し、かつそのICチップのパッシベーシ
ョン膜にクラックが入ることを防止し、ICチップの動
作安定性を高く維持できるようにすることを目的とす
る。
[0008] The present invention solves the above-mentioned problem of flip-chip mounting a bare chip on a substrate by connecting a bumpless IC chip and a terminal of a circuit board at low cost using an anisotropic conductive adhesive. It is another object of the present invention to prevent cracks from entering the passivation film of the IC chip and to maintain high operation stability of the IC chip.

【0009】[0009]

【課題を解決するための手段】上述の目的を達成するた
め、本発明は、パッシベーション膜上に有機絶縁膜を形
成したバンプレスベアチップICと回路基板とが、少な
くとも表面が金属の硬質導電性粒子を含有する異方性導
電接着材で接合されていることを特徴とするベアチップ
実装構造を提供する。
In order to achieve the above object, the present invention provides a bumpless bear chip IC having an organic insulating film formed on a passivation film and a circuit board, wherein at least the surface is formed of hard conductive particles having a metal surface. The present invention provides a bare chip mounting structure characterized by being joined by an anisotropic conductive adhesive containing:

【0010】本発明で使用するベアチップICはバンプ
を有していないので、回路基板への実装時に、そのAl
電極パッド表面にはAl酸化被膜が生じている。しか
し、このICチップと回路基板とを接続する異方性導電
接着材の導電性粒子として、少なくとも表面が金属の硬
質導電性粒子を使用するので、ICチップと回路基板と
の接続時にはこの硬質導電性粒子がAl酸化被膜を破
り、ICチップのAl電極パッドと回路基板の端子との
導通を確保することが可能となる。
Since the bare chip IC used in the present invention does not have bumps, when mounted on a circuit board, its bare chip
An Al oxide film is formed on the electrode pad surface. However, as the conductive particles of the anisotropic conductive adhesive for connecting the IC chip and the circuit board, hard conductive particles having at least a metal surface are used. The conductive particles break the Al oxide film, and it is possible to secure conduction between the Al electrode pad of the IC chip and the terminal of the circuit board.

【0011】さらに本発明では、実装するICチップと
して、パッシベーション膜上に有機絶縁膜を形成したも
のを使用する。この有機絶縁膜は、硬質導電性粒子とパ
ッシベーション膜との緩衝材として機能し、パッシベー
ション膜にクラックが入ることを防止する。
In the present invention, an IC chip having an organic insulating film formed on a passivation film is used as an IC chip to be mounted. The organic insulating film functions as a buffer between the hard conductive particles and the passivation film, and prevents the passivation film from being cracked.

【0012】したがって、本発明によれば、安価でかつ
ICチップの動作安定性の良いICチップの実装構造を
得ることが可能となる。本発明の実装構造は、ICチッ
プのパッケージ用途にも有用なものとなり、さらにこの
実装構造を繰り返し形成することにより、マルチチップ
モジュールの形成にも有用なものとなる。
Therefore, according to the present invention, it is possible to obtain an IC chip mounting structure which is inexpensive and has good operation stability of the IC chip. The mounting structure of the present invention is also useful for IC chip package applications, and is also useful for forming a multi-chip module by repeatedly forming this mounting structure.

【0013】[0013]

【発明の実施の形態】以下、本発明の異方性導電接着材
を、図面を参照しつつ詳細に説明する。なお、各図中、
同一符号は同一又は同等の構成要素を表している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The anisotropic conductive adhesive of the present invention will be described below in detail with reference to the drawings. In each figure,
The same reference numerals represent the same or equivalent components.

【0014】図1は、本発明のベアチップ実装構造の断
面図である。同図のように、本発明において、ICチッ
プ1はAl電極パッド2上にバンプを有しておらず、パ
ッシベーション膜4上に有機絶縁膜6を有しており、I
Cチップ1と回路基板10の端子11とを異方性導電接
着材20を用いて接続した構造となっている。
FIG. 1 is a sectional view of a bare chip mounting structure according to the present invention. As shown in the figure, in the present invention, the IC chip 1 has no bump on the Al electrode pad 2, has an organic insulating film 6 on the passivation film 4,
The structure is such that the C chip 1 and the terminal 11 of the circuit board 10 are connected using an anisotropic conductive adhesive 20.

【0015】ここで、パッシベーション膜4としては、
ICチップの製造の最終段階で表面保護膜として形成さ
れた公知のSiN膜等をそのまま使用することができ
る。
Here, as the passivation film 4,
A known SiN film or the like formed as a surface protective film in the final stage of the production of the IC chip can be used as it is.

【0016】パッシベーション膜4上の有機絶縁膜6と
しては、異方性導電接着材20中の硬質導電性粒子23
のパッシベーション膜4に対する緩衝材として機能し、
パッシベーション膜4にクラックが発生することを防止
できる限り、種々の絶縁性膜を形成することができる。
例えば、BTレジン(ビスマレイミドトリアジン樹
脂)、PEEK(ポリエーテルエーテルケトン)、PP
S(ポリフェニレンスルフィド)、POB(ポリオキシ
ベンゾイル)、PEI(ポリエーテルイミド)、PAI
(ポリアミドイミド)等の膜を形成することができる。
中でも、緩衝性、耐熱性の点から厚さ1〜10μmのポ
リイミド膜が好ましい。
As the organic insulating film 6 on the passivation film 4, the hard conductive particles 23 in the anisotropic conductive adhesive 20 are used.
Functions as a buffer for the passivation film 4 of
Various insulating films can be formed as long as the generation of cracks in the passivation film 4 can be prevented.
For example, BT resin (bismaleimide triazine resin), PEEK (polyetheretherketone), PP
S (polyphenylene sulfide), POB (polyoxybenzoyl), PEI (polyetherimide), PAI
A film such as (polyamide imide) can be formed.
Among them, a polyimide film having a thickness of 1 to 10 μm is preferable from the viewpoint of buffering property and heat resistance.

【0017】この有機絶縁膜6は、Al電極パッド2が
開口するように感光性有機絶縁膜形成用組成物を塗布
し、感光し、エッチングすることにより形成できる。
The organic insulating film 6 can be formed by applying a photosensitive organic insulating film forming composition so that the Al electrode pad 2 is opened, exposed to light, and etched.

【0018】一方、異方性導電接着材20としては、少
なくとも表面が金属の硬質導電性粒子23と、絶縁性接
着剤22からなるものを使用する。
On the other hand, as the anisotropic conductive adhesive 20, a material having at least a surface made of hard conductive particles 23 of metal and an insulating adhesive 22 is used.

【0019】異方性導電接着材20を構成する導電性粒
子として、少なくとも表面が金属の硬質導電性粒子23
を使用することにより、異方性導電接着材20でICチ
ップ1と回路基板10とを接続するときに、Al電極パ
ッド2上に生じているAl酸化膜を破ってAl電極パッ
ド2と回路基板10の端子11とを確実に導通させるこ
とができる。
The conductive particles constituting the anisotropic conductive adhesive 20 include hard conductive particles 23 having at least a metal surface.
When the IC chip 1 and the circuit board 10 are connected to each other with the anisotropic conductive adhesive material 20, the Al oxide film formed on the Al electrode pad 2 is broken and the Al electrode pad 2 and the circuit board Conduction with the ten terminals 11 can be ensured.

【0020】硬質導電性粒子23としては、硬度が圧縮
硬さK値として300kgf/mm2以上の粒子を使用
することが好ましい。この圧縮硬さK値とは、次式
(I)
As the hard conductive particles 23, it is preferable to use particles having a hardness of 300 kgf / mm 2 or more as a compression hardness K value. This compression hardness K value is expressed by the following equation (I)

【0021】[0021]

【数1】K=E/(1−σ2) (I) (式中、Eは球体の弾性率、σは球体のポアッソン比を
表す。)により定義され、次式(II)
K = E / (1−σ 2 ) (I) (where E represents the elastic modulus of the sphere and σ represents the Poisson's ratio of the sphere), and the following equation (II)

【0022】[0022]

【数2】 K=(3/√2)・F・S-3/2・R-1/2 (II) (式中、Fは球体にかける圧縮力、Sは圧縮変形量、R
は球体の半径を表す。)により近似的に求められる値で
あり、球体の硬さを普遍的かつ定量的に表すものであ
る。従ってK値により微粒子の硬さを定量的かつ一義的
に表すことができる。
[Number 2] K = (3 / √2) · F · S -3/2 · R -1/2 (II) ( wherein, F is compressive force applied to the sphere, S is the amount of compressive deformation, R
Represents the radius of the sphere. ) Is a value approximately determined by the formula (1), and represents the hardness of the sphere universally and quantitatively. Therefore, the hardness of the fine particles can be quantitatively and uniquely represented by the K value.

【0023】この式(II)は次のようにして導びかれた
ものである。即ち、ランダウ−リフシッツ理論物理学教
程「弾性理論」(東京図書1972年発行)42頁の2
つの弾性球体の接触の式である次式(1)、(2)
This equation (II) is derived as follows. That is, the Landau-Lifshitz theoretical physics curriculum "Elasticity" (published by Tokyo Book, 1972), p.
Equations (1) and (2), which are equations for contact between two elastic spheres

【0024】[0024]

【数3】 h=F2/3[D2(1/R+1/R’)]1/3 (1) D=(3/4)[(1−σ2)/E+(1−σ’2)/E’] (2) (式中、R、R’は各弾性球体の半径、hはR+R’と
両球体の中心間の距離の差、Fは圧縮力、EとE’は2
つの弾性球体の弾性率、σとσ’は2つの弾性球体のポ
アッソン比を表す。)に対し、一方の弾性球体を板に置
き換え、かつ両側から圧縮し、R’→∞、E≫E’とす
ることにより近似的に次式(3)
H = F 2/3 [D 2 (1 / R + 1 / R ′)] 1/3 (1) D = (3/4) [(1−σ 2 ) / E + (1−σ ′ 2) ) / E '] (2) (where R and R' are the radii of the respective elastic spheres, h is the difference between the distance between R + R 'and the center of the two spheres, F is the compressive force, and E and E' are 2)
The elastic modulus of one elastic sphere, σ and σ ′, represent the Poisson's ratio of the two elastic spheres. ), One of the elastic spheres is replaced by a plate and compressed from both sides to make R ′ → ∞ and E≫E ′, thereby approximating the following equation (3).

【0025】[0025]

【数4】 F=(21/2/3)(S3/2)(E・R1/2)(1−σ2) (3) (式中、Sは圧縮変形量を表す。)を得、この式(3)
を上述のKの定義式(I)に適用することにより前述の
式(II)が得られる。
F = (2 1/2/3 ) (S 3/2 ) (E · R 1/2 ) (1-σ 2 ) (3) (where S represents the amount of compressive deformation) And this equation (3)
Is applied to the above-described definition equation (I) of K to obtain the above-described equation (II).

【0026】硬質導電性粒子23の具体例としては、N
i、硬質半田、Co、Cu等からなる金属粒子、硬質プ
ラスチックを核材とし、その表面にNi、Co、Cu等
の金属層を形成した粒子等をあげることができる。な
お、半田粒子を使用する場合には、ICのメモリー保護
の点からPb含有量の低い低α線タイプのものが好まし
い。
Specific examples of the hard conductive particles 23 include N
i, metal particles made of hard solder, Co, Cu, or the like; and particles obtained by forming a metal layer of Ni, Co, Cu, etc. on the surface of a hard plastic as a core material. When solder particles are used, a low α-ray type having a low Pb content is preferable from the viewpoint of memory protection of the IC.

【0027】また、硬質導電性粒子23の粒径は、有機
絶縁膜6の形成材料にもよるが、有機絶縁膜6の膜厚以
上、特に膜厚の150%〜400%とすることが好まし
く、通常、1.5〜20μmとすることが好ましい。こ
れにより、硬質導電性粒子23を有効に変形させ、接続
信頼性を確保することができる。
The particle size of the hard conductive particles 23 depends on the material for forming the organic insulating film 6, but is preferably not less than the thickness of the organic insulating film 6, particularly preferably 150% to 400% of the film thickness. Usually, it is preferably 1.5 to 20 μm. Thereby, the hard conductive particles 23 can be effectively deformed, and the connection reliability can be secured.

【0028】異方性導電接着材20を構成する絶縁性接
着剤22としては、種々の熱硬化性接着剤や熱可塑性接
着剤を使用することができる。ICチップ1の実装後の
信頼性の点からは、エポキシ系樹脂、ウレタン系樹脂、
アクリレート系樹脂、BTレジン樹脂等の熱硬化性接着
剤を使用することが好ましい。なお、これら樹脂成分か
ら絶縁性接着剤を調製する場合に、単一種の樹脂成分を
使用してもよく、複数種を混合して使用してもよい。
As the insulating adhesive 22 constituting the anisotropic conductive adhesive 20, various thermosetting adhesives or thermoplastic adhesives can be used. From the viewpoint of reliability after mounting the IC chip 1, epoxy resin, urethane resin,
It is preferable to use a thermosetting adhesive such as an acrylate resin or a BT resin. When preparing an insulating adhesive from these resin components, a single type of resin component may be used, or a plurality of types may be mixed and used.

【0029】異方性導電接着材20としては、硬質導電
性粒子23と絶縁性接着剤22とを混合し、液状に調製
したもの、あるいはフィルム状に成形したものを使用す
ることができるが、作業性の点からはフィルム状のもの
を使用することが好ましい。
As the anisotropic conductive adhesive 20, one prepared by mixing the hard conductive particles 23 and the insulating adhesive 22 to prepare a liquid or a film can be used. It is preferable to use a film-like material from the viewpoint of workability.

【0030】ICチップ1を実装する回路基板10には
特に制限はない。公知のフィルム状あるいは板状のプリ
ント配線基板を使用することができる。
There is no particular limitation on the circuit board 10 on which the IC chip 1 is mounted. A well-known film-shaped or plate-shaped printed wiring board can be used.

【0031】上述の異方性導電接着材20を用いてIC
チップ1と回路基板10とを接続し、本発明の実装構造
を得るに際しては、ICチップ1と回路基板10との間
に異方性導電接着材20を配し、加熱加圧する。
An IC using the anisotropic conductive adhesive 20 described above
In connecting the chip 1 and the circuit board 10 to obtain the mounting structure of the present invention, an anisotropic conductive adhesive 20 is provided between the IC chip 1 and the circuit board 10 and heated and pressed.

【0032】[0032]

【実施例】以下、本発明を実施例に基づいて具体的に説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments.

【0033】実施例1〜3、比較例1,2 図4に示すように、ICチップ1の全面に、クラックチ
ェック用パターンとして、2μm間隔のAlパターン7
を形成し、その上にパッシベーション膜を、ICチップ
1の全周にわたって形成されているAl電極パッド2が
開口するように形成した。さらに実施例1〜3にはパッ
シベーション膜上に厚さ2μm又は5μmのポリイミド
膜を表1に示すように設けた。このポリイミド膜のパタ
ーンは、感光性ポリイミド膜を塗布し、感光し、エッチ
ングすることにより行った。
Examples 1 to 3 and Comparative Examples 1 and 2 As shown in FIG. 4, on the entire surface of the IC chip 1, Al patterns 7 at 2 μm intervals were used as crack check patterns.
Was formed thereon, and a passivation film was formed thereon so that the Al electrode pad 2 formed over the entire periphery of the IC chip 1 was opened. Further, in Examples 1 to 3, a polyimide film having a thickness of 2 μm or 5 μm was provided on the passivation film as shown in Table 1. The pattern of the polyimide film was formed by applying a photosensitive polyimide film, exposing it to light, and etching.

【0034】一方、フェノキシ樹脂、エポキシ樹脂、硬
化剤を50:50:30の重量比で配合した絶縁性接着
剤と、表1に示す導電性粒子とから異方性導電接着材を
調製し、これを乾燥膜厚が20μmになるようにフィル
ム化し、異方性導電膜を得た。得られた異方性導電膜を
配線板上に貼付し、その上に上述のICチップを重ね合
わせ、温度180℃、圧力400kgf/cm2で20
秒間加熱加圧することによりICチップを実装した。な
お、異方性導電膜の成膜と配線板への貼付に代えて、異
方性導電接着材を配線板上に乾燥膜厚が20μmとなる
ように直接塗布することによっても同様にICチップを
実装することができた。
On the other hand, an anisotropic conductive adhesive was prepared from an insulating adhesive containing a phenoxy resin, an epoxy resin, and a curing agent in a weight ratio of 50:50:30, and the conductive particles shown in Table 1. This was formed into a film so as to have a dry film thickness of 20 μm to obtain an anisotropic conductive film. The obtained anisotropic conductive film is stuck on a wiring board, and the above-mentioned IC chip is superimposed thereon, and the temperature is set to 180 ° C. and the pressure is set to 400 kgf / cm 2 for 20 minutes.
The IC chip was mounted by heating and pressing for 2 seconds. In addition, instead of forming the anisotropic conductive film and attaching it to the wiring board, an IC chip can be similarly formed by directly applying an anisotropic conductive adhesive on the wiring board so as to have a dry film thickness of 20 μm. Could be implemented.

【0035】評価 実施例及び比較例で作製したICチップの実装構造につ
いて、(1)実装直後とエージング後のパッシベーション
膜のクラックの有無、(2)導通性を次のように評価し
た。これらの結果を表1に示す。
Evaluation Regarding the mounting structure of the IC chips manufactured in the examples and comparative examples, (1) the presence or absence of cracks in the passivation film immediately after mounting and after aging, and (2) the conductivity were evaluated as follows. Table 1 shows the results.

【0036】(1)パッシベーション膜のクラックの有無 導電性粒子がパッシベーション膜にクラックを生じさ
せ、Alパターン7に到達すると図4のAlパターン7
はショートするので、実装直後のパッシベーション膜の
クラックの有無を、導通検査でショートの有無を調べる
ことにより行った。また、温度85℃、湿度85%のオ
ーブン中で加湿エージングさせた場合に、パッシベーシ
ョン膜にクラックが入ると水分が侵入し、Alパターン
7が腐食に至るので、加湿エージング後に赤外線顕微鏡
でAlパターン7を観察し、その腐食の有無を調べるこ
とにより、エージング後のパッシベーション膜のクラッ
クの有無を判定した。
(1) Presence or Absence of Cracks in Passivation Film When the conductive particles cause cracks in the passivation film and reach the Al pattern 7, the Al pattern 7 in FIG.
Was short-circuited, and the presence or absence of cracks in the passivation film immediately after mounting was determined by checking the presence or absence of short-circuits by a continuity test. Further, when humidification aging is performed in an oven at a temperature of 85 ° C. and a humidity of 85%, if cracks enter the passivation film, moisture penetrates and the Al pattern 7 is corroded. Was observed and the presence or absence of the corrosion was examined to determine the presence or absence of cracks in the passivation film after aging.

【0037】(2)導通性 四端子法により、ICチップと配線板の端子との異方性
導電膜による接続部に電流を1mA流し、その接続部に
かかる電圧を測定し、接続部の抵抗を求めた(図4参
照)。この場合、接続部の抵抗は、ICチップの実装直
後と、温度85℃、湿度85%のオーブン中での加湿エ
ージング後に測定した。そして、加湿エージング後の抵
抗が、実装直後の抵抗の2倍以上になった場合に導通が
不安定であると評価し、2倍未満を良好と評価した。
(2) Conductivity A 1 mA current is applied to the connection between the IC chip and the terminal of the wiring board by the anisotropic conductive film by the four-terminal method, the voltage applied to the connection is measured, and the resistance of the connection is measured. (See FIG. 4). In this case, the resistance of the connection portion was measured immediately after mounting the IC chip and after humidification aging in an oven at a temperature of 85 ° C. and a humidity of 85%. When the resistance after humidification and aging became twice or more as large as the resistance immediately after mounting, conduction was evaluated as unstable, and less than twice was evaluated as good.

【0038】[0038]

【表1】 実施例1 実施例2 実施例3 ホ゜リイミト゛ 膜の厚さ 2μm 2μm 5μm 導電性粒子(粒径) Ni(6μm) フ゜ラスチック核(5μm) 鉛レス半田(5μm) Niメッキ(0.2μm) 圧縮硬さK値(kgf/mm2) 約6000 800 約4000 ハ゜ッシヘ゛ーション 膜クラック 実装直後 無 無 無 エーシ゛ンク゛後 無 無 無 導通性 実装直後 良好 良好 良好 エーシ゛ンク゛後 良好 良好 良好 比較例1 比較例2 ホ゜リイミト゛ 膜 無し 無し 導電性粒子(粒径) Ni(6μm) フ゜ラスチック核(5μm) Niメッキ(0.2μm) 圧縮硬さK値(kgf/mm2) 約6000 200 ハ゜ッシヘ゛ーション 膜クラック 実装直後 有 無 エーシ゛ンク゛後 有 無 導通性 実装直後 良好 不安定 エーシ゛ンク゛後 良好 不安定 [Table 1] Example 1 Example 2 Example 3 Example 3 Polyimide film thickness 2 μm 2 μm 5 μm Conductive particles (particle size) Ni (6 μm) Plastic core (5 μm) Leadless solder (5 μm) Ni plating (0.2 μm) Compression hardness K value (kgf / mm 2 ) Approx.6000 800 Approx.4000 hash film crack Immediately after mounting None None None After aging None None None Conductivity Immediately after mounting Good Good Good After aging Good Good Good Comparative example 1 Comparative example 2 Polyimid film None None Conductive particles (particle size) Ni (6 μm) Plastic core (5 μm) Ni plating (0.2 μm) Compression hardness K value (kgf / mm 2 ) Approx. 6000 200 Immediately Yes No After post-acquisition Yes No Conductivity Immediately after mounting Good Unstable Post-acquisition Good Unstable

【0039】表1の結果から、ICチップにポリイミド
膜を設けることにより、パッシベーション膜のクラック
を防止できることがわかる。また、導電性粒子が軟質で
あるとAl電極パッドとの導通が十分にとれないことが
わかる(比較例2)。
From the results shown in Table 1, it can be seen that cracks in the passivation film can be prevented by providing the polyimide film on the IC chip. Further, it can be seen that if the conductive particles are soft, sufficient conduction with the Al electrode pad cannot be obtained (Comparative Example 2).

【0040】[0040]

【発明の効果】本発明によれば、ICチップと基板の端
子とを異方性導電接着材を用いて安価に接続し、かつそ
の場合にバンプを形成しなくても、ICチップのパッシ
ベーション膜にクラックが入らず、ICチップの動作安
定性を高く維持することが可能となる。
According to the present invention, the IC chip and the terminal of the substrate are connected at low cost by using an anisotropic conductive adhesive, and in this case, the passivation film of the IC chip can be formed without forming bumps. Cracks do not occur, and the operation stability of the IC chip can be kept high.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のICチップの実装構造の断面図であ
る。
FIG. 1 is a sectional view of a mounting structure of an IC chip of the present invention.

【図2】従来のICチップの実装構造の断面図である。FIG. 2 is a cross-sectional view of a conventional IC chip mounting structure.

【図3】従来のICチップの実装構造をバンプレスにし
た場合の断面図である。
FIG. 3 is a cross-sectional view of a bumpless mounting structure of a conventional IC chip.

【図4】ICチップに形成したAlパターンの平面図で
ある。
FIG. 4 is a plan view of an Al pattern formed on an IC chip.

【符号の説明】[Explanation of symbols]

1 ICチップ 2 Al電極パッド 3 バンプ 4 パッシベーション膜 5 クラック 6 有機絶縁膜 7 Alパターン 10 回路基板 11 端子 20 異方性導電接着材 21 導電性粒子 22 絶縁性接着剤 23 硬質導電性粒子 DESCRIPTION OF SYMBOLS 1 IC chip 2 Al electrode pad 3 Bump 4 Passivation film 5 Crack 6 Organic insulating film 7 Al pattern 10 Circuit board 11 Terminal 20 Anisotropic conductive adhesive 21 Conductive particles 22 Insulating adhesive 23 Hard conductive particles

───────────────────────────────────────────────────── フロントページの続き (72)発明者 武市 元秀 栃木県鹿沼市さつき町12−3 ソニーケミ カル株式会社内 Fターム(参考) 4M105 AA01 BB09 FF00 FF06  ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Motohide Takeichi 12-3 Satsukicho, Kanuma-shi, Tochigi Sony Chemical Corporation F-term (reference) 4M105 AA01 BB09 FF00 FF06

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 パッシベーション膜上に有機絶縁膜を形
成したバンプレスベアチップICと回路基板とが、少な
くとも表面が金属の硬質導電性粒子を含有する異方性導
電接着材で接合されていることを特徴とするベアチップ
実装構造。
1. A bumpless bear chip IC having an organic insulating film formed on a passivation film and a circuit board are bonded at least on their surfaces with an anisotropic conductive adhesive containing hard conductive particles of metal. Features a bare chip mounting structure.
【請求項2】 硬質導電性粒子の硬度が、圧縮硬さK値
として300kgf/mm2以上である請求項1記載の
ベアチップ実装構造。
2. The bare chip mounting structure according to claim 1, wherein the hardness of the hard conductive particles is 300 kgf / mm 2 or more as a compression hardness K value.
【請求項3】 有機絶縁膜がポリイミド膜である請求項
1又は2記載のベアチップ実装構造。
3. The bare chip mounting structure according to claim 1, wherein the organic insulating film is a polyimide film.
【請求項4】 ポリイミド膜の厚みが1〜10μmであ
る請求項1〜3のいずれかに記載のベアチップ実装構
造。
4. The bare chip mounting structure according to claim 1, wherein the thickness of the polyimide film is 1 to 10 μm.
JP20224598A 1998-07-16 1998-07-16 Bare chip mounting structure Expired - Lifetime JP3486346B2 (en)

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