JP2000039937A - Computer system and power save control method thereof - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To enable a sufficient power saving to be realized while minimizing a decrease in system performance, and to extend an operation time by a battery. Kind Code: A1 When a wake-up event occurs while the CPU is kept in a sleep state, a CP
The operation speed of U11 is not immediately returned to the operation speed before the transition to the sleep state, but is gradually changed from a low level to a predetermined high level at predetermined time intervals by throttling control by the CPU throttling control circuit 152. It is gradually raised until. This makes it possible to reduce the power consumption of the CPU 11 and to extend the battery operation time, as compared to the case where the operation speed of the CPU 11 is immediately returned to the operation speed before the transition to the sleep state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system such as a battery-powered personal computer, and more particularly to a computer system having a power saving function.

[0002]

2. Description of the Related Art In recent years, various laptop or notebook personal computers (PCs) which are easy to carry and can be operated by a battery have been developed. In this type of PC, the performance of the CPU has been improved, and this has made it possible for the user to easily obtain a comfortable use environment.

[0003] However, with the advancement of CPU performance, CP
The power consumption of U also increases, which causes problems such as an increase in power consumption of the entire PC and a reduction in battery operating time.

Therefore, recently, various power management technologies have begun to be developed. Typical power management techniques used in PCs include LCD brightness control, HDD automatic motor off, and CPU sleep control.

However, such conventional power management has a power saving function (LCD brightness control, HD control, etc.).
D, automatic motor-off, CPU sleep control, etc.) is fixedly determined in advance by user setting as to whether to use or not.

[0006] This is a source of trouble in balancing power saving and system performance, and has been a hindrance to the performance of the system. In other words, in order to enhance the power saving function, it is necessary to allow the system performance to always be kept low (regardless of the remaining battery power and the operating status of the system). When I kept it high, I had to give up some power savings.

In the conventional typical CPU sleep control, control is performed such that the CPU state is shifted to a low power consumption sleep state when idle, and the CPU state is returned to the original state when a wake event such as an interrupt occurs. Done. In this case, once the wake event occurs, the CPU is immediately returned to the performance before the transition to the sleep state. Thus, for example, once a user performs a keyboard or mouse operation, the CPU returns to the maximum performance or a predetermined performance close thereto, and the performance is maintained until the idle is detected again. You. Therefore, especially when the system operation rate is relatively low, a lot of wasteful power is consumed.

Also, a CP used as a sleep state
The U state has always been fixed. That is, ACPI (Advanced Config)
ratio and Power Manageme
nt InterfaceSpecificatio
In the n) specification, three states C1 to C3 usable as a sleep state are defined as the CPU power state, in addition to the C0 state used as a normal operation state. These power states C1 to C3 are C
Latency to return to the 0 state and sleep depth are different, and power consumption decreases in the order of C1, C2, and C3, and latency to return to the C0 state increases in the order of C1, C2, and C3. Become.

However, conventionally, in an environment without an ACPI-OS, which state among C1 to C3 to use as a sleep state is fixedly defined in advance by the system, and the operating state of the system and the like are defined. There is no control to dynamically switch the power state to be used according to. For this reason, there has been a problem that an appropriate CPU power state cannot be selected, and only a shallow sleep can be used even when a shift to a deeper sleep state is possible.

[0010]

As described above, conventionally, in order to perform power saving, it is necessary to decrease the performance of the system in a fixed manner. Therefore, the system performance and the power saving are well balanced. It was difficult to do. In particular, in the CPU sleep control, in response to the occurrence of the wake event, the CPU performance is immediately returned to the high performance state before the transition to the sleep state, and wasteful power may be consumed. Further, the depth of the CPU sleep state to be shifted at the time of idling is always fixed, and it has been difficult to realize sufficient power saving.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it is possible to realize a sufficient power saving while minimizing a decrease in system performance, and to greatly extend an operation time by a battery. It is an object of the present invention to provide a possible computer system and a power saving control method thereof.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a battery-operable computer system, wherein the computer system transitions from an operating state to a sleep state when the computer system is idle. Means for increasing a processing speed of the computer system from a low level to a predetermined high level when the computer system returns from the sleep state to the operation state in response to occurrence of a predetermined wake-up event. And processing speed control means for causing the processing speed to be controlled.

It is preferable to use a CPU sleep unit for shifting the CPU of the computer system from an operation state in which the instruction can be executed to a low power consumption sleep state in which the instruction execution is stopped. Further, the processing speed control means includes the CPU
When returning from the sleep state to the operation state,
It is preferable to use CPU speed control means for increasing the operation speed of the CPU stepwise from a low level to a predetermined high level at predetermined time intervals.

In this computer system, for example, when a wake-up event occurs while the CPU is kept in the sleep state, the operation speed of the CPU is not immediately restored to the operation speed before the transition to the sleep state. , From a low level to a predetermined high level. As a result, the processing speed of the system is gradually increased, and power consumption can be reduced as compared with a case where the processing speed is immediately returned to the processing speed before the transition to the sleep state. Further, there is no delay in the return timing itself to the operation state. Therefore, even if, for example, the user operates the keyboard or the mouse during the sleep state, it is possible to immediately execute the corresponding process. After a certain period, the system processing performance returns to the original performance. For this reason, excessive C
As long as processing involving a PU load is not suddenly requested, there is no problem such as a decrease in the perceived speed of the user. Therefore, a sufficient power saving can be realized while minimizing the deterioration of the system performance, and the operation time by the battery can be greatly extended.

Further, according to the present invention, the operation rate of the computer system is determined based on a ratio between an idle period in which the CPU is maintained in a sleep state and a wake period in which the CPU is maintained in an operation state. Operating rate detecting means for detecting whether or not the operating rate is equal to or less than a threshold value, wherein the stepwise operating speed control processing by the CPU speed controlling means is performed when the operating rate of the computer system is equal to or less than a predetermined threshold value. The execution is permitted when it is detected that there is something.

This makes it possible to execute the above-mentioned stepwise operation speed control processing only when the system operation rate is relatively low, and to maintain a better balance between system performance and power saving. .

[0017] The CPU speed control means may be configured to perform a control based on duty control information set in a predetermined register.
The duty ratio of the stop clock signal for controlling the clock of the CPU is variably set in a plurality of stages, and
CPU throttling control means for supplying to the PU; means for generating an interrupt signal indicating a request for updating the duty control information to the CPU at predetermined time intervals;
Preferably, the duty control information is updated every time the interrupt signal is generated so that the operating speed of U is gradually increased from a low level to a predetermined high level.

As described above, by using the hardware interrupt signal to the CPU to gradually increase the performance of the CPU in the operating state, the CPU performance can be efficiently reduced without affecting the OS or application being executed. It is possible to raise it step by step.

[0019] Further, the CPU has a first sleep state,
In the case of having the second sleep state with lower power consumption than the first sleep state, the CPU sleep means is allowed to shift the state of the computer system to the second sleep state. Means for determining whether or not a predetermined condition is satisfied; and when the condition is satisfied, the CPU is shifted to the second sleep state; and when the condition is not satisfied, the CPU is switched to the first sleep state.
Means for shifting to a sleep state.

As described above, by selecting the sleep state to be shifted according to the state of the computer system,
A more appropriate sleep state can be selected. Further, the first sleep state is a state in which the CPU can maintain cache coherency, and the second sleep state is a state in which the CPU cannot maintain cache coherence. Is in a state of
Whether or not a device other than the CPU is operating as a bus master in the computer system can be used as a predetermined condition under which the transition to the second sleep state is permitted. As described above, by shifting to the second sleep state on condition that there is no device performing the bus master operation, rewriting of the main memory by the device performing the bus master causes inconsistency between the main memory and the CPU cache. Can be prevented.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention. This computer system is a notebook-type personal computer (PC) that can be driven by a battery.
When external power is supplied through the adapter 181, the external power supply operates and the battery 1
82 is charged. On the other hand, when the AC adapter 181 is not connected to the PC main body, such as when used in a mobile environment, the PC operates on the power from the battery 182.

As shown, a processor bus 1, a PCI bus 2, an ISA bus 3, a CPU 1
1, host-PCI bridge 12, main memory 13, display controller 14, PCI-ISA bridge 15, I /
An O controller 16, a BIOS-ROM 17, a power controller 18, an LCD brightness control logic 19, and the like are provided.

As the CPU 11, for example, a microprocessor "Pe" manufactured and sold by Intel Corporation of the United States is used.
The CPU 11 has a built-in PLL circuit, which is connected to an external clock CL.
Based on K, an internal clock CLK2 equal to or faster than the external clock CLK is generated. This C
The PU 11 is configured so that its clock state is controlled by the stop clock signal STPCLK #.
Clock states, namely the normal state (N
normal State, Stop Grant State, and Stop Clock State
e).

The normal state is a normal operation state of the CPU 11, and an instruction is executed in this normal state. This normal state is the state that consumes the most power, and its current consumption is about 700 mA.

The stop clock state consumes the least amount of power, and its current consumption is about 30 μA. In this stop clock state, not only the execution of the instruction is stopped, but also the external clock CLK and the internal clock CLK2 are stopped.

The stop grant state is an operation state intermediate between the normal state and the stop clock state, and its current consumption is relatively small, about 20 to 55 mA. In the stop grant state, no instruction is executed. The external clock CLK and the internal clock CLK2 are both in a running state,
Internal clock CLK2 to internal logic (CPU core)
Supply is forbidden. This stop grant state is a state in which the external clock CLK can be stopped. In this stop grant state, the external clock CLK is stopped.
Is stopped, the CPU 11 shifts from the stop grant state to the stop clock state.

The transition between the normal state and the stop grant state is performed by a stop clock (STPCLK #).
It can be performed at high speed by a signal. That is, the STPC supplied to the CPU 11 in the normal state
When the LK # signal is enabled, that is, set to the active state, the CPU 11 empties the internal pipeline after executing the currently executed instruction without executing the next instruction, and then executes the stop grant cycle. Execute and shift from the normal state to the stop grant state. On the other hand, when the STPCLK # signal is disabled or set to the inactive state in the stop grant state, the CPU 11 shifts from the stop grant state to the normal state and resumes execution of the next instruction.

The transition from the stop grant state to the stop clock state is performed by the external clock CLK.
Is done instantly by stopping. The external clock CL to the CPU 11 in the stop clock state
When the supply of K is restarted, the CPU 11 shifts to the stop grant state after 1 ms. As described above, there is a problem that it takes time to return from the stop clock state.

As described above, the stop grant state has much lower power than the normal state,
In addition, it has a feature that it can be returned to a normal state, that is, an instruction execution state at a high speed by the STPCLK # signal.

For this reason, in this system, the CPU throttling control function for controlling the CPU operating speed in multiple stages is realized by periodically switching between the stop grant state and the normal state by the STPCLK # signal. In this case, depending on the duty ratio between the stop grant state and the normal state,
CPU performance is determined.

The CPU 11 has the above-described four CPU power states C0 to C3 defined by the ACPI specification by the functions of the CPU 11 and the host-PCI bridge 12.

The power state C0 is a state used as a normal operation state (wake state) for executing an instruction. CPU that controls CPU operation speed in multiple stages
The throttling control function is executed in the power state C0.

The power states C1 to C3 are used to set the CPU 11 to a sleep state during idle time, and have different latencies until returning to the C0 state and sleep depths. C
The power consumption decreases in the order of 1, C2, and C3, and the latency until returning to the C0 state increases in the order of C1, C2, and C3. No instruction is executed in C1, C2, and C3.

In C2, the cache coherency is maintained by the bus snoop operation, but in C3, no snoop operation is performed and the cache coherency is not maintained.
CPU power state C specified in ACPI specification
The relationship between 0 to C3 and the global system states G0 to G2 is as shown in FIG.

G0 is a state where the system is operating (that is, a state where the power of the system is turned on and software is being executed). In this G0 state, the power states C0 to C3 of the CPU 11 change dynamically. Is done.

In the present embodiment, when the system idle is detected by the OS, the CPU 11 to which the CPU 11 is to be shifted is described.
As the sleep state, C2 and C3 are selectively used.

To shift from C0 to C2, a host-PC
The P_LVL2 register 122 of the I bridge 12 is used. That is, the reading of the P_LVL2 register 122 by the CPU 11 causes switching of the power state from C0 to C2. When a wake event such as a hardware interrupt (IRQ) or a CPU reset occurs in C2, the CPU power state automatically returns from C2 to C0.

The transition from C0 to C3 requires a host-PC
The P_LVL3 register 123 of the I bridge 12 is used. That is, the reading of the P_LVL3 register 123 by the CPU 11 causes the switching of the power state from C0 to C3. In addition, when shifting from C0 to C3, “1” is stored in the ARB_DIS register 124.
Is set, and the bus arbitration operation of the PCI bus 2 by the PCI arbiter 121 is disabled. As a result, a new bus access request is not permitted. When a wake event such as a hardware interrupt or a CPU reset occurs in C3, the CPU power state automatically returns from C3 to C0.

G1 is a sleep state of the entire system. In the G1 state, system states S1 to S having different power consumptions are defined. In this system, G
Reference numeral 1 is mainly used as a system state during suspend or hibernation.

G2 is in an off state, that is, a state in which execution of all software has been completed and the system has been turned off. Further, the CPU 11 of FIG. 1 has the following system management function.

That is, the CPU 11 includes a real mode, a protect mode, a virtual 86 mode, and a system management mode (SMM; System Ma) for executing programs such as an application program and an OS.
The system has an operation mode for executing a system management program dedicated to system management or power management, which is referred to as “nagement mode”.

The real mode is a mode in which a memory space of at most 1 Mbyte can be accessed, and a physical address is determined by an offset value from a base address represented by a segment register. The protect mode is a mode in which a maximum of 4 GB of memory space can be accessed per task, and a linear address is determined using an address mapping table called a descriptor table. This linear addressless is finally converted to a physical address by paging. The virtual 86 mode is a mode for operating a program configured to operate in the real mode in the protect mode, and a program in the real mode is treated as one task in the protect mode.

The system management mode (SMM) is a pseudo real mode. In this mode, the descriptor table is not referred to and paging is not executed. System management interrupt (SMI; System Management Interrupter)
When (rupt) is issued to the CPU 11, the operation mode of the CPU 11 is switched from the real mode, the protect mode, or the virtual 86 mode to the SMM. In the SMM, a system management program dedicated to system management or power save control is executed.

The SMI is a type of non-maskable interrupt NMI, but is the highest-priority interrupt having a higher priority than a normal NMI or maskable interrupt INTR. This SM
By issuing I, various SMI service routines prepared as a system management program can be started without depending on the application program being executed or the OS environment. In this computer system, the SMI is used for switching the CPU power state described above.

The main memory 13 stores an operating system, an application program to be processed, user data created by the application program, and the like. When the CPU 11 shifts to the SMM, the CPU status, that is, the registers and the like of the CPU 11 when the SMI is generated, are saved in the SMRAM mapped to a predetermined address space of the main memory 13 in a stack format. This SMRAM contains a BIOS-RO
Instructions for calling the M17 system management program are stored. This instruction is the first instruction to be executed when the CPU 11 enters the SMM, and the execution of this instruction transfers control to the system management program.

The display controller 14 has an image memory (V
The display data drawn on the (RAM) 141 is displayed on one or both of the LCD 142 and the external CRT 143 provided in the PC main body. This display controller 1
4 can operate as a bus master of the PCI bus 2. The brightness of the LCD 142 is determined by the LCD brightness control logic 19 that controls the brightness of the backlight of the LCD 142.
Is controlled by

The PCI-ISA bridge 15 is a bridge connecting the PCI bus 2 and the ISA bus 3, and is a PCI-ISA bridge.
It can operate as a bus master of the bus 2. The PCI-ISA bridge 15 includes an SMI generation circuit 15
1, a CPU throttling control circuit 152, a DMA controller (DMAC) 153, and the like are provided.

The SMI generation circuit 151 has the CPU 11
Generate an I signal. Causes of the generation of the SMI signal include a software SMI, an I / O trap SMI, and a power switch operation. The software SMI is generated using a down counter or the like accessible by software. That is, when the software sets a value corresponding to the time until the generation of the SMI signal in the down counter in the SMI generation circuit 151, the SMI signal is generated at the time of timeout. An I / O trap SMI is triggered by executing an IN or OUT instruction using a predetermined I / O address.

The CPU throttling control circuit 152
Using the stock lock signal STPCLK #,
For performing U throttling control, and P
Based on control information set in a register in the CI-ISA bridge 15, the performance of the CPU 11 is set to a predetermined ratio with respect to its maximum performance value. The specific configuration of the CPU throttling control circuit 152 will be described later with reference to FIG.

DMA controller (DMAC) 153
Is a device having no bus master function and the main memory 13
It performs DMA transfer between the two, and has a plurality of DMA channels.

The I / O controller 16 has an HDD 162
Bus master ID for controlling IDE devices such as
An E controller 161 is built in. Bus master ID
The E controller 161 includes the HDD 162 and the main memory 13
It can operate as a bus master for data transfer between the two. The I / O controller 16 is a PC
Various USB that can be connected to the USB port provided on the main unit
It also has the function of controlling devices.

The BIOS-ROM 17 stores the system BIOS.
This is for storing S (Basic I / O System), and is constituted by a flash memory so that a program can be rewritten. The system BIOS is
It is configured to operate in the real mode. This system BIOS includes an I / O executed at system boot time.
An RT routine, a device driver for controlling various I / O devices, and a system management program are included. The system management program is a program (SM-BIOS) executed in the SMM,
It performs throttling control, CPU power state switching control, LCD brightness control, and the like.

The power controller 18 controls the power on / off of the PC, and turns on / off the power switch 183, the remaining capacity of the battery 182,
It has a status monitoring function such as connection / non-connection of the adapter 181 and ON / OFF of a display panel open / close detection switch.

FIG. 2 shows an example of a specific configuration of the CPU throttling control circuit 152. The CPU throttling control circuit 152 includes a stop clock control circuit 21 for controlling the generation of STPCLK #, an STPC
A stop clock interval timer 22 for controlling the generation interval of the LK #, a stop clock hold timer 23 for controlling a period for keeping the CPU 11 in the stop grant state, and a register group 24 programmable by the CPU 11 are provided. In the register group 24, a control flag for setting validity / invalidity of CPU throttling control and duty control information for specifying a CPU throttling level are set.

Hereinafter, the CPU throttling control operation in which the stop grant state and the normal state are alternately repeated at certain time intervals will be described with reference to FIG. When the stop clock interval time (duty width) is set in the register group 126, the stop clock interval timer 22 periodically generates a timeout output for each time. In response to the timeout output, the stop clock control circuit 21
LK # is set to the active state. Further, the stop clock hold timer 23 sets the register group 126 after the STPCLK # is set to the active state.
A timeout output is generated when the hold time (clock-off time) set in has elapsed. In response to the timeout output, the stop clock control circuit 2
1 returns STPCLK # to the inactive state.

When STPCLK # is set to the active state, the CPU 11 executes a grant cycle and then shifts from the normal state to the stop grant state. The stop grant state is maintained until STPCLK # is returned to the inactive state.

Therefore, the CPU 11 alternately repeats the stop grant state and the normal state at a certain time interval, so that the average operation speed is lower than that at the maximum speed when throttling control is not performed. In this case, the rate of decrease in operating speed is determined by the ratio between the stop clock interval time and the hold time given by the duty control information (duty width, clock off time). Therefore, by setting the duty ratio of STPCLK variably as shown in FIG. 4 according to the duty control information, it is possible to variably set the performance (operating rate) of the CPU in multiple stages.

Next, the principle of the power save control method used in this embodiment will be described. In the present embodiment, the following power saving function is provided. (1) Power Save 1 When the system is performing only processing for a certain time or more and a certain amount or less (while the system operating rate is low), when the CPU 11 is returned from the sleep state to the wake state, it is stepwise. Power saving is performed by raising the CPU throttling level from a lower one to a higher one at regular intervals (slow recovery).

Here, a method of judging that “the state where the system operating rate is low continues” will be described with reference to FIG. (Measurement of sleep time t1) The CPU power state is
When the idle request from the OS is issued, the state is shifted from the wake state (C0) to the sleep state (C2 or C3), and the state returns to the wake state (C0) when a wake event such as an interrupt occurs.

The timer is read before entering the sleep state, and the timer is read again after exiting from the sleep state. Then, the sleep time t1 is obtained from the difference. Here, as the timer, a timer that continues the count operation while the system is maintained in the G0 state, for example, a PM timer defined by the ACPI specification may be used.
This timer is either the host-PCI bridge 12 or the PCI
-Provided in the ISA bridge 15.

(Measurement of Wake Time t2) When exiting from the sleep state, the timer is read, and before the sleep state is entered again, the timer is read. The wake time t2 is obtained from the difference.

(Measurement of low system operation rate duration time t3) t3 is a certain value (for example, a ratio of t1 / t2)
This is the time during which the state of 1/26 or less continues.
The count-up of t3 is performed by accumulating the values of t1 and t2 in which the ratio continues to be 1/26 or less.

When t3 exceeds a predetermined time (t5), it is determined that "the state where the system operation rate is low continues". That is, when t3 exceeds t5, the condition for executing the slow recovery process is satisfied, and the slow recovery process is performed from the next wake.

(Slow recovery) Hardware interrupt (IRQ) while CPU 11 is kept in the sleep state
When a wake-up event such as occurs, the operating speed of the CPU 11 (CPU operating ratio) usually immediately returns to the operating speed (CPU operating ratio) before the transition to the sleep state, as shown in FIG. However, when the condition of the slow return is satisfied, the slow return process is executed as shown in FIG. 7B, and the CPU operation speed is gradually increased at predetermined time intervals by the CPU throttling control. Is gradually raised from a low level to a predetermined high level.

As a result, as compared with the case where the operation speed of the CPU 11 is immediately returned to the operation speed before the transition to the sleep state, the amount of the CPU 1 is reduced by the hatched portion in FIG.
1 can be reduced.

It should be noted that C finally returned in the slow return process
The PU performance is up to the performance before shifting to the sleep state.
As shown in (2), when the state shifts from a state in which the CPU operates at a performance of 50% to a sleep state depending on conditions such as the remaining capacity of the battery and the CPU temperature, the state is finally returned by the slow recovery process. Is CPU utilization = 50
% Performance.

Even when such a slow recovery process is performed, the wake timing itself to C0 is not delayed. Therefore, even when the user operates the keyboard or the mouse during the sleep state, for example, the processing corresponding to the operation can be immediately started. After a certain period of time, the CPU performance returns to the performance set before entering the sleep state. For this reason, unless a process involving an excessive CPU load is suddenly requested, there is no problem such as a decrease in the perceived speed of the user. Therefore, a sufficient power saving can be realized while minimizing the deterioration of the system performance, and the operation time by the battery can be greatly extended.

Note that the measurement of t1 and t2 is continued even after the slow return condition is satisfied. If the ratio between t1 and t2 is greater than 1/26, clear t3,
Thereafter, until the accumulated value of t3 exceeds t5 again, the slow return process is not executed.

(2) Power Save 2 When the system is not performing a specific process (bus master operation by DMAC or bus master IDE), the CPU state to enter the idle state is transferred to C3 instead of C2 to save power. Make a save.

That is, at the time of idling, it is determined whether or not the system state at that time satisfies the condition for shifting to C3. If the transition condition is satisfied, the state shifts to the deeper sleep state C3 (deep sleep). If the transition condition is not satisfied, the state shifts to the sleep state C2 (quick start) capable of returning to C0 at high speed.

The condition for shifting to C3 is as follows.
The other device is not operating as a bus master. As described above, since the snoop operation for maintaining the consistency between the CPU cache and the main memory 13 is not performed in C3, if there is a device that is operating as a bus master, the device that operates as a bus master is not used. This is because rewriting of the main memory 13 may cause inconsistency between the main memory 13 and the CPU cache.

(3) Power Save 3 When the remaining battery power falls below a certain standard, the CPU throttling is made more effective (throttling level is lowered), so that the CPU in the wake state is turned off.
Reduce power and save power.

(4) Power Save 4 When the remaining battery power falls below a certain reference, power saving is performed by lowering the brightness of the LCD.

FIG. 9 shows the flow from the detection of system idle by the OS to the execution of CPU sleep control by the SM-BIOS. OS
When there are no more tasks to be executed by the CPU 11,
It detects that it is in the system idle state (CPU idle) and issues an idle request to the system BIOS (or SM-BIOS). In response to this idle request, the system BIOS (or SM-BIOS)
CPU sleep control for shifting the CPU 11 from the wake state to the sleep state is started.

Next, the processing procedure by the BIOS will be described with reference to the flowchart of FIG. System BI
The OS determines whether the PC is running on a battery (step S11). This means that information indicating whether the AC adapter is connected or not is supplied to the power controller 18.
It is determined by obtaining from. If the AC adapter is not connected, the battery is being driven.

If the battery is being driven, the process proceeds to the following steps S12 to S21. That is, first,
"T" of the ratio 1/26 or less that has been accumulated so far
The time “t3” is acquired from the accumulated values of “1” and “t2” (step S12), and “t3” is set to the threshold “t”.
5 "is determined (step S1).
2). If “t3” exceeds the threshold value “t5”, it is recognized that the state where the system operation rate is low continues. In this case, first, the timer is read, and “t2” is measured from the difference from the timer value read during the previous wake (step S14). Next, in order to execute the slow recovery process at the next wake, CPU throttling control is enabled, and the throttling level is set to the lowest level (for example, 12.5
%) (Step S15). Then, CPU sleep processing for switching the CPU power state from C0 to C2 or C3 is executed (step S1).
6). The BIOS processing is interrupted at this point.

When the CPU power state is C2 or C3 and a wake event such as a hardware interrupt (IRQ) from a device in the PC occurs, the CP
The U power state automatically returns to C0. In this case, the CPU performance is returned to the minimum level (12.5%) set in step S15. And C2 or C3
The CPU 11 starts executing the instruction from the instruction following the instruction executed before the transition. As a result, the process is restarted from step S17 of the BIOS. The BIOS reads the timer and calculates “t” from the difference from the timer value read in step S14.
1 ”is measured (step S17). Next, in order to periodically update the CPU throttling level, the next B
After setting a timer value indicating the time (t4) until calling the IOS in the software SMI timer (step S1)
8) Execute a return instruction to return control to the OS.

When the software SMI requesting the change of the duty information is generated during the period when the CPU 11 is in the wake state (power state C0), the SM-BIOS slow recovery processing routine is started. As shown in FIG. 11, the slow return processing routine increases the CPU throttling level by +1 level by updating the duty control information (step S31). The CPU to which the CPU throttling level raised by +1 level should finally return
If it has not reached the PU throttling level (NO in step S32), the software SMI is set again (step S33). As a result, until the CPU throttling level finally reaches the CPU throttling level to be returned, the slow return processing routine is periodically called by the software SMI.

Returning to FIG. 10, at step S13, "t
If “3” is equal to or smaller than the threshold “t5”, that is, if the condition for executing the slow recovery is not satisfied, step S1
9, S20 and S21 are executed. Step S19, S
Steps S20, S21 correspond to steps S14, S16, S17 described above.
Respectively. That is, the aforementioned step S
15 and step S18 are skipped. In this case, a normal return process is performed.

If it is detected in step S11 that AC driving is being performed (NO in step S11),
Only the CPU sleep processing (step S22) is executed. Note that even during the AC drive, “t1”, “t2”
May be measured.

Next, referring to the flowchart of FIG. 12, the CP executed in steps S16, S20, S22
The procedure of the U sleep process will be described. In the CPU sleep process, first, the current system state, that is, whether or not the DMA channel is set, whether or not the bus master IDE is active, whether or not a bus master request is generated, and the like are set. Each value is checked with reference to the value of the register used for this (step S4).
1) It is determined whether or not the condition for shifting to C3 is satisfied based on whether or not a device other than the CPU 11 is operating as a bus master (step S42). It should be noted that the condition may be added that a battery is driven, a USB device is not connected, and the like. In this case, the process of determining whether or not the transition condition is satisfied is performed in step S in FIG.
This is performed in steps S51 to S55.

If it is determined in step S4 of FIG. 12 that the condition for shifting to C3 is satisfied, the CPU power state is switched from C0 to C3 (step S4).
3). In this case, bus arbitration is also prohibited as described above. On the other hand, if the condition for shifting to C3 is not satisfied, the CPU power state is switched from C0 to C2 (step S44).

As described above, by dynamically switching the sleep state according to the system state under the control of the BIOS, it is possible to realize the optimum power saving even in an environment without the ACPI-OS.

The presence or absence of the bus master operation can also be checked by checking whether a specific driver is operating. Further, in addition to the condition for shifting to C3, the fact that the state where the system operation rate is low is added to the condition for shifting to C3.
It may be determined whether or not another condition for shifting to is satisfied.

Furthermore, the slow return processing of the present invention, which gradually raises the system performance from a low level to a high level, does not immediately return the system performance to the original state.
Since it is important to save power by returning the power stepwise, not only control for increasing the CPU speed stepwise, but also, for example, power state control of each device other than the CPU and intermittent supply of clocks Even if control is performed to increase the average operation speed of those devices step by step, intermittent control of cache validity / invalidity, intermittent control of HDD motor on / off, etc. good.

Further, not only when an idle request is received from the OS, but also when no key input is made for a certain period or more, it may be determined that the system is idle and the above-described CPU sleep control may be performed.

[0087]

As described above, according to the present invention,
Sufficient power saving can be realized while minimizing the deterioration of the system performance, and the operating time by the battery can be greatly extended.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary block diagram showing a configuration of a CPU throttling control circuit provided in the computer system of the embodiment.

FIG. 3 is a timing chart for explaining a CPU throttling control operation used in the embodiment.

FIG. 4 is a diagram showing the duty and CP of the stop clock signal used in the CPU throttling control operation of the embodiment.
The figure which shows the relationship with U performance.

FIG. 5 is a state transition diagram for explaining a CPU power state used in the embodiment.

FIG. 6 is an exemplary view for explaining the principle of a system operation rate determination process in the embodiment.

FIG. 7 is an exemplary view for explaining the principle of a slow recovery process used in the embodiment;

FIG. 8 is another view for explaining the principle of the slow return process used in the embodiment.

FIG. 9 is an exemplary view for explaining the flow from the detection of system idle by the OS to the execution of CPU sleep control by the BIOS in the embodiment.

FIG. 10 is an exemplary flowchart illustrating the procedure of a CPU power save process executed by the BIOS in the embodiment.

FIG. 11 is an exemplary flowchart illustrating the procedure of a slow recovery process executed by the BIOS in the embodiment.

FIG. 12 is an exemplary flowchart illustrating the procedure of CPU sleep processing executed by the BIOS in the embodiment.

FIG. 13 is a flowchart illustrating an example of a transition condition determination process to a C3 state executed in the CPU sleep process of FIG. 12;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... CPU 12 ... Host-PCI bridge 13 ... Main memory 15 ... PCI-ISA bridge 17 ... BIOS-ROM 121 ... PCI arbiter 151 ... SMI generation circuit 152 ... CPU throttling control circuit 153 ... DMA controller 21 ... Stop clock control circuit 22: Stop clock interval timer 23: Stop clock hold timer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B011 DA02 EA04 LL08 LL10 LL11 5B062 AA05 DD05 HH02 HH06 HH07 JJ10 5B079 BA01 BB02 BC01 DD02 DD20

Claims (11)

[Claims] 1. A battery-powered computer system, comprising: a sleep unit for causing the computer system to transition from an operating state to a sleep state when the computer system is idle; and a computer responsive to a predetermined wake-up event A computer system comprising: a processing speed control means for stepwise increasing a processing speed of the computer system from a low level to a predetermined high level when the system returns from the sleep state to the operation state. . 2. The CPU according to claim 2, wherein the sleep unit includes a CPU sleep unit that shifts a CPU of the computer system from an operation state in which instructions can be executed to a low power consumption sleep state in which instruction execution is stopped. The means includes CPU speed control means for increasing the operation speed of the CPU stepwise from a low level to a predetermined high level at predetermined time intervals when the CPU returns from the sleep state to the operation state, Based on a ratio between an idle period in which the CPU is kept in a sleep state and a wake period in which the CPU is kept in an operation state, whether or not the operation rate of the computer system is equal to or less than a predetermined threshold value Operating rate detecting means for detecting the step-by-step operating speed control processing by the CPU speed control means. 2. The computer system according to claim 1, wherein execution of the computer system is permitted when it is detected that the operation rate of the computer system is lower than a predetermined threshold. 3. The CPU according to claim 1, wherein the sleep unit includes a CPU sleep unit that shifts a CPU of the computer system from an operation state in which instructions can be executed to a low power consumption sleep state in which instruction execution is stopped. The means includes CPU speed control means for increasing the operation speed of the CPU stepwise from a low level to a predetermined high level at predetermined time intervals when the CPU returns from the sleep state to the operation state, The CPU speed control means variably sets a duty ratio of a stop clock signal for controlling a clock of the CPU in a plurality of steps based on duty control information set in a predetermined register, and supplies the duty ratio to the CPU. Throttling control means, and an interrupt signal indicating a request for updating the duty control information Means for generating the CPU at intervals, and updating the duty control information each time the interrupt signal is generated such that the operation speed of the CPU is stepwise increased from a low level to a predetermined high level. 2. The computer system according to claim 1, further comprising means. 4. The CPU according to claim 1, wherein the sleep unit includes a CPU sleep unit that shifts a CPU of the computer system from an operation state in which an instruction can be executed to a low power consumption sleep state in which instruction execution is stopped. The means includes CPU speed control means for increasing the operation speed of the CPU stepwise from a low level to a predetermined high level at predetermined time intervals when the CPU returns from the sleep state to the operation state, The CPU has a first sleep state and a second sleep state that consumes lower power than the first sleep state. The CPU sleep unit is configured to switch the state of the computer system to the second sleep state. Means for determining whether or not a predetermined condition for permitting a transition to a sleep state is satisfied; and The PU is shifted to the second sleep state, the computer system according to claim 1, characterized in that it comprises and means for shifting said CPU to said first sleep state when said condition is not satisfied. 5. The CPU according to claim 1, wherein the first sleep state is set to the CPU.
Is a state in which the coherency of the cache can be maintained, the second sleep state is a state in which the CPU cannot maintain the coherency of the cache, and the CPU sleep means is In the computer system, it is determined whether or not a predetermined condition for permitting the transition to the second sleep state is satisfied based on whether or not a device other than the CPU operates as a bus master. The computer system according to claim 4, wherein: 6. A computer system capable of being driven by a battery, wherein a first sleep state in which instruction execution is stopped, and a second sleep state in which instruction execution is stopped and which consumes less power than the first sleep state. When the computer system is idle, the CPU
From the operating state in which the instruction can be executed,
CPU sleep means for shifting to any one of the sleep states of the above, wherein the CPU sleep means includes a predetermined condition that the state of the computer system is allowed to shift to the second sleep state. Means for determining whether or not the condition is satisfied; and when the condition is satisfied, the CPU
Means for shifting to the first sleep state when the condition is not satisfied. 7. The CPU according to claim 1, wherein the first sleep state is the CPU
Is a state in which the coherency of the cache can be maintained, the second sleep state is a state in which the CPU cannot maintain the coherency of the cache, and the CPU sleep means is In the computer system, it is determined whether or not a predetermined condition for permitting the transition to the second sleep state is satisfied based on whether or not a device other than the CPU operates as a bus master. The computer system according to claim 6, wherein: 8. A power saving control method for a computer system, comprising: when the computer system is idle, transitioning the computer system from an operating state to a sleep state; and responding to the occurrence of a predetermined wake-up event. When the computer system returns from the sleep state to the operation state, gradually increasing the processing speed of the computer system from a low level to a predetermined high level. Method. 9. The step of causing the computer system to transition from an operation state to a sleep state includes causing the CPU of the computer system to transition from an operation state capable of executing instructions to a low power consumption sleep state in which instruction execution is stopped. And the step of increasing the processing speed step by step comprises:
When the PU returns from the sleep state to the operation state, the operation speed of the CPU is gradually increased from a low level to a predetermined high level at predetermined time intervals, and the CPU is maintained in the sleep state. Detecting whether the operation rate of the computer system is equal to or less than a predetermined threshold based on a ratio between the idle period being set and a wake period during which the CPU is kept operating. When it is detected that the operation rate of the computer system is equal to or less than a predetermined threshold value, the operation speed of the CPU is increased stepwise from a low level to a predetermined high level at predetermined time intervals. The power save control method according to claim 8, wherein: 10. A computer comprising a CPU having a first sleep state in which instruction execution is stopped, and a second sleep state in which instruction execution is stopped and consuming less power than the first sleep state. A power saving control method for a system, comprising: determining whether a state of the computer system satisfies a predetermined condition that allows a transition to the second sleep state when the computer system is idle. When the condition is satisfied, the CPU shifts from the operation state in which the instruction can be executed to the second sleep state; and when the condition is not satisfied, the CPU is changed from the operation state to the first sleep state. A power save control method characterized by shifting to (1). 11. The method according to claim 11, wherein the first sleep state is the CP.
U is in a state where it is possible to maintain cache coherency, and the second sleep state is a state in which the CPU is unable to maintain cache coherence. Determining whether or not a predetermined condition for permitting the transition to the second sleep state is satisfied, based on whether or not another device other than the device performs a bus master operation. A power save control method according to claim 10.