JP2000172236A - Drive device and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving device of an MLA driving method suppressing an increase in the circuit scale in the case of being integrated by keeping an increase of the current consumption suppressed with the circuit configuration optimized. SOLUTION: A driving device 301 of a liquid crystal device 10 comprises a controller 1, a memory 2, a row selection pattern generating circuit 7, a row voltage generating circuit 9, a latch circuit 6B, a column voltage generating circuit 11, an arithmetic circuit 51 (a line buffer 3, a comparator circuit 4, adding circuits 5A, 5B, a latch circuit 6A, a virtual data generating circuit 8). And the device adopts an expanded orthogonal matrix B of six simultaneous selection rows, two virtual rows, and four row orthogonal matrix A as a row selection pattern, and calculates column output voltages in units of A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device and a liquid crystal display device suitable for a simple matrix type liquid crystal display device driven by a simultaneous selection driving method for a plurality of lines.

[0002]

2. Description of the Related Art Conventionally, as a driving method of a simple matrix liquid crystal display device, a driving method based on a so-called line-sequential driving method (conventional example 1), a multiple line simultaneous selection driving method for simultaneously selecting row electrodes, or And a driving method called a multi-line addressing driving method (hereinafter, referred to as an MLA driving method) (conventional example 2).

In the prior art 1, a scanning voltage is sequentially applied to one row electrode, and a column control voltage is applied to a plurality of column electrodes at the same time to apply a brightness control voltage to each row electrode. It is a driving method. Then, the display dots are controlled to have a transmittance corresponding to an average effective value voltage during a period of time (hereinafter, referred to as one frame period) until voltage application to all row electrodes is completed once. A predetermined image can be displayed every frame period.

In Conventional Example 2, all the row electrodes constituting a display screen are divided into a plurality of simultaneously selected groups, and a scanning voltage is simultaneously applied to each of the row electrodes in the simultaneously selected group. Also, by applying a column voltage to a plurality of column electrodes simultaneously with the application of the scanning voltage, a selection voltage is simultaneously applied to a plurality of liquid crystal pixels to which the same column voltage is applied. Is repeated at least as many times as the number of the simultaneously selected row electrodes.

Thus, the display dots are controlled to have a transmittance corresponding to the average effective value voltage applied per time (one frame period) until the repetition is completed.
One display image is formed for each one frame period.

In the second conventional example, the column voltage applied to each column electrode is obtained by performing a matrix operation on display data corresponding to a plurality of row electrodes selected at the same time and a scanning voltage applied at the time of the simultaneous selection. , A voltage obtained by multiplying the determined value by the “unit column voltage” is applied.

[0007] The maximum value of the magnification determined by the matrix operation is limited by the determinant of the scanning voltage used in the matrix operation. At most, it is equal to or less than the larger of the number of rows and the number of columns of the determinant. Conventional example 2
For example, JP-A-6-27907, US52
62881 and JP-A-8-234164.

Incidentally, such a liquid crystal display device is used as a display device for a man-machine interface with the development of a highly information-oriented society. In recent years, it is widely used not only for desktop PCs but also for so-called notebook PCs, PDAs (Personal Digital Assistants), mobile phones, etc. that are suitable for portable use by taking advantage of their lightweight and thin characteristics. ing. As a result, in the development of liquid crystal display devices, while improvements have been made to larger screens, improvements to lighter weight and lower power consumption have also been made.

Therefore, in such a liquid crystal display device,
Various devices have been adopted to reduce power consumption. As a specific example, there is a device that enables the liquid crystal display device to respond with a low effective value voltage, and a device that employs a reflective liquid crystal display device that does not require a backlight.

[0010] As a third conventional example, a document "General-purpose addressing technology of an effective value response liquid crystal display device," SID, 1988, which reported the relationship between the MLA driving method and power consumption.
Conference Report, pp. 80-85 ". The condition shown in the conventional example 3 is “L = ΔM (where M is the total number of row electrodes on the display screen, L is the number of simultaneously selected rows)”, and the effective value voltage at the time of ON display and OFF The optimum bias ratio (B _best = maximum column voltage / scanning voltage = VC / VR) at which the ratio with the effective value voltage at the time of display is maximized. It has been reported that the MLA driving under this condition can reduce the driving voltage of the entire liquid crystal display device as compared with the line sequential driving method.

Further, in Japanese Patent Application No. 9-277650, L
When the MLA driving is performed under conditions other than the optimum bias ratio at ≠ √M, the ratio between the effective value voltage at the time of ON display and the effective value voltage at the time of OFF display does not become the maximum. However, a lower supply voltage can be provided. In a multiplex drive up to a duty ratio of about 1/80, the drive circuit can be integrated by a process for a 5 V standard logic IC as a semiconductor process, and not only low power consumption but also cost can be reduced. (Conventional Example 4). On the other hand, as a device for reducing power consumption by a circuit configuration, there is a method based on parallel processing by lowering a clock frequency.

Next, the operation of the conventional example 1 will be described with reference to FIGS. FIG. 7 is a block diagram of a controller-equipped driving device 201 for driving a matrix liquid crystal display element of “64 rows × 132 columns” dots.

The memory 2 has a built-in display data RAM,
One dot of the built-in RAM corresponds to one dot of the liquid crystal panel 10 on a one-to-one basis. The memory 2 decodes a row address signal from the controller 1, outputs one row of data corresponding to the address in parallel, and latches the data in a line buffer 3 in synchronization with a clock.

The column voltage generating circuit 11 has a line buffer 3
From the display data and the signal for converting the liquid crystal sent from the controller 1, that is, the polarity inversion signal, are decoded, and "V0, V2,
An appropriate column voltage from the levels of “V3, V5” is output to the liquid crystal panel 10 in synchronization with the clock.

The row voltage generating circuit 9 sequentially selects a selected row in a shift register format in synchronization with a clock, decodes a polarity inversion signal and a value of a register indicating selection or non-selection, and outputs "V0, V1" through a level shifter. , V4,
An appropriate row voltage is output to the liquid crystal panel 10 from among "V5". Here, when the row voltage generation circuit 9 selects the nth row, the column voltage generation circuit 11 is synchronized so as to output data corresponding to the nth row of the display RAM from the column voltage.

FIG. 11 shows an example of a drive waveform when driven in this manner. After the change of the polarity inversion signal, both the row output and the column output are synchronized at the center of the “V2, V3” level in synchronization with the clock. As described above, under the condition of a multiplex drive and a low duty ratio, a method of processing all column signal data in parallel is used.

Next, the operation of the conventional example 2 will be described with reference to FIGS. FIG. 8 is a block diagram of a controller-equipped driving device 202 which is a matrix type liquid crystal display element of “64 rows × 132 columns” dots, and has a simultaneous selection of driving rows a and virtual rows b. FIG. 10 shows the operation timing of each circuit. The memory 2 decodes a row address signal from the controller 1 in the same manner as the line sequential driving method, outputs one row of data in parallel, and latches the data in the line buffer 3 in synchronization with the clock CL1.

The address value from the controller 1 is CL
The data is incremented in synchronization with 1, and the same operation is repeated a times to hold data for a row in the line buffer 3. D1, D2,... Da shown in FIG. 10 are the first line, the second line,.
3 shows the latched data. At the same time as the data for a row is accumulated, a predetermined operation is performed on the row selection pattern signal sent from the row selection pattern generation circuit 7, and the operation result is latched by the latch circuit 6 in synchronization with the clock CL2. The operation period, the latch data and the timing relationship between CL1 and CL2 are as shown in FIG.

Here, the arithmetic circuit calculates the data for row a output from the line buffer 3, the virtual data for row b output from the virtual data generation circuit 8, and the row selection pattern for (a + b) rows, as shown in FIG. As shown in (1), the exclusive OR of each bit is calculated, and the (a + b) output is added.

This operation is performed in parallel on 132 column signals. The operation result output from the latch circuit 6 is sent to the column voltage generation circuit 11. The c-bit data sent to the column voltage generation circuit 11 is output as a column voltage via a decoder and a level shifter. Here, the c bits of the operation result are normally (a + b) In the case of an input addition circuit, the output value is (a + b) of 0, 1, 2,..., (A + b).
+1) values are conceivable, and the corresponding bits are obtained.

However, by appropriately selecting the virtual data, the number of output values can be reduced. Hereinafter, a method of adjusting operation bits by virtual data and the virtual data generating circuit 8 will be described by taking as an example a case where the number of simultaneously selected rows is 5 and the number of virtual rows is 3.

FIG. 5 shows an “8 × 8” Hadamard matrix. The upper 5 bits are used as a matrix for the actually selected row, and the lower 3 bits are used as a matrix for the virtual row. Here, a 5-row simultaneous selection driving method without a virtual row is considered. For example, in the case of the data shown in FIG. 12, the exclusive OR of each bit with the “5 × 8” matrix is taken, and the added value is “0, 2, 2, 2, 1,.
3, 3, 3 ".

In the case of the data shown in FIG.
2, 2, 2, 5, 3, 3, 3 ”, and considering all other data, possible values are“ 0, 1, 2, 3, 4,
5 ". That is, there are six column output levels.

Here, in the sixth row of the data in FIG.
Assuming that 0 is on the line and 0 is on the 8th line, “8 × 8” in FIG.
Performs a similar operation with a matrix. Then, the output of each column is “2, 4, 2, 4, 2, 4, 6, 4”. Also, in the case of FIG. 13, assuming 0 in the sixth row, 0 in the seventh row, and 1 in the eighth row, if the same calculation is performed, the output value becomes “6,
4, 4, 2, 6, 4, 4, 6 ".

Assuming that these are appropriate virtual data for all 6-bit data, the output value is "2, 4, 6".
It can be seen that they can be aggregated in three ways. This can be considered as follows.

As described above, there are six output values "0, 1, 2, 3, 4, 5" when there is no virtual row. But,
The output value is set to “0, + 1,
+2 or +3 ”. Therefore, if the output value when there is no virtual row is 0, "2"
In the case of 1, "2" or "4", in the case of 2, "2" or "4", in the case of 3, "4" or "6"
In the case of 4, it can be changed to "4" or "6", and in the case of 5, it can be changed to "6". As a result, they are collected in three ways, "2, 4, 6".

Based on these rules, the virtual data generating circuit 8 can appropriately determine virtual data by using an a-bit decoder or a look-up table. In this way, the data output from the virtual data generating circuit 8 allows the output of the adding circuit 5 to reduce the number of effective bits. The row voltage generation circuit 9 decodes the row selection signal output from the row selection signal generation circuit, and applies a row voltage to a selected rows sequentially selected in a shift register format. The output timing of the row voltage and the column voltage is as shown in FIG.

[0028]

However, the driving device for setting and driving a virtual row in the technique of the prior art 2 is composed of the above-described circuit blocks, and thus has the following problems. That is, when the column signals are processed in parallel, the conventional example 1
As compared with the driving device of the line sequential driving method, a column voltage operation circuit, a line buffer, and a virtual data generation circuit are required, the circuit scale is increased, and the chip area is increased. Even if a single-chip LSI is to be manufactured, the cost increases as a result, although a process for a 5V standard logic IC can be used as a semiconductor process.

When the clock speed is increased in order to suppress an increase in the circuit scale, the current consumption increases. Therefore, there is a trade-off between the circuit scale and the current consumption. The present invention is a driving device for performing an MLA driving method,
The present invention proposes a drive device that optimizes the circuit configuration and suppresses an increase in circuit scale when integrated, while suppressing an increase in current consumption.

[0030]

Means for Solving the Problems That is, claim 1 is as follows.
Virtual data generating means, row electrode driving means, column electrode driving means, memory means for storing display data, calculating means for calculating a column output voltage, and row selection pattern generating means for outputting a row selection pattern. And a liquid crystal display element in which row electrodes and column electrodes are arranged in a matrix.
m (k is an integer of 2 or more, m is an integer of 1 or more) simultaneously selected driving rows and k · n (n is an integer of 1 or more) virtual rows are set and driven by a multiple row simultaneous selection method. In the driving device, a driving device is characterized in that a matrix B obtained by expanding a matrix A of (m + n) rows whose row vectors are orthogonal to each other is used as a row selection pattern, and a column output voltage is calculated in A units.

[0031] Further, the present invention provides a row electrode driving means, a column electrode driving means, a memory means for storing display data, a calculating means for calculating a column output voltage, and a row selection pattern for outputting a row selection pattern. Generating means, and set up km · m (k is an integer of 2 or more, m is an integer of 1 or more) simultaneously selected driving rows for a liquid crystal display element in which row electrodes and column electrodes are arranged in a matrix. Then, in a driving device driven by the multiple-row simultaneous selection method, a matrix B obtained by expanding a matrix A in which row vectors are orthogonal to each other (m rows + 1 virtual rows) is used as a row selection pattern, and a column output voltage is calculated in units of A. A driving device is provided.

The third aspect of the present invention provides the driving device according to the first or second aspect, wherein a matrix B in which the row vectors of the equation (1) are orthogonal to each other is used. However, in equation (1),
p ₁ , p ₂ , p ₃ , and p ₄ are each 1 or −1, and p ₁ , p ₂ , p _3, and p ₄ = −1.

[0033]

(Equation 3)

According to a fourth aspect of the present invention, there is provided the driving device according to the third aspect, wherein a matrix C in which the row vectors of the equation (2) are orthogonal to each other is used. However, in equation (2), p ₅ , p
₆ , p ₇ and p ₈ are each 1 or −1, and
_{p 5 · p 6 · p 7} · p 8 = -1.

[0035]

(Equation 4)

Further, the present invention provides the above-mentioned driving device, which uses one of the rows and columns of the matrix B or the matrix C by exchanging them. In addition, the present invention provides the above-described driving device, which uses the matrix B or the matrix C with the column code reversed. Also, k = 2 and m = 3
The drive device described above is provided. Also, K = 2 and m =
The present invention provides the above-described driving device, wherein 3 and n = 1. According to a fifth aspect of the present invention, there is provided the driving device according to the first, second, third, or fourth aspect, wherein the one-chip LSI is provided. At this time, it is preferable to incorporate an oscillation circuit and a power supply circuit. A sixth aspect of the present invention provides a liquid crystal display device including the driving device according to the first, second, third, fourth, or fifth aspect and a liquid crystal display element.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. Examples 1 and 2 are the invention, and Example A
Is a comparative example.

Example 1 FIG. 1 is a block diagram showing the structure of Example 1. By simple matrix drive, "64 rows x 132
A liquid crystal panel 10 having a simple matrix liquid crystal display element of "row" dots is used. In this example, the number of simultaneously selected row electrodes is 6 (k = 2, m = 3), and the number of virtual row electrodes is 2 (k =
2, n = 1).

The driving device 301 of the liquid crystal panel 10 is an MPU
A controller 1 for controlling an interface with each other and each internal timing, a memory 2 in which display data is written, an arithmetic circuit 51 for determining a voltage to be applied to a column electrode, a pattern for determining a column voltage by operation with display data, That is, a row selection pattern generation circuit 7 for generating a row selection pattern to be applied to a row electrode, a row voltage generation circuit 9 for generating a row voltage according to the row selection pattern, and a column voltage according to the output of the arithmetic circuit 51 are generated. Column voltage generation circuit 1
1 is provided.

The arithmetic circuit 51 includes a line buffer 3,
A virtual data generation circuit 8, a comparator circuit 4, an addition circuit 5A, a latch circuit 6A, and an addition circuit 5B are provided. Further, the output of the addition circuit 5B is connected to the latch circuit 6B, and the output of the latch circuit 6B is connected to the column voltage generation circuit 1
Connected to 1.

Next, the operation of each block will be described in detail. The controller 1 is compatible with 80-system parallel, 68-system parallel, and serial MPU interfaces, and stores data sent from the interface in the memory 2. The memory 2 has a display RAM of 64 × 132 bits, and one dot of the built-in RAM corresponds to one dot of a pixel of the liquid crystal panel 10 on a one-to-one basis.

The memory 2 decodes the value of the line address signal sent from the controller 1, and sends 132 data corresponding to one line to the line buffer 3. The line address value of the controller 1 is incremented in synchronization with CL1. Line buffer 3
Row data is sent as continuous row data and latched in the line buffer 3 in synchronization with CL1. The line buffer 3 has a latch function for three rows, and holds data for three consecutive rows in a shift register format.

In this example, a latch function for three rows is provided. However, if synchronization is achieved well, a latch function for two rows may be used. Data in the third row is obtained by directly converting a signal from the memory 2 into a comparator. What is necessary is just to input to the circuit 4 and the virtual data generation circuit 8.

On the other hand, the row selection pattern generation circuit 7 generates a 4-bit row selection pattern in synchronization with CL2 sent from the controller 1. CL2 is a signal obtained by dividing the frequency of CL1 by 3 as shown in FIG. 2, and updates the row selection pattern every time data of three rows of the line buffer 3 is updated.

The row selection pattern is “8 × 8” shown in FIG.
Was used. The orthogonal matrix B is an orthogonal matrix obtained by expanding the “4 × 4” orthogonal matrix A shown in FIG. 3 as shown in FIG. The row corresponding to the fourth row of the orthogonal matrix A in FIG. 3 was defined as a virtual row electrode. The orthogonality is maintained even with such an extension. The “8 × 8” orthogonal matrix B is output in the order of upper 4 bits and lower 4 bits in the column in synchronization with CL2, and is sequentially shifted in the column direction and output.

Here, the elements “1” and “−” of the orthogonal matrix
"1" is a signal corresponding to "1" and "0" respectively as a logic signal, and as a voltage finally output to the liquid crystal panel 10, "1" is a positive selection voltage and "-1". Corresponds to a negative selection voltage.

The 4-bit row selection pattern output from the row selection pattern generation circuit 7 is sent to the row voltage generation circuit 9 and the comparator circuit 4 and, of the 4 bits, 3 bits corresponding to the actually selected row are output. It is sent to the row voltage generation circuit 9. The signal sent to the row voltage generating circuit 9 is converted into a row voltage of 6 bits, that is, two 3-bit data by a decoder and a level shifter, and is output from the selected 6 rows in synchronization with CL2.

Here, the six rows selected by the row voltage generating circuit 9 and the column voltage outputs calculated from the data corresponding to the six rows are synchronized with the output shown in FIG. Then, the timing with the column signal is adjusted. The selected row is sequentially selected for each block of 6 rows by the shift register, and the eleventh block, that is,
After selecting “lines 61, 62, 63, 64, 65, 66”, the first block, that is, “1, 2, 3, 4,.
The selection of “5th and 6th rows” is repeated.

Here, the 65th and 66th lines are not actually displayed and do not exist in the memory 2, but they are required for the calculation, so in this example, the increment of the address of the memory 2 is stopped. , The data of the 64th line
It hit the 65th and 66th lines. All the blocks have been selected once for each of the eight columns of the orthogonal matrix B, resulting in one frame.

On the other hand, the row selection pattern sent to the comparator circuit 4 includes the data for three rows of the line buffer 3 and the data for one row sent from the virtual data generation circuit 8 for a total of four rows. Is performed for 132 columns, that is, 4 × 13
An operation with 2-bit data is performed.

The virtual data generation circuit 8 generates one row of virtual data from three rows of data, and comprises a 3-bit decoder. This virtual data generation circuit 8 serves to reduce the column voltage level as described above. For example, in the case of simultaneous selection of three rows, virtual data is determined so that only 1, 3 are taken from four column voltage levels of 0, 1, 2, and 3.

The comparator circuit 4 is composed of 4 × 132 exclusive OR circuits, and a 4-bit row selection pattern and an exclusive OR of each bit of 4 rows of data are parallelized to 132 columns of data. To process. This calculation result is sent to the addition circuit 5A. The adder circuit 5A is a 4-input adder 13
It consists of two, and adds the 4-bit output value of the comparator circuit 4.

There are five possible addition values, "0, 1, 2, 3, 4". As described above, virtual data is determined so that the output value takes only "1" and "3". I have. For this reason, there are actually only two cases, and only the lower second bit of the addition output is valid. Addition circuit 5
The output of A is latched by the latch circuit 6A in synchronization with CL2. In this way, first, data of three lines out of six lines is processed.

The remaining three rows can be similarly calculated. A one-bit output is obtained from the adder circuit 5A. This output and the 1-bit data already held in the latch circuit 6A are added by the adder circuit 5B, and as a result, three 2-bit data "0, 1, 2" are latched in the latch circuit 6B. The output of the latch circuit 6B is sent to the column voltage generation circuit 11, passed through the decoder and the level shifter circuit, synchronized with the row voltage generation circuit 9 described above, and output to the liquid crystal panel 10 in synchronization with CL2.

As described above, when the orthogonal matrix A of “4 × 4” is extended to create the orthogonal matrix B of “8 × 8”, as shown in the following example A, all six lines are used. Need not be calculated in parallel. The calculation can be performed twice for every three lines. As a circuit, the number of latch circuits including line buffers is reduced from 8 × 132 to 6 × 132. The number of the comparator circuits 4 is reduced by half from 8 × 132 exclusive logic circuits to 4 × 132 circuits. The 8-bit adder circuit can be replaced with a 4-bit adder circuit and a 2-bit adder circuit, and a 6-bit decoder. Can be reduced to a 3-bit decoder. For this reason, drastic circuit reduction can be achieved for the entire driving device.

The same operation can be performed when the columns of the expanded matrix are exchanged or when the column codes are changed. When the rows are replaced, the same operation can be performed by replacing the address value at the time of calling the data from the memory and matching the rows so that the matrix which has not been replaced can be used as it is.

(Example 2) FIG. 9 is a block diagram of a driving device 401 of the present example. Also in this example, as in Example 1, the number of simultaneously selected rows 6 and the number of virtual rows 2 were adopted. The configuration different from Example 1 is as follows. First, the signal output from the memory 2 is not directly input to the line buffer 3 but input through the comparator circuit 4. Second
The point is that the virtual data generation circuit 8 has been deleted. The operation timing and the like are as shown in FIG. First, the mechanism and operation of the present example will be described.

As described above, in the case of the simultaneous selection number 6, the output value after the operation for determining the column voltage is “0, 1, 2, 3, 4,.
5, 6 ", and can be aggregated into" 2, 4, 6 "by adding two virtual data. In this example, since the block is divided into two blocks with three simultaneous selections, one virtual data is added to four output values “0, 1, 2, 3” in the case of three simultaneous selections to add “1, 3”. ].

Here, when the number of simultaneous selections is 6, and the output value after the operation is 2, the output value which can be considered when the output values are aggregated by setting two virtual data is invariable by the virtual data. There are two cases, “2” in the case and “4” in the case of +2, and cannot be uniquely determined from data when virtual data is not added.

On the other hand, when one virtual data is added when the number of simultaneous selections is three, the output value that can be changed by one virtual data is “0” or “+1”. If the output value is 0 or 1, the output value is "1".
In the case of 2, 3, it is uniquely determined that the data is aggregated into “3”.

From the above, in the case of three simultaneous selections,
The virtual data generation circuit becomes unnecessary, and the addition circuit 5A shown in FIG.
In this case, only the lower 2 bits of the output of the data No. need to be extracted as valid data. Further, since the virtual data generation circuit 8 is unnecessary, it is not necessary to temporarily store data in the line buffer 3 and then perform an operation, and the data can be latched after passing through the comparator circuit 4, and the number of comparator circuits can be reduced.

In this case, since the comparison is performed for each line, the row selection pattern generation circuit 7 synchronizes the bit from the top of each column of the orthogonal matrix one by one with the clock CL1 and the comparator circuit 4 and the row voltage generation circuit 9 Send to The row voltage generation circuit 9 uses a 5-bit shift register to store the five rows of the row selection pattern serially transmitted, so that the signal 1 directly transmitted from the row selection pattern generation circuit 7 is used.
A total of six rows are latched in synchronization with CL2, and output in synchronization with the next CL2 in synchronization with the column voltage generation circuit 11.

The timing of output synchronization is as shown in FIG. Also, as described in Example 1, if the timing of the line buffer of the arithmetic unit is appropriately adjusted,
As shown in this example, a line buffer for two lines is also possible, and there is a method of directly inputting the output of the comparator to the addition circuit 5A. The timing in this case is also as shown in FIG.

As described above, if the features of the number of simultaneous selections 3 and the number of virtual rows 1 are properly used, the virtual data generation circuit 8 can be eliminated. In addition, the circuit size of the comparator unit is only 1/3 of that of Example 1, so that the circuit size can be significantly reduced.
Further, since the circuit configuration is as described above, one chip of L
It becomes easy to integrate into SI.

For example, even when a power supply circuit including a booster circuit or the like and an oscillation circuit are built in, the chip size is determined by the output pad size due to the circuit reduction effect of the present invention, and there is almost no increase in chip cost. Rather, since integration can be performed using a semiconductor process for a 5V standard logic IC, manufacturing is facilitated and cost reduction can be achieved.

In the above embodiment, a square matrix is used as the matrices A and B whose row vectors are orthogonal to each other. However, the present invention is not limited to the case where a square matrix is used.

(Example A) With regard to the liquid crystal panel 10 of “64 rows × 132 columns” dots, six simultaneously selected drive rows and virtual row 2
The MLA driving method in which the “8 × 8” Hadamard matrix shown in FIG. 5 is used as a row selection pattern, the upper six rows are assigned to the actually selected rows, and the lower two rows are assigned to the virtual rows.

FIG. 15 is a block diagram of the driving device 302 with a controller. This corresponds to M
This corresponds to a = 6 and b = 2 in the LA driving method. The basic operation is the same as that shown in the conventional example 2. In the case of this method, the latch circuit including the line buffer is 8 × 132
8 × 132 comparator circuits 4, adder circuit 5
Requires an 8-bit circuit, and the virtual data generation circuit 8 requires a 6-bit decoder. For this reason, the circuit scale is greatly increased, and when a one-chip IC is used, the chip area is larger than the chip area determined by the output pad size.

[0069]

As described above, the driving device and the liquid crystal display device according to the present invention can suppress an increase in the scale of the arithmetic circuit even if the simultaneous selection driving method for a plurality of lines having virtual rows is used. By using a matrix in which the number of virtual rows is expanded to 1, the data generation circuit for virtual rows that has been conventionally required can be deleted. As a result, even when integrated on a one-chip LSI, the chip size can be determined by the pad size while minimizing the increase in current consumption, and a reduction in chip cost can be achieved. It became.

[Brief description of the drawings]

FIG. 1 is a block diagram of a driving device of Example 1.

FIG. 2 is a timing chart for explaining the operation of Example 1;

FIG. 3 is an explanatory diagram showing an orthogonal matrix of “4 × 4”;

FIG. 4 is an explanatory diagram showing an expanded orthogonal matrix used in the row selection pattern generation circuit of Example 1;

FIG. 5 is an explanatory diagram showing an “8 × 8” Hadamard matrix.

FIG. 6 is a circuit diagram showing a circuit configuration example of one line of a comparator.

FIG. 7 is a block diagram of a driving device using Conventional Example 1 (line-sequential driving method).

FIG. 8 is a block diagram of a driving device using Conventional Example 2 (MLA driving method).

FIG. 9 is a block diagram of a driving device of Example 2.

FIG. 10 is a timing chart illustrating the operation of Conventional Example 2.

FIG. 11 is a waveform chart showing a driving waveform example of Conventional Example 1.

FIG. 12 is an explanatory diagram showing an example of display data.

FIG. 13 is an explanatory diagram showing an example of display data.

FIG. 14 is a timing chart for explaining the operation of Example 2;

FIG. 15 is a block diagram of a driving device used in Example A.

[Explanation of symbols]

 1: Controller 2: Memory 3: Line buffer 4: Comparator circuit 5, 5A, 5B: Addition circuit 6, 6A, 6B: Latch circuit 7: Row selection pattern generation circuit 8: Virtual data generation circuit 9: Row voltage generation circuit 10: liquid crystal panel 11: column voltage generation circuit 101, 201, 202, 301, 401: driving device 51, 52, 61: arithmetic circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masakazu Kitamura 1150 Hazawacho, Kanagawa-ku, Yokohama-shi, Kanagawa Prefecture Inside Asahi Glass Co., Ltd. (72) Inventor Yoshiyoshi Tamai 1150 Hazawacho, Kanagawa-ku, Yokohama-shi, Kanagawa Prefecture Asahi Glass Co. 72) Inventor Makoto Nagai 1150 Hazawa-cho, Kanagawa-ku, Yokohama City, Kanagawa Prefecture Inside Asahi Glass Co., Ltd.

Claims (6)

[Claims] 1. A virtual data generating means, a row electrode driving means, a column electrode driving means, a memory means for storing display data, a calculating means for calculating a column output voltage, and a row selection for outputting a row selection pattern. Pattern generating means,
For a liquid crystal display element in which row electrodes and column electrodes are arranged in a matrix, k · m (k is an integer of 2 or more, m is an integer of 1 or more) simultaneously selected driving rows and k · n (n is 1) In the driving apparatus in which virtual rows of the above integers are set and driven by the multiple row simultaneous selection method, a matrix B obtained by expanding a matrix A of (m + n) rows in which row vectors are orthogonal to each other as a row selection pattern.
And a column output voltage is calculated in units of A using the following. A row electrode driving means; a column electrode driving means; a memory means for storing display data; a calculating means for calculating a column output voltage; and a row selection pattern generating means for outputting a row selection pattern. For a liquid crystal display element in which row electrodes and column electrodes are arranged in a matrix, km · m (k is an integer of 2 or more, m is an integer of 1 or more) simultaneously selected driving rows and k virtual rows And a matrix B in which a matrix A in which row vectors are orthogonal to each other (m rows + 1 virtual rows) is used as a row selection pattern, and a column output voltage is set in units of A. A driving device for calculating 3. The driving apparatus according to claim 1, wherein a matrix B in which the row vectors of the equation (1) are orthogonal to each other is used. However, in the formula (1), p ₁ , p ₂ , p ₃ , and p ₄ are each 1 or −1, and p ₁ · p ₂ · p ₃ · p
₄ = -1. (Equation 1) 4. The driving apparatus according to claim 3, wherein a matrix C in which the row vectors of the equation (2) are orthogonal to each other is used. However, in the equation (2), p ₅ , p ₆ , p ₇ , and p ₈ each represent 1
Or -1, _{and, p 5 · p 6 · p} 7 · p 8 = -
It is one. (Equation 2) 5. The semiconductor device according to claim 1, wherein the LSI is a one-chip LSI.
Or the driving device according to 4. 6. A liquid crystal display device comprising the driving device according to claim 1, 2, 3 or 4, and a liquid crystal display element.