JP2001186413A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor that can reduce the utilizing rate of a data bus in the case of superimposing OSD data onto image data, improve the update frequency of image contents and reduce the storage capacity. SOLUTION: A RAM 1 stores image data 8, OSD data 7, and OSD mask data 6 and an image data transfer section 40 reads the data via a data bus 2. An 'image+OSD' data composition circuit 14 receives the three kinds of the data read from the RAM 1 in prescribed timing and superimposes the OSD data 7 onto the image data 8 according to the OSD mask data 6. The composited image by the 'image+OSD' data composition circuit 14 is directly fed to a video signal generating circuit 5, where the image is converted into a video signal of a prescribed format.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an on-screen display (OSD) function for displaying control information or service information such as characters and graphics on an image in an overlapping manner. The present invention relates to an image processing apparatus having the same.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional image processing apparatus. The image processing apparatus includes a RAM (Random Access Memory) 1, a data bus 2 connected to the RAM 1,
RAM control block 3 for managing the state of M1 and data bus 2, image data transfer unit 4 for reading out color or monochrome image data from RAM 1 via data bus 2, and video signal generated from output from image data transfer unit 4 Video signal generating circuit 5 and data bus 2
Connected to the RAM 1 via the superimpose (su
The apparatus includes a superimpose circuit 10 that generates “image + OSD” data 20 that has been subjected to per inpose.

The RAM 1 as storage means stores OSD mask data 6 and OSD data 7 as processing information,
The image data 8 combined with the D data 7, “image + OS
D ”data 20 is stored. For example, if the video signal output from the video signal generation circuit 5 is NTSC
(National Television System Committee) method, OSD mask data 6 for 720 × 480 pixels,
OSD data 7 and image data 8 are stored. The OSD mask data 6 includes position information at the time of superimposing, color information, information for masking a part of an image as needed, and the like. The image data transfer unit 4 includes an image data buffer memory 11 for reading and storing “image + OSD” data 20, an image buffer write control circuit 12 for controlling data writing to the buffer memory 11, and an image data buffer memory. 1
1 is provided with a buffer read control circuit 13 for controlling data read from the video signal generation circuit 5 to the video signal generation circuit 5. The video signal generation circuit 5 includes a timing signal generation unit 9 that controls the image buffer write control circuit 12 and the buffer read control circuit 13. Also,
The superimpose circuit 10 includes an “image + OSD” data synthesizing circuit 14 that synthesizes OSD data with an image and outputs “image + OSD” data 20.

FIG. 6 shows image processing of the image processing apparatus shown in FIG. The operation of the image processing apparatus of FIG. 5 will be described with reference to FIG. Conventional image processing is roughly divided into two processes.
D "process 20 for generating and storing data 20;
From the "image + OSD" data 20 to generate a video signal.

First, image data 8, OSD data 7, and OSD mask data 6 are read from the RAM 1 by the superimpose circuit 10 via the data bus 2 (step 301), and the "image + OSD" data synthesizing circuit 14 is used. Then, the image data 8 and the OSD data 7 are superimposed according to the OSD mask data 6 to generate "image + OSD" data (step 302), and are stored again in the RAM 1 as "image + OSD" data 20 (step 303). Next, as a process 2, the “image + OSD” data 20 stored in the RAM 1 is read from the RAM by the image data transfer unit 4 (step 304), and the “image + OSD” is stored in the image data buffer memory 11 of the image data transfer unit 4. The data 20 is written (step 305), and the image data written to the image data buffer memory 11 is read out by the buffer read control circuit in accordance with the timing of the video signal timing generation circuit 9 in accordance with the image input timing required by the video signal generation circuit 5. 13 and is input to the video signal generation circuit 5. The video signal generation circuit 5
Since the image of "image + OSD" obtained by superimposing the OSD data 7 on the image data 8 is an R, G, B digital signal, this is converted into an NTSC video signal and output (step 306).

[0006]

However, according to the conventional image processing apparatus, the superimposed "image + OS
Superimposing processing 1 in steps 301 to 303 to output the image of "D" as a video signal;
It is necessary to execute processing 2 for outputting the “image + OSD” data 20 after superimposition as a video signal. And "Image + OSD" after superimposing
Since the data is stored in the RAM 1, the use of the data bus 2 is increased and the bus processing is easily broken.

Further, since the image is temporarily stored in the RAM 1, the continuity of the processing is lost, and the utilization rate of the data bus is increased as described above.
It is difficult to update the contents of the "OSD" data 20 many times to continuously output a video output. In order not to interrupt the video signal, the image of the same content is repeatedly output continuously.
D "The update frequency of the data 20 needs to be reduced. “Image + OSD” data 2 after superimposition
Since 0 is stored in the RAM 1, it is necessary to secure the storage area in the RAM 1, and the minimum storage capacity required for realizing the image processing apparatus is large.

An object of the present invention is to provide an image processing apparatus capable of reducing the use rate of a data bus when superimposing OSD data on image data, increasing the frequency of updating image contents, and reducing storage capacity. To provide.

[0009]

In order to achieve the above object, the present invention provides image data, OSD (on-screen display) data superimposed on the image data, and processing information for superimposing. And a data synthesizing unit for performing the superimposing process, wherein the image data read from the storage means, the OSD data read from the storage means, and the data read from the storage means are stored. An image generating unit that supplies each of the processing information to the data synthesizing unit at a predetermined timing and generates a synthesized image in which the OSD data is superimposed on the image data based on the processing information; and Video signal generating means for converting the synthesized image into a video signal of the NTSC system or the like. To provide an image processing apparatus, characterized in that it comprises.

According to this configuration, at the time of the superimposing process, the image data, the OSD data, and the processing information stored in the storage unit are read at the time of the superimposing process and supplied to the data synthesizing unit at a predetermined timing. The OSD data is superimposed on the image data according to the processing information. The obtained superimposed image is sent to the video signal generating means as it is without being stored, and becomes a video signal converted into a predetermined format.
Therefore, the utilization rate of the data bus when outputting video by superimposing OSD data on image data is reduced. For this reason, it is possible to update the image content every time and continuously output a video signal in real time, thereby increasing the update frequency of the image content, and storing the image data after superimposing in the storage means. Since there is no need, the used storage area can be reduced.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a first embodiment of an image processing apparatus according to the present invention. The image processing apparatus according to the present invention includes:
RAM 1, data bus 2 connected to RAM 1, RA
RAM control block 3, which manages the state of M1 and data bus 2, and three kinds of data (OSD mask data 6, OSD data 7, and image data 8) are read out from RAM 1 via data bus 2 and "image + OSD" data An image data transfer unit 40 for generating the image data 20 and a video signal generation circuit 5 for generating a video signal based on the “image + OSD” data 20 from the image data transfer unit 40 are provided.

The image data transfer section 40 is provided in
In addition to the image data buffer memory 11, the image buffer write control circuit 12, the buffer read control circuit 13, and the "image + OSD" data synthesizing circuit 14, the OSD mask data buffer memory 41, OSD
The circuit includes a mask buffer write control circuit 42, an OSD data buffer memory 43, and an OSD buffer write control circuit 44. The OSD mask data buffer memory 41 is used to store the OSD mask data 6, and the OSD data buffer memory 43 is
Used to store data 7. The image data 8 is stored in the image data buffer memory 11. And
FIFO memories are used for the image data buffer memory 11, the OSD mask data buffer memory 41, and the OSD data buffer memory 43.

FIG. 2 shows the processing of the embodiment of FIG. The operation of the image processing apparatus having the configuration shown in FIG. 1 will be described with reference to FIGS. First, under the control of the RAM control circuit 3, the image data 8, OSD data 7, and OSD mask data 6 stored in the RAM 1 are read out to the image data transfer section 40 via the data bus 2, and the image data 8 is a buffer memory for image data 11
Next, the OSD mask data 6 is stored in the OSD mask data buffer memory 41 and the OSD data 7 is stored in the OSD data buffer memory 43 (step 101). When writing the image data 8 into the image data buffer memory 11, the image data 8 is written into the image data buffer memory 11 in accordance with the timing of the video signal timing generation circuit 9 in accordance with the image input timing required by the video signal generation circuit 5. Buffer memories 11, 41, 43
, Each data relating to the same pixel is simultaneously read out to the “image + OSD” data synthesizing circuit 14 by the buffer reading circuit 13. The “image + OSD” data synthesizing circuit 14 outputs the read OSD
OS for image data 8 according to contents of mask data 6
A process of superimposing the D data 7 is performed (step 102), and “image + OSD” data 20 is generated.
This is output to the video signal generation circuit 5 (step 10).
3). The video signal generation circuit 5 converts the image data 8 into an OSD
"Image + OSD" with data 7 superimposed
Is output as a video signal (step 10).
4).

As described above, in the present embodiment,
The image data transfer unit 40 converts the image data 8 and the OSD data 7 separately stored in the RAM 1 into RA data.
Read from M1, "image + OSD" data synthesis circuit 1
4 generates a superimposed image and directly outputs the video without storing it in the RAM 1 as in the prior art, thereby enabling continuous image processing. RAM1
, Only reading is performed, so that the load on the data bus is reduced as compared with the related art, and the data storage capacity of the RAM 1 can be reduced.

[Second Embodiment] FIG. 3 shows a second embodiment of the present invention.
An embodiment will be described. This embodiment is characterized in that an image data transfer unit 50 is used in place of the image data transfer unit 40 in the configuration of FIG. The image data transfer unit 50 includes an interpolation circuit 51 between the OSD mask data buffer memory 41 and the “image + OSD” data synthesizing circuit 14 in addition to the configuration of the image data transfer unit 40. Image + OSD "data combining circuit 14
And an interpolation circuit 52 is provided between them.

The interpolating circuits 51 and 52 read out from the buffer memories 41 and 43 in the image data transfer unit 50 when reducing the information amount of the OSD data 7 and the OSD mask data 6 stored in the RAM 1 with respect to the image data 8. After that, the reduced original information amount is used by the interpolation circuits 51 and 52 to make up. The process of reducing the information amount of the OSD data 7 and the OSD mask data 6 is performed by a circuit (not shown) and then stored in the RAM 1. Although there are various processes for reducing the information amount of the OSD data 7 and the OSD mask data 6, for example, it is achieved by a process of thinning out each pixel. The interpolation processing by the interpolation circuits 51 and 52 may be the reverse of the processing for reducing the information amount.

In general, it is known that the information amount of the OSD data 7 sufficiently fulfills its function with respect to the image data 8. For example, if the total number of pixels of the image data 8 is 720 pixels × 480 lines,
360 pixels x 48 with the number of pixels in the horizontal direction reduced to half
Data for 0 lines is stored in the RAM 1 as OSD data 70 and OSD mask data 60. In the image processing apparatus, the number of pixels of the OSD data 7 and the number of pixels of the image data 8 need to be equal at the time of performing the superimposition. However, as described above, RAM1
Stores OSD data 70 whose data amount is reduced to half that of the image data 8, and this OSD data 70 is directly used as the “image + OSD” data synthesizing circuit 14.
Cannot be read. Therefore, the O read from the RAM 1 and stored in the OSD data buffer memory 43
When the SD data 70 is read, the interpolation circuit 52 interpolates to generate the OSD data 7. When the OSD mask data 60 read from the RAM 1 and stored in the OSD mask data buffer memory 41 is read, the interpolation circuit 51
To generate OSD mask data 6. As a result, the amount of information of the OSD data 7 to be stored in the RAM 1 can be reduced and stored as the OSD data 70, so that the frequency of use of the data bus 2 is reduced and the load on the data bus 2 is significantly larger than that of the first embodiment. To reduce.

FIG. 4 shows the processing of the image processing apparatus of FIG.
The operation of the image processing apparatus having the configuration shown in FIG. 3 will be described with reference to FIGS. As described above, the data obtained by reducing the number of pixels in the horizontal direction by half is stored in the RAM 1 as the OS.
D data 70 and OSD mask data 60 are stored. Under the control of the RAM control circuit 3, R
Image data 8 and OSD data 7 stored in AM1
0 and the OSD mask data 60 are read out to the image data transfer unit 50, the image data 8 is stored in the image data buffer memory 11, and the OSD mask data 60 is stored in the OSD mask data 60.
The OSD data 70 is stored in the OSD data buffer memory 43 (step 201). Buffer memories 11, 41, 43
Of the same pixel is simultaneously read out to the “image + OSD” data synthesizing circuit 14 under the control of the buffer reading circuit 13. At this time, the interpolation circuit 52 applies to the OSD data 70 read from the OSD data buffer memory 43.
, The process of interpolation into the original OSD data 7 of 720 pixels × 480 lines is performed, and the OSD mask data 6 read from the OSD mask data buffer memory 41
For 0, the interpolation circuit 51 uses the original 720 pixels × 48
A process of interpolating the OSD mask data 6 for 0 lines is performed, and each is sent to the “image + OSD” data combining circuit 14 (step 202). The “image + OSD” data synthesizing circuit 14 applies an interpolation circuit 52 to the image data 8 according to the contents of the OSD mask data 6 from the interpolation circuit 51.
To superimpose the OSD data 7 from the camera (step 203), and the “image + OSD” data 20
Generate This superimposed image data is output to the video signal generation circuit 5 (step 204).
The video signal generation circuit 5 outputs an image of “image + OSD” in which the OSD data 7 is superimposed on the image data 8 as an NTSC video signal (step 205).

In the above embodiment, the RAM is used to store the image data 8, the OSD data 7, and the OSD mask data 6. However, the present invention is not limited to this. For example, a Herber disk, a CD-ROM, etc. Storage medium. Further, only the OSD mask data 6 may be stored in a ROM (read only memory), and the image data 8 and the OSD data 7 may be stored in the RAM 1. Further, the video signal output from the video signal generation circuit 5 is based on the NTSC system, but is not limited thereto, and may be a PAL, a Secum system, or the like. Note that the RAM1
Have different amounts of data.

[0020]

As described above, according to the image processing apparatus of the present invention, the image data read from the storage means,
The SD data and the processing information are supplied to the data synthesizing section at a predetermined timing, and the image data is converted to image data according to the processing information.
Since the image generating means for generating the synthesized image obtained by superimposing the D data by the data synthesizing unit is provided, the superimposed image can be directly used as the video signal generating means without being stored again in the storage means. The load on the data bus can be reduced, and the storage area used by the storage means can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a flowchart illustrating a process of the image processing apparatus of FIG. 1;

FIG. 3 is a block diagram illustrating a second embodiment of the image processing apparatus according to the present invention.

FIG. 4 is a flowchart illustrating a process of the image processing apparatus of FIG. 3;

FIG. 5 is a block diagram showing a conventional image processing apparatus.

FIG. 6 is a flowchart illustrating a process of the image processing apparatus of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 RAM 2 Data bus 40 Image data transfer part 5 Video signal generation circuit 11 Image data buffer memory 12 Image buffer write control circuit 13 Buffer read control circuit 14 "Image + OSD" data synthesis circuit 41 OSD mask data buffer memory 42 OSD Buffer write control circuit for mask 43 Buffer memory for OSD data 44 Buffer write control circuit for OSD 51, 52 Interpolation circuit

 ────────────────────────────────────────────────── ─── Continued on the front page F term (reference) 5C023 AA18 CA01 CA05 CA08 DA03 5C025 CA02 CA09 5C082 AA02 BA02 BA12 BA34 BA35 BB22 CA55 CB03 DA63 DA76 DA86 EA14 MM02 MM04

Claims (5)

[Claims] Storage means for storing image data, OSD (on-screen display) data superimposed on the image data, and processing information for superimposing the OSD data; A data synthesizing unit for performing the above-mentioned processing. An image generating means for generating a composite image in which the OSD data is superimposed on the image data based on the processing information; and converting the composite image from the image generating means into a video signal of an NTSC system or the like. An image processor comprising a video signal generating means for converting. Apparatus. A first buffer memory for temporarily storing the image data read from the storage unit; and a second buffer memory for temporarily storing the OSD data read from the storage unit. A buffer memory for temporarily storing the processing information read from the storage means, and a first buffer memory for controlling writing of the image data from the storage means to the first buffer memory. A write control circuit; and the O from the storage means to the second buffer memory.
A second write control circuit that controls writing of SD data; a third write control circuit that controls writing of the processing information from the storage unit to the third buffer memory; The image processing apparatus according to claim 1, further comprising: a read control circuit that controls reading of the image data, the OSD data, and the processing information from a third buffer memory to the data combining unit. 3. The video signal generating means according to claim 1, wherein:
2. The image processing apparatus according to claim 1, further comprising: a second and third write control circuit; and a timing signal generation unit that supplies a timing signal for writing and reading to and from the read control circuit. 4. The storage means stores the OSD data and the processing information whose data amount has been reduced, and wherein the OSD data buffer memory and the processing information buffer memory have the data amount reduced. O
2. The image processing apparatus according to claim 1, further comprising an interpolation unit that corrects an information amount of the SD data and the processing information so as to match an information amount of the image data. 5. The image according to claim 1, wherein said storage means is a RAM from which each of said storage data, said OSD data, and said processing information is read out via a common data bus. Processing equipment.