JP2002033444A - Semiconductor device - Google Patents

Abstract

(57) [Summary] A semiconductor device of a type in which an RF signal chip and a high-speed digital signal chip are mixed has a problem of designing electric characteristics thereof. SOLUTION: A wiring board 9 having an area array electrode 7
Connecting the first semiconductor chip 3f of the CSP type using the lead frame 1 to the lead frame 1, further stacking it together with the second semiconductor chip 3s which is a semiconductor chip for RF analog signals, and forming one package with the sealing resin 6. As a result, a stacked semiconductor device satisfying the electrical characteristics required for a high-speed digital signal semiconductor chip and reducing the mounting area of an RF analog signal semiconductor chip can be realized with small size, high performance, and low cost. is there.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a plurality of semiconductor chips mounted in one package.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described below with reference to the drawings. 5 and 6 are main cross-sectional views showing a conventional semiconductor device.

First, in the conventional semiconductor device shown in FIG. 5, a semiconductor chip 3 is mounted on a die pad 2 of a lead frame 1 by die bonding via an adhesive 4, and bonding pads of the semiconductor chip 3 (not shown). And the tip of the inner lead 1a of the lead frame 1 is wire-bonded with a thin metal wire 5 to make electrical connection.
The semiconductor device is formed by molding with a sealing resin 6 in a mold having a predetermined shape. After the resin is sealed and the resin is cured, the outer leads 1b of the lead frame 1 of the semiconductor device removed from the mold are processed into a predetermined lead shape by a lead forming mold.

[0006] The semiconductor device shown in FIG. 6 is a two-chip stacked type semiconductor device, in which a first semiconductor chip 3 f is mounted on a die pad 2 portion of a lead frame 1 by die bonding via an adhesive 4. Further, a second semiconductor chip 3s is mounted thereon via an adhesive 4,
The bonding pads (not shown) of each semiconductor chip and the tips of the inner leads 1a of the lead frame 1 are wire-bonded by the first and second thin metal wires 5f and 5s to be electrically connected to each other and have a predetermined shape. The semiconductor device is formed by molding with a sealing resin 6 in a mold having the following. After the resin is sealed and the resin is cured, the outer leads 1b of the lead frame 1 of the semiconductor device removed from the mold are processed into a predetermined lead shape by a lead forming mold.

[0005] After the semiconductor device is completed, electrical connection, signal inspection, and reliability test are performed, and products judged as non-defective are packaged and shipped.

[0006]

However, in the above-mentioned conventional semiconductor device, there is a problem that a lead frame or a thin metal wire causes delay, loss or reflection of a transmission signal. This problem is caused by a plurality of types of semiconductor chips in one package. This is particularly noticeable when the device is mounted. For example, in a stack package or a multi-chip package in which an RF analog signal semiconductor chip and a high-speed digital signal semiconductor chip having different signal components are mixed in one package, and a transmission line design including a lead frame and a thin metal wire (wire). In this case, it becomes difficult to design a package for achieving both electrical characteristics of the semiconductor chips. One of the simple solutions is a small package or BGA (Ball Gri) using a wiring board.
dArray) and CSP (Chip Size Pac)
Kage), which is a package with good impedance characteristics, and is particularly effective for high-speed digital signal semiconductor chips. At present, in the case of a chip whose clock frequency exceeds 400 MHz, an area array package such as CSP or BGA is used. ing. R
Although there have been some types of semiconductor chips for F-system analog signals exceeding 2 GHz, there is no need to reduce the size in terms of performance, but rather, the aim is only to reduce the mounting area.
In addition, although it is technically possible to form a multi-chip package or stacked package of CSP and BGA for RF analog signal semiconductor chips and high-speed digital signal semiconductor chips,
The RF analog signal semiconductor chip is smaller in area than the high-speed digital signal semiconductor chip, and may be more expensive. Therefore, a design that maximizes the performance of high-speed digital signals, and a reduction in mounting area, low cost, and high productivity due to a mixture of RF signal systems have been issues.

An object of the present invention is to provide a semiconductor device having a plurality of semiconductor chips in a single package, which is capable of tuning the resonance intensity of an RF signal system and which can be easily manufactured at low cost. With the goal.

[0008]

In order to solve the above-mentioned conventional problems, a semiconductor device according to the present invention has an area array electrode on a bottom surface thereof and a bonding pad electrically connected to the area array electrode inside the substrate on the surface. A first semiconductor chip mounted face-down with its back face up with respect to the bonding pads on the top face of the wiring board; and a back face end of the first semiconductor chip bonded to the bonding pad. An inner lead of the lead frame, a second semiconductor chip stacked and mounted on the back surface of the first semiconductor chip, a thin metal wire connecting the second semiconductor chip and the inner lead, and an inner lead. A sealing resin that seals an upper surface area of the wiring substrate, and an inner lead of the lead frame whose tip end surface is exposed from the sealing resin. And more becomes a semiconductor device and outer lead portions that.

More specifically, the first semiconductor chip is a high-speed digital signal semiconductor chip, and the second semiconductor chip is an RF analog signal semiconductor chip.

[0010] Further, the present invention is a semiconductor device having a metal cap for shielding around a sealing resin.

As described above, a CSP using a wiring board having an area array electrode is laminated together with a semiconductor chip for an RF analog signal in a resin-sealed package of a normal method, thereby providing a high-speed digital signal semiconductor chip. It is possible to realize a stacked semiconductor device that satisfies the required electrical characteristics and reduces the mounting area of the semiconductor chip for RF analog signals.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the semiconductor device of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to this embodiment.

The semiconductor device shown in FIG. 1 uses a lead frame and a wiring board. First, an area array electrode 7 having a two-dimensional array is provided on the bottom surface of the substrate. A first semiconductor chip 3f is mounted face down on a wiring board 9 having on its surface bonding pads 8 which are electrically connected to the inside of the board. In this state, a one-chip chip size package (CSP) is formed, and a space between the chip and the substrate is filled with a sealing resin (not shown). Then, the back end (bottom surface) of the first semiconductor chip 3f and the inner lead 1a of the lead frame are bonded to the adhesive 4
The second semiconductor chip 3s is adhered and mounted on the back surface of the first semiconductor chip 3f by the adhesive 4 on the bottom surface of the first semiconductor chip 3f, thereby forming a two-chip stacked state. And the second
Pad of semiconductor chip 3s (not shown)
And the inner leads 1a are connected by thin metal wires 5, and the upper surface area of the wiring board 9 including the inner leads 1a of the lead frame 1 is sealed with a sealing resin 6. Also, the inner lead 1a of the lead frame 1
The outer lead portion 1b connected to the sealing resin 6 is cut so that the tip end surface is exposed on substantially the same surface as the side surface of the sealing resin 6,
QFN (Quad Flat Non-leaded)
(Package) structure.

In the present embodiment, the first semiconductor chip 3f is a high-speed digital signal semiconductor chip.
The second semiconductor chip 3s is an RF analog signal semiconductor chip.

The semiconductor device according to the present embodiment is characterized in that a CSP using a wiring board having an area array electrode is laminated together with a semiconductor chip for RF analog signals in a resin-sealed package of a normal method. Thus, it is possible to realize a stacked semiconductor device that satisfies the securing of the electrical characteristics required for the high-speed digital signal semiconductor chip and the reduction of the mounting area of the RF analog signal semiconductor chip.

Next, the electrical characteristics of the semiconductor device shown in FIG. 1 will be described.

In particular, a line for transmitting an analog signal of an RF system has an extremely strong resonance intensity (Q value) in a used frequency band.
Alternatively, either the transmission line, which is extremely weak, requires tuning. In the equation, f = 1 / 2π√LC, Q = ωL /
R (f is a resonance frequency, L is an inductance, C is a capacitance, Q is a resonance intensity, R is a DC resistance, and ω is a phase), and is an inductance L
The components can be used for tuning. Therefore, the second semiconductor chip 3s needs to be an RF analog signal semiconductor chip. Tuning of the L component is adjusted by the length of the thin metal wire 5. Further, in the RF system, it is necessary to reduce the influence of electromagnetic radiation noise, so that a metal shield connected to GND is required.

On the other hand, a baseband high-speed digital signal from a high-speed digital signal-based semiconductor chip has a plurality of high-frequency components as sine waves, so even if only a certain high frequency can be adjusted, it is very difficult to control all of them. Difficult. The reason is that the transmission line having the lead frame and the thin metal wire of the present embodiment is a lossy line having no characteristic impedance. As baseband digital signals increase in speed, standard plastic packages (resin-sealed packages), lead frames, and semiconductor devices using thin metal wires (wires) become inevitably difficult to use. A CSP or BGA having a layer or area array electrode is required.

The former multilayer substrate has a GND layer and can easily form a microstrip line or a coplanar line.
Characteristic impedance can be designed to be constant. The latter area array electrode can be designed to shorten the wiring length.

Next, another embodiment will be described.

FIG. 2 is a main sectional view showing the semiconductor device of the second embodiment. The basic configuration is the same as that of the semiconductor device shown in FIG. 1, and a wiring board 9 having an area array electrode 7 is used. The CSP of one chip is laminated together with a semiconductor chip for RF analog signals (second semiconductor chip 3s) using a lead frame 1 in a resin-sealed package of a normal method. The molding configuration around the semiconductor chip is different, and the outer lead 1b of the lead frame 1 is configured to protrude from a substantially central portion of the side surface of the sealing resin 6. The semiconductor device shown in FIG. 2 is similar in characteristics and function to the semiconductor device shown in FIG. 1, but is a conventional gull-wing-shaped outer lead 1b, so that the versatility for substrate mounting is improved. is there. That is, the conventional QFP (Quad Flat P
The semiconductor device can be mounted on a substrate by using the same equipment as the semiconductor device of the package type.

FIG. 3 is a main sectional view showing the semiconductor device of the third embodiment. The basic structure is the same as that of the QFN type semiconductor device shown in FIG. 9 using a lead frame 1 in a resin-sealed package of the normal method.
It is laminated together with the F-system analog signal semiconductor chip (second semiconductor chip 3s), but is shielded by the metal cap 10. Metal cap 10
By covering the outer periphery of the semiconductor device with α, it plays a role as a measure against α-rays and as an electromagnetic shield.

FIG. 4 is a view showing a semiconductor device according to the fourth embodiment, and shows a GND ground state together with a cross-sectional view of the semiconductor device. The semiconductor device shown in FIG. 4 is different from the CSP shown in FIG. 1 in that a single-chip CSP using a wiring substrate 9 having an area array electrode 7 is compared with an RF analog signal semiconductor chip (a second semiconductor chip). 3s), the outer periphery is sealed with a sealing resin 6, and the outermost surface is shielded by a metal cap 10. A mounting GN connected to the metal cap 10
The semiconductor device has a D terminal 11 at a bottom end (package corner) of the semiconductor device.

As described above, the semiconductor device according to the present embodiment has a wiring board having an area array electrode on the bottom surface thereof and a bonding pad electrically connected to the area array electrode inside the substrate, and a wiring board having an upper surface of the wiring board. A first semiconductor chip mounted face-down with its back face up with respect to the bonding pad; inner leads of a lead frame adhered to the back face end of the first semiconductor chip;
A second semiconductor chip stacked and mounted on the back surface of the first semiconductor chip, a thin metal wire connecting the second semiconductor chip and the inner lead, and an upper surface area of the wiring substrate including the inner lead are sealed. A semiconductor device comprising a sealing resin and an outer lead portion connected to an inner lead of a lead frame whose tip surface is exposed from the sealing resin. Therefore, the mounting area of the semiconductor chip for analog signals can be reduced.

[0026]

As described above, according to the present invention, a CSP type first semiconductor chip using a wiring board having an area array electrode is connected to a lead frame, and further, an RF analog signal semiconductor chip is used. By stacking together with a certain second semiconductor chip and forming one package with sealing resin, it satisfies the securing of the electrical characteristics required for high-speed digital signal semiconductor chips and the reduction of the mounting area of RF analog signal semiconductor chips. The stacked semiconductor device can be realized with small size, high performance, and low cost.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a sectional view showing a semiconductor device according to one embodiment of the present invention;

FIG. 4 is a diagram showing a semiconductor device according to one embodiment of the present invention;

FIG. 5 is a sectional view showing a conventional semiconductor device.

FIG. 6 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lead frame 1a Inner lead 1b Outer lead 2 Die pad 3 Semiconductor chip 3f First semiconductor chip 3s Second semiconductor chip 4 Adhesive 5 Thin metal wire 5f First thin metal wire 5s Second thin metal wire 6 Sealing resin 7 Area Array electrode 8 Bonding pad 9 Wiring board 10 Metal cap 11 GND terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 23/28 H05K 9/00

Claims (3)

[Claims] A wiring board having an area array electrode on a bottom surface thereof and a bonding pad electrically connected to the area array electrode inside the substrate, and a back surface of a bonding pad on an upper surface of the wiring board. A first semiconductor chip mounted face-down with the top side up, inner leads of a lead frame adhered to a back end of the first semiconductor chip, and stacked and mounted on a back surface of the first semiconductor chip Second semiconductor chip, and the second semiconductor chip
A thin metal wire connecting the semiconductor chip and the inner lead, a sealing resin that seals an upper surface area of the wiring substrate including the inner lead, and a lead frame whose tip surface is exposed from the sealing resin. A semiconductor device comprising an outer lead portion connected to an inner lead. 2. The semiconductor device according to claim 1, wherein the first semiconductor chip is a high-speed digital signal semiconductor chip, and the second semiconductor chip is an RF analog signal semiconductor chip. 3. The semiconductor device according to claim 1, wherein a metal cap for shielding is provided around the sealing resin.