JP2004069882A - Asynchronous processing device for image signals - Google Patents

Abstract

Kind Code: A1 The present invention relates to an asynchronous processing apparatus for an image signal, and an object of the present invention is to provide an asynchronous processing apparatus for an image signal that prevents overlapping of writing and reading of an image signal to and from a frame memory and that does not disturb the image. I have.
A plurality of frame memories for writing and reading image signals, a vertical synchronization frequency difference detecting means for detecting a frequency difference between a vertical synchronization signal of an image input signal and an image output signal, and a reference oscillator are provided. Output synchronizing signal generating means 11 for generating an image synchronizing signal upon receiving the output, and receiving the output of the vertical synchronizing frequency difference detecting circuit 12 and the output of the output synchronizing signal generating circuit 11 and A frame memory control means 15 for controlling the writing and reading of data, wherein if the input vertical synchronizing frequency is within an allowable value of the output vertical synchronizing frequency, the output synchronizing signal generating means 11 is reset to perform synchronization. I do.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image signal asynchronous processing device.
An image signal such as an image signal is written to a frame memory, and the image signal written to the frame memory is read from the frame memory and displayed on, for example, a display device. In this case, since the writing system of the image signal and the reading system of the image signal are not synchronized (asynchronous), it is necessary to write and read the image signal to and from the frame memory without error.
[0002]
[Prior art]
FIG. 10 is a diagram showing a configuration example of a conventional device. Here, a case where a video signal is used as an image signal is shown. In the figure, reference numeral 1 denotes a frame memory for writing and reading a video signal, and shows a case where three frame memories 1 to 3 exist in the figure. A video signal is input to the frame memory 1, and a video signal is output from the frame 1.
[0003]
Reference numeral 2 compares the video synchronization signal extracted from the video signal with the output synchronization signal generated from the crystal oscillator 4 and output from the output synchronization signal generation circuit 3 to generate a control signal for controlling the frame memory. This is a frame memory control signal generation circuit.
[0004]
In the device configured as described above, the frame memory control signal generation circuit 2 receives the video synchronization signal and the output synchronization signal, and controls writing and reading of the video signal in the frame memories 1 to 3.
[0005]
FIG. 11 is a time chart of writing to and reading from the frame memory. First, video signals W1, W2, and W3 are sequentially written to the frame memories 1 to 3, respectively. The video signals written in the frame memories 1 to 3 are read out as indicated by R1 to R3 in FIG. For the same frame, it is necessary that the write operation and the read operation do not overlap.
[0006]
In FIG. 10, a video signal is written to a frame memory 1 by generating a memory control signal in a frame memory control signal generating circuit 2 with an input clock based on an input vertical synchronizing signal. The reading of the signal is performed by controlling the frame memory control signal generation circuit 2 with a memory control signal of a predetermined vertical synchronization frequency by the output side clock.
[0007]
Therefore, the writing and reading of the video signal become asynchronous, and at the timing when the writing operation and the reading operation to the frame memory 1 overlap, the image signals of the new and old frames are mixed on the same frame. FIG. 12 is an explanatory diagram of the overlap between the write signal and the read signal. As the “H” active, the write signal and the read signal partially overlap, and an overlap region is formed.
[0008]
[Problems to be solved by the invention]
As described above, in an apparatus that converts an image signal from an imaging system having a different vertical synchronization frequency into a predetermined image signal having a different vertical synchronization frequency, when the writing and reading of the image signal to the frame memory overlap, the same There is a problem that the images of the new and old frames (the image of the previous frame and the image of the current frame) are mixed in the frame, and the images are disturbed.
[0009]
The present invention has been made in view of such a problem, and it is an object of the present invention to provide an image signal asynchronous processing device that prevents overlapping of writing and reading of an image signal in a frame memory and that does not disturb the image. The purpose is.
[0010]
[Means for Solving the Problems]
(1) FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 10 are denoted by the same reference numerals. In the figure, reference numeral 1 denotes a frame memory, and in the figure, three cases of frame memories 1 to 3 are shown. An image signal is input to these frame memories, and an image signal is output. In the figure, reference numeral 10 denotes a crystal oscillator for outputting an accurate constant frequency pulse, and reference numeral 11 denotes an output synchronization signal generation circuit as output synchronization signal generation means for receiving an output of the crystal oscillator 10 and generating an output synchronization signal.
[0011]
Reference numeral 12 denotes a vertical synchronization frequency difference detection circuit as vertical synchronization frequency difference detection means for detecting a vertical synchronization frequency difference by inputting a video synchronization signal and comparing it with a predetermined reference frequency value. An AND gate which receives a video synchronizing signal and an output of the vertical synchronizing frequency difference detecting circuit at the other input to generate a reset signal. The reset signal is supplied to the output synchronization signal generation circuit 11.
[0012]
Reference numeral 14 denotes an overlap detection circuit that receives the video synchronization signal, the output of the vertical synchronization frequency difference detection circuit 12, and the video synchronization output that is the output of the output synchronization signal generation circuit 11, and detects an overlap between the write signal and the read signal. A frame memory control signal generator 15 receives the output of the overlap detection circuit 14, the video synchronization signal, and the video synchronization output of the output synchronization signal generation circuit 11 to generate a write and read control signal for the frame memory 1. Circuit.
[0013]
According to such a configuration, when the difference detected by the vertical synchronization frequency difference detection circuit 12 is within the allowable range of the output vertical synchronization frequency, the output synchronization signal generation circuit 11 is reset and synchronized, thereby achieving the frame memory. It is possible to prevent overlapping of writing and reading of an image signal into the memory.
(2) The invention according to claim 2 further comprises means for detecting overlap between writing and reading of the image signal to and from the frame memory, and when the input vertical synchronization frequency exceeds the allowable value of the output vertical synchronization frequency, the overlap occurs. Sometimes, writing of image signals or reading of the same frame is performed in frame units depending on the overlapping direction.
[0014]
Here, the overlapping direction indicates whether the input-side synchronization frequency is earlier or later than the output synchronization frequency.
According to such a configuration, when the overlap detection circuit 14 detects the overlap between the writing and reading of the image signal, the writing of the image signal and the reading of the same frame are performed in units of frames according to the overlapping direction, so that the input vertical synchronization frequency Can be equivalently adjusted to the output vertical synchronization frequency, and image distortion can be prevented.
(3) The invention according to claim 3 is provided with means for calculating an average value of image signals of the respective frame memories, and calculates an average value of image signals of two frames immediately before the occurrence of an overlap in a frame in which an overlap is detected. The image signal of the frame immediately before the occurrence of the overlap in the next frame is read.
[0015]
According to such a configuration, when an overlap is detected by the overlap detection circuit 14, an average value of two frames before the occurrence of the overlap is calculated, and in the next frame, an image signal immediately before the occurrence of the overlap is read, thereby generating an overlap. Disturbance of an image can be prevented by preventing discontinuity of the image.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, details of the principle block diagram shown in FIG. 1 will be described. The control of writing and reading of the image signal to and from the frame memory is performed based on a signal in which the vertical synchronization frequency difference detection circuit 12 detects the frequency difference between the input vertical synchronization signal and the output vertical synchronization signal. Here, the frequency value of the reference output vertical synchronization signal is written in a register of the vertical synchronization frequency difference detection circuit 12 in advance. Therefore, the vertical synchronization frequency difference detection circuit 12 compares the video synchronization input signal with the reference value and outputs the frequency difference.
[0017]
FIG. 2 is a block diagram showing an embodiment of the vertical synchronization frequency difference detection circuit 12. In the figure, reference numeral 20 denotes an output clock generation circuit for generating an output clock. Since the output side clock generation circuit 20 uses a crystal as an oscillator, it can generate a highly accurate clock. Reference numeral 21 denotes a synchronization circuit for synchronizing an input vertical synchronization signal with an output clock of the output side clock generation circuit 20.
[0018]
The output of the synchronizing circuit 21 is frequency-divided by a subsequent frequency-dividing circuit 22. As a result, a pulse with a duty of 50% is generated, which is "H" level for one frame period and "L" level for one frame period. Reference numeral 23 denotes a time measurement counter that receives the output of the divide-by-2 circuit 22 as an enable signal and counts the output clock of the output-side clock generation circuit 20. Reference numeral 24 denotes a window comparator that receives the output of the time measurement counter 23 and the reference frequency value of the output-side synchronization signal as a set value, and outputs a difference between the two frequency values. The window comparator 24 outputs a frequency difference detection signal. The operation of the circuit thus configured will be described as follows.
[0019]
The input vertical synchronization signal is hit by the output of the output side clock generation circuit 20 to be synchronized by the synchronization circuit 21. The input vertical synchronizing signal synchronized by the synchronizing circuit 2 is frequency-divided by 1/2 in the subsequent frequency dividing circuit 22. As a result, a pulse whose width corresponding to one cycle of the frame is at the “H” level is obtained. This pulse is used as an enable signal of the subsequent time counter 23. As a result, the time measurement counter 23 counts the output of the output-side clock generation circuit 20 while the output of the divide-by-2 circuit 22 is at “H” level. This count value becomes the count value of the input-side vertical synchronization frequency, and enters one input of the window comparator 24.
[0020]
On the other hand, a value corresponding to a predetermined allowable range of the output-side vertical synchronization frequency is set as a set value in the other input of the window comparator 24. The window comparator 24 determines the difference between these two frequency values and determines whether the input vertical synchronization frequency is within the allowable range of the output vertical synchronization frequency. Then, the window comparator 24 outputs a frequency difference detection signal. The frequency difference detection signal generates, for example, a signal that becomes “H” level when it is within an allowable range and “L” when it is out of an allowable range.
[0021]
The AND gate 13 ANDs the determination result of the window comparator 24 with the input vertical synchronization signal and inputs the result to the reset input of the output synchronization signal generation circuit 11. When the input vertical synchronization frequency is within the allowable range of the output vertical synchronization frequency, a reset signal is supplied from the AND gate 13 to the output synchronization signal generation circuit 11. As a result, the output synchronization signal is synchronized with the input vertical synchronization signal.
[0022]
FIG. 3 is a diagram showing the relationship between the video synchronization input and the video synchronization output. (A) is a video synchronization input, (b) and (d) are video synchronization outputs, and (c) is a reset signal. Since the video synchronization input signal and the video synchronization output signal are asynchronous, the video synchronization input (a) and the video synchronization output (b) are not synchronized as shown in the figure. Therefore, when a reset signal as shown in (c) synchronized with the video synchronization input signal is given to the output synchronization signal generation circuit 11, the output synchronization signal is synchronized with the reset signal, and therefore, as shown in (d). A video synchronization output synchronized with the input (a) is obtained.
[0023]
When the input vertical synchronization frequency exceeds the allowable range of the output vertical synchronization frequency, an overlap detection circuit 14 is provided to perform the overlap detection and the overlap direction detection, and according to the magnitude relationship between the input vertical synchronization frequency and the output vertical synchronization frequency, the following is shown. Such processing is performed.
[0024]
Hereinafter, the operation of the present invention will be described with reference to a time chart shown in FIG.
(A) When the input vertical synchronization frequency is higher than the output vertical synchronization frequency
4A shows the operation of the output frame, FIG. 4B shows the operation of the input frame, FIG. 4C shows the operation of the frame memory 1, FIG. 4D shows the operation of the frame memory 2, and FIG. The output frame is output as O1, O2, O3,..., And the input frame is input as I1, I2, I3,. Each unit of the frame is shown.
[0025]
In the three frames, writing and reading are sequentially performed as shown in FIG. Here, when the input frame is at the timing of I2, the video signal of the frame I2 is input while the video signal from the frame memory 1 is being read, so that reading and writing overlap (overlapping occurrence Q1). When reading and writing occur in the same frame memory, new and old video data are mixed.
[0026]
Therefore, in this case, the overlap detection circuit 14 detects the overlap and the direction of the overlap. The output of the overlap detection circuit 14 is given to a frame memory control signal generation circuit 15, and the frame memory control signal generation circuit 15 controls writing and reading of the frame memory 1. In this case, priority is given to reading from the frame memory 1, and writing of the video signal of the frame I2 is prohibited.
[0027]
Then, the video signal of the frame I3 is written into the frame memory 1 at the timing of the input frame I3 (W3), and the frequency difference between the input and output is adjusted so as not to take in one frame of the video input signal of the input frame I2.
[0028]
Note that the overlap also occurs in the overlap occurrence Q2, but this case shows a case where the video signal of the frame I7 is input while the video signal is being read from the frame memory 2. Also in this case, as in the case of the overlap Q1, the writing of the frame I7 is prohibited, and the video signal of the next frame I8 is written.
[0029]
As described above, when the overlap detection circuit 14 detects the overlap between the writing and reading of the video signal, the input vertical synchronization frequency is equivalently changed to the output vertical synchronization frequency by prohibiting the writing of the video signal in frame units according to the overlapping direction. Can be adjusted to prevent image disturbance.
(B) When the input vertical synchronization frequency is lower than the output vertical synchronization frequency
It is assumed that an overlap has occurred in Q3. In this case, the frame memory 1 is writing video data. During the writing of the video data, the data reading overlaps. Therefore, in this case, the overlap detection circuit 14 detects the overlap and the direction of the overlap. The output of the overlap detection circuit 14 is given to a frame memory control signal generation circuit 15, and the frame memory control signal generation circuit 15 controls writing and reading of the frame memory 1. In this case, the writing of the video data in the frame memory 1 is prioritized. In this frame, the video signal is read from the frame memory 3 in which the video signal of the previous frame is stored, and the same image of one frame is inserted. Thus, the difference between the input vertical synchronization frequency and the output vertical synchronization frequency can be adjusted.
[0030]
Note that the overlap occurs also in the overlap occurrence Q4, but in this case, the image data is being written in the frame memory 3. During the writing of the video data, the data reading overlaps. Therefore, in this case, the overlap detection circuit 14 detects the overlap and the direction of the overlap. The output of the overlap detection circuit 14 is given to a frame memory control signal generation circuit 15, and the frame memory control signal generation circuit 15 controls writing and reading of the frame memory 1. In this case, the writing of the video data in the frame memory 3 is prioritized. In this frame, the video signal is read from the frame memory 2 in which the video signal of the previous frame is stored, and the same image of one frame is inserted.
[0031]
As described above, when the overlap detection circuit 14 detects the overlap between the writing and the reading of the image signal, the same vertical frame of the image signal is read out by reading the same frame of the image signal in the unit of the frame according to the overlapping direction. The frequency can be adjusted to the synchronization frequency, and image distortion can be prevented.
[0032]
FIG. 5 is a diagram illustrating a specific configuration example of the overlap detection circuit 14. In the figure, a write pulse and a read pulse are generated in an overlap detection circuit 14 by receiving an output of a vertical synchronization frequency difference detection circuit 12, a video synchronization signal input, and an output of an output synchronization signal generation circuit 11. Thus, a write timing (write) pulse and a read timing (read) pulse for the frame memory are created. The overlap detection circuit 14 includes an overlap detection unit 1 and an overlap detection unit 2.
[0033]
In the overlap detection unit 1, an AND gate 30 receives a write pulse at one input, an inverted signal of a read pulse at the other input, and 31 an inverted signal of a write pulse at one input and the other input. The AND gate 32 receives a read pulse at one input and a read pulse at the other input. Reference numeral 33 denotes a D-type flip-flop (hereinafter abbreviated as FF1) which receives the "H" level of the power supply Vcc at its D input, the output of the AND gate 30 at the clock input CLK, and the output of the AND gate 31 at the clear input CLR. . An AND gate 34 receives the Q output of the FF 1 at one input and the output of the AND gate 32 at the other input. Here, the output of the AND gate 32 is referred to as a point A signal. An overlap pulse 1 is output from the AND gate 34. This overlap pulse is output when the input synchronization frequency Fin <the output synchronization frequency Fout.
[0034]
In the overlap detection unit 2, an AND gate 35 receives an inverted signal of a write pulse at one input, a read pulse at the other input, and a write pulse at one input and a read pulse at the other input. AND gate that receives the inverted signal of Reference numeral 37 denotes a D-type flip-flop (hereinafter abbreviated as FF2) which receives the "H" level of the power supply Vcc at its D input, the output of the AND gate 35 at the clock input CLK, and the output of the AND gate 36 at the clear input CLR. An AND gate 38 receives the point A signal at one input and the Q output of the FF2 at the other input. The overlap pulse 2 is output from the AND gate 38. This overlap pulse is output when the input synchronization frequency Fin> the output synchronization frequency Fout.
[0035]
The operation of the circuit thus configured will be described with reference to a time chart. FIG. 6 is a time chart showing the operation of the overlap detection unit 1, and FIG. 7 is a time chart showing the operation of the overlap detection unit 2. In the case where the input synchronization frequency Fin <the output synchronization frequency Fout, the writing is gradually delayed, so that the leading edge of the read pulse and the trailing edge of the write pulse overlap, and in the case of the input synchronization frequency Fin> the output synchronization frequency Fout, Since the reading is gradually delayed, the leading edge of the writing pulse and the trailing edge of the reading pulse overlap. That is, the overlapping direction is determined by the magnitude relationship between the input synchronization frequency and the output synchronization frequency.
[0036]
In each case, (a) is an output frame, (b) is a read pulse, (c) is a write pulse, (d) is a clock signal of FF1, (e) is a clear signal of FF1, and (f) is Q of FF1. The output, (g), is the point A signal.
[0037]
In the case of the overlap detection unit 1 shown in FIG. 6, when the input synchronization frequency Fin <the output synchronization frequency Fout as described above, the writing is gradually delayed, so that the leading edge of the reading pulse and the trailing edge of the writing pulse are different from each other. Overlap as shown at point Q10. Before the overlap, as shown in the figure, there is no section in which both the read pulse and the write pulse are at the “H” level, so that the point A signal is not generated.
[0038]
On the other hand, when the overlap occurs as shown in Q10, the output (point A signal) of the AND gate 32 becomes “H” level as shown in FIG. While the point A signal is at the "H" level, the Q output of the FF1 is at the "H" level, so that the point A signal passes through the AND gate 34 and is output as the overlap pulse 1.
[0039]
In the case of the overlap detection unit 2 shown in FIG. 7, when the input synchronization frequency Fin> the output synchronization frequency Fout, reading is gradually delayed, so that the leading edge of the writing pulse and the trailing edge of the reading pulse overlap. Before the overlap, as shown in the figure, there is no section in which both the read pulse and the write pulse are at the “H” level, so that the point A signal is not generated.
[0040]
On the other hand, as shown in Q11, when an overlap occurs, the output (point A signal) of the AND gate 32 becomes "H" level as shown in FIG. While the point A signal is at the “H” level, the Q output of the FF 1 is at the “H” level, so that the point A signal passes through the AND gate 34 and is output as the overlap pulse 2.
[0041]
The frame memory control signal generation circuit 15 of FIG. 1 receives the signals of the overlap pulse 1 and the overlap pulse 2 as described above, and performs write control and read control of the frame memory 1, and outputs the image signal in frame units according to the overlap direction. Write inhibition and reading of the same frame are performed. With such control, it is possible to prevent an overlap between writing and reading of the image signal to and from the frame memory, and to provide an image signal asynchronous processing device in which the image is not disturbed.
[0042]
FIG. 8 is a block diagram showing one embodiment of the present invention. 1 are denoted by the same reference numerals. In the figure, 1 is a frame memory, 10 is a crystal oscillator, 11 is an output synchronization signal generation circuit, 12 is a vertical synchronization frequency difference determination circuit, 13 is an AND gate 13, an overlap detection circuit, and 15 is a frame memory control signal generation circuit. is there. Since these components have been described with reference to FIG. 1, detailed description of their connection and the like will be omitted.
[0043]
Reference numeral 16 denotes an average value calculation circuit for receiving outputs of the frame memories 1 to 3 and calculating an average value of these outputs. The average value calculating circuit 16 may be configured to perform an arithmetic processing by software in addition to an arithmetic circuit by hardware. Reference numeral 17 denotes whether to select the output of the frame memories 1 to 3 or the output of the average value calculation circuit 16 in response to the outputs of the frame memories 1 to 3 and the output of the average value calculation circuit 16. This is a switching circuit for switching. A video signal is output from the switching circuit 17. The operation of the circuit thus configured will be described below with reference to a time chart shown in FIG.
[0044]
FIG. 9 is a time chart showing the operation of each unit of the embodiment. (A) is an output frame, (b) is an input frame, (c) is an operation of the frame memory 1, (d) is an operation of the frame memory 2, (e) is an operation of the frame memory 3, and (f) is an operation of the frame memory 3. Each output image is shown.
[0045]
First, the operation of the embodiment will be described. At the beginning of each output frame, the overlap detection circuit 14 determines whether or not a read has occurred with respect to the frame memory where the write is currently being performed. At the same time, reading is also performed from the frame memory in which the video signal of the previous frame is stored, the average value calculating circuit 16 calculates the average value of the video signals of the two frames, and outputs the average video signal. Then, in the next frame after outputting the average value video signal, the image signal of the frame immediately before the occurrence of the overlap is read.
[0046]
FIG. 9 shows the operation at that time. In the output frame O2 where the overlap (Q20) occurs, the video R0 of the frame memory 3 storing the video signal of the previous frame and the video signal R1 from the frame memory 1 storing the video signal of the current frame. , And the two-frame video signal is input to the average value calculation circuit 16 to generate an average value video signal. The average value is obtained by (R0 + R1) / 2.
[0047]
In the frame where the overlap occurs, the switching circuit 17 selects the average value calculation circuit 16 side, so that the average value video signal is output as a video signal via the switching circuit 17. Then, in the next frame O3 in which the overlap has occurred, the video signal R1 of the frame immediately before the occurrence of the overlap is read.
[0048]
According to this embodiment, when the overlap is detected by the overlap detection circuit 14, the average value of two frames before the occurrence of the overlap is calculated, and the image signal immediately before the occurrence of the overlap is read in the next frame, so that when the overlap occurs, Disturbance of the image can be prevented by preventing the resulting discontinuity of the image.
[0049]
In the above-described embodiment, the case where a video signal is used as an image signal is taken as an example. However, the present invention is not limited to this, and any type of image signal may be used. Can be applied to
[0050]
Further, in the above-described embodiment, the case where the number of the frame memories is three is described, but the present invention is not limited to this, and can be applied to the case where the number of the frame memories is four or more.
[0051]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
(1) According to the first aspect of the invention, when the difference detected by the vertical synchronization frequency difference detection circuit is within the allowable range of the output vertical synchronization frequency, the output synchronization signal generation circuit is reset and synchronized. In addition, overlapping of writing and reading of an image signal to and from the frame memory can be prevented.
(2) According to the second aspect of the invention, when the overlap detection circuit detects the overlap between the writing and reading of the image signal, the writing of the image signal is prohibited in the frame unit and the same frame is read in the overlapping direction. The input vertical synchronizing frequency can be equivalently adjusted to the output vertical synchronizing frequency, and image distortion can be prevented.
(3) According to the third aspect of the invention, when an overlap is detected by the overlap detection circuit, an average value of two frames before the occurrence of the overlap is calculated, and an image signal immediately before the occurrence of the overlap is read in the next frame, It is possible to prevent discontinuity of an image that occurs at the time of occurrence of overlap, thereby preventing image disturbance.
[0052]
As described above, according to the present invention, it is possible to provide an image signal asynchronous processing device that prevents overlapping of writing and reading of an image signal into and from a frame memory and that does not disturb the image.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the present invention.
FIG. 2 is a block diagram showing an embodiment of a vertical synchronization frequency difference detection circuit.
FIG. 3 is a time chart showing a relationship between a video synchronization input and a video synchronization output.
FIG. 4 is a time chart illustrating an operation of each unit of the circuit illustrated in FIG. 1;
FIG. 5 is a diagram illustrating a specific configuration example of an overlap detection circuit.
FIG. 6 is a time chart illustrating an operation of the overlap detection unit 1;
FIG. 7 is a time chart illustrating an operation of the overlap detection unit 2.
FIG. 8 is a block diagram showing an embodiment of the present invention.
FIG. 9 is a time chart showing the operation of each unit of the embodiment.
FIG. 10 is a block diagram illustrating a configuration example of a conventional device.
FIG. 11 is a time chart of writing to and reading from a frame memory.
FIG. 12 is an explanatory diagram of overlap between a write pulse and a read pulse.
[Explanation of symbols]
1 frame memory
10 Crystal oscillator
11 Output synchronization signal generation circuit
12. Vertical synchronization frequency difference detection circuit
13 And Gate
14 Overlap detection circuit
15 Frame memory control signal generation circuit

Claims (3)

In an apparatus for converting an image signal from an imaging system having a different vertical synchronization frequency into a predetermined image signal having a different vertical synchronization frequency,
A plurality of frame memories for writing and reading image signals;
Vertical synchronization frequency difference detection means for detecting a frequency difference between a vertical synchronization signal of the image input signal and the image output signal,
Output synchronization signal generating means for receiving an output of the reference oscillator and generating an image synchronization signal,
Receiving an output of the vertical synchronization frequency difference detection means and an output of the output synchronization signal generation means, and providing a frame memory control means for controlling writing and reading of the frame memory;
If the input vertical synchronizing frequency is within an allowable value of the output vertical synchronizing frequency, the output synchronizing signal generating means is reset to perform synchronization. Providing means for detecting overlap of writing and reading of image signals to the frame memory,
2. The image signal according to claim 1, wherein when the input vertical synchronizing frequency exceeds an allowable value of the output vertical synchronizing frequency, when an overlap occurs, the writing of the image signal is prohibited or the same frame is read in frame units depending on the overlapping direction. Asynchronous processing unit. Providing means for calculating an average value of the image signal of each frame memory,
2. The asynchronous processing of an image signal according to claim 1, wherein an average value of the image signals of two frames immediately before the occurrence of the overlap is calculated in the frame in which the overlap is detected, and the image signal of the frame immediately before the occurrence of the overlap is read in the next frame. apparatus.

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