JP3876794B2 - Vertical sync signal processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a vertical synchronization signal processing circuit, and more particularly to a vertical synchronization signal processing circuit for processing a vertical synchronization signal of a non-standard television signal when a VTR is played back at a variable speed.
[0002]
[Prior art]
In the video display system that performs processing based on the synchronization signal, the discrimination of the odd / even field is performed depending on whether the change point of the vertical synchronization signal VSYNC is near or in the middle of the horizontal synchronization signal HSYNC. In order to realize this, for example, in the case of using a counter that is reset by the vertical synchronization signal VSYNC and counts 1H (H is a horizontal scanning period; hereinafter, sometimes referred to as “1 line”), FIG. As shown, a method is used in which a window of 25% to 75% of 1H is created, and the field is discriminated depending on whether or not the horizontal synchronization signal HSYNC is present in this window. This also determines the position of the vertical start pulse in each field.
[0003]
[Problems to be solved by the invention]
By the way, as shown in FIG. 10, in the non-standard television signal when the VTR is played back at a variable speed, one line from the timing (near or in the middle of the horizontal sync signal) at which the change point of the vertical sync signal VSYNC is assumed. May be around 25% or more. For this reason, in the conventional technique in which a window of 25% to 75% of 1H is created and the field is discriminated depending on whether or not the horizontal synchronization signal HSYNC is present in this window, the field is erroneously discriminated, and the display image is displayed on the display. It will vibrate up and down. In addition, in a system that performs thinning display, the thinned line differs for each field, so that the wrong line is thinned out.
[0004]
The present invention has been made in view of the above problems, and the object of the present invention is to cause a display image to vibrate up and down on a display or a field with respect to a non-standard television signal when a VTR is played back at a variable speed. It is an object of the present invention to provide a vertical synchronizing signal processing circuit that prevents erroneous determination of the above.
[0005]
[Means for Solving the Problems]
The vertical synchronization signal processing circuit according to the present invention performs a counting operation at a frequency twice the horizontal scanning frequency, and is reset by a first counter that counts the number of lines in the field, and a count result of the first counter, Based on the second counter that performs a counting operation at a frequency twice the horizontal scanning frequency and the count result of the second counter, it is possible to determine a special mode in which a non-standard television signal is input. A mode discriminating unit that performs in synchronization with an input vertical synchronizing signal, a field information generating unit that predicts a next field based on past field information from the count result of the second counter, and a discriminating unit of the mode discriminating unit When the result is the special mode, the field information generating means predicts based on the count result of the second counter. It has a configuration in which a correction vertical synchronizing signal generator for generating a correction vertical synchronizing signal by performing processing corresponding to the fields.
[0006]
In the vertical sync signal processing circuit configured as described above, in the special mode in which a non-standard television signal is input, the next field is predicted based on past field information, and processing corresponding to the field is performed. By generating a corrected vertical synchronization signal, stable vertical operation can be achieved even when the change point of the vertical synchronization signal VSYNC is assumed to be about 25% or more of 1H from the timing (near or in the middle of the horizontal synchronization signal HSYNC). A synchronization signal is obtained.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0008]
FIG. 1 is a block diagram showing a configuration example of a vertical synchronization signal processing circuit according to an embodiment of the present invention. As apparent from FIG. 1, the vertical synchronization signal processing circuit according to the present embodiment includes a synchronization separation circuit 11, a noise processing circuit 12, a detection processing circuit 13, and a correction processing circuit 14.
[0009]
The synchronization separation circuit 11 separates the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC from the input video signal. The vertical synchronization signal VSYNC is input to the noise processing circuit 12. The noise processing circuit 12 includes an AND circuit 121, a window generation circuit 122, and a selector 123. The AND circuit 121 has the vertical synchronization signal VSYNC as one input and the window 1 generated by the window generation circuit 122 as the other input. The window generation circuit 122 generates the window 1 having a width before and after the field period of the standard television signal, for example, 90% to 110%.
[0010]
The AND circuit 121 obtains the logical product of the vertical synchronization signal VSYNC and the window 1 so as to pass only the vertical synchronization signal VSYNC in the window 1 and masks the others. Thereby, noise included in the vertical synchronization signal VSYNC can be removed. The selector 123 receives the vertical synchronization signal VSYNC and the output signal of the AND circuit 121 as selection inputs, selects one of them according to the mode signal given from the mode generation circuit 15 and outputs it.
[0011]
The mode generation circuit 15 outputs a mode signal corresponding to each of a normal mode, a no-signal mode, and a special mode (these modes will be described later). The selector 123 selects and outputs the vertical synchronization signal VSYNC when a mode signal indicating the no-signal mode is supplied from the mode generation circuit 15, and when the mode signal indicating the normal mode and the special mode is supplied, the selector 123 Select the output signal and output it.
[0012]
That is, the noise processing circuit 12 does not perform mask processing in the no-signal mode. This is because when the vertical synchronization signal VSYNC is input, the mode shifts from the no-signal mode to the special mode, as will be described later. This is because there is a possibility that it cannot be transferred to. In the window generation circuit 122, the width of the window 1 may be changed between the special mode and the normal mode.
[0013]
The vertical synchronization signal VSYNC that has passed through the noise processing circuit 12 is input to the detection processing circuit 13. The detection processing circuit 13 has a configuration in which an up / down counter 131 and a decoder 132 are arranged in that order. Only a signal having a certain pulse width or more is regarded as a vertical synchronization signal VSYNC, and a vertical synchronization signal detection pulse vres is output. To do. As a result, noise in the window 1 that could not be removed by the noise processing circuit 12 in the previous stage can be more reliably removed.
[0014]
In this noise removal processing, an up / down counter 131 is used. As a result, the influence of noise mixed in the vertical synchronization signal VSYNC can be ignored. However, the output timing of the vertical synchronization signal detection pulse vres is n lines after the change point of the vertical synchronization signal VSYNC (n is an integer), for example, after 2 lines.
[0015]
The horizontal synchronization signal HSYNC separated by the synchronization separation circuit 11 is input to the correction processing circuit 14. The correction processing circuit 14 includes a PLL (Phase Locked Loop) circuit 21, a decoder 22, OR circuits 23A and 23B, a counter 24, a decoder 25, a counter 26, a decoder 27, a window generation circuit 28, a mode determination circuit 29, and a field information generation circuit. 30 and a corrected vertical synchronizing signal generation circuit 31.
[0016]
The PLL circuit 21 and the decoder 22 generate 0%, 25%, 50%, and 75% signals of 1H based on the horizontal synchronization signal HSYNC. The OR circuit 23A takes a logical sum of the 0% signal and the 50% signal. The OR circuit 23B takes a logical sum of a 25% signal and a 75% signal. The OR signal of the OR circuit 23A is input to the corrected vertical synchronization signal generation circuit 31. The OR signal of the OR circuit 23B is input to the first and second counters 24 and 26 as hsync2. The logical sum signal hsync2 has the frequency of the horizontal synchronization signal HSYNC, that is, twice the horizontal scanning frequency.
[0017]
The counter 24 is reset by a correction vertical synchronization signal (hereinafter referred to as “correction vres”), which will be described later, generated by the correction vertical synchronization signal generation circuit 31, and is synchronized with the logical sum signal hsync2, that is, 2 of the horizontal scanning frequency. The number of lines in the field is counted by performing a counting operation at a double frequency. The count result of the counter 24 is given to the counter 26 via the decoder 25.
[0018]
The counter 26 is reset by the count result of the counter 24, and performs a count operation in synchronization with the logical sum signal hsync2, that is, at a frequency twice the horizontal scanning frequency. The count result of the counter 26 is given to the window generation circuit 28, the field information generation circuit 30, and the corrected vertical synchronization signal generation circuit 31 through the decoder 27, respectively.
[0019]
Based on the count result of the counter 26, the window generation circuit 28 generates a mode determination window used in the mode determination circuit 29 in the next stage. The mode determination circuit 29 performs mode determination in synchronization with the vertical synchronization signal detection pulse vres given from the detection processing circuit 13 using the mode determination window generated by the window generation circuit 28. The field information generation circuit 30 generates field information in synchronization with the vertical synchronization signal detection pulse vres based on the count result of the counter 26. The corrected vertical synchronization signal generation circuit 31 generates a corrected vertical synchronization signal (correction vres) based on the count result of the counter 26, the determination result of the mode determination circuit 29, and the generation information in the field information generation circuit 30.
[0020]
FIG. 2 is a timing chart of the mode determination window generation in the window generation circuit 28. The window generation circuit 28 generates three windows, first, second, and third windows 2, 3, and 4. Window 2 is a window showing the same cycle as the standard television signal. If the width of the window 2 is 1 / 2H and the television signal has one field of 262.5 lines, this is the case when the counter 24 counts 525, which is twice.
[0021]
Window 3 is a window showing the vicinity of the standard television signal period. As the width of the window 3, a width of 1 / 2H or the like is set before and after the window 2, for example. Window 4 is a window indicating that it is deviated from the standard television signal cycle. As the width of the window 4, for example, an area outside the window 3 up to an area where the vertical synchronization signal VSYNC is not masked is set.
[0022]
The mode discriminating circuit 29 discriminates between the normal mode, special mode and no signal mode. Here, the normal mode represents a state in which a standard television signal is input. The special mode represents a state in which a non-standard television signal is input. The no-signal mode represents a state where the vertical synchronization signal VSYNC is not input. The mode generation circuit 15 described above outputs a mode signal indicating each mode based on the determination result of the mode determination circuit 29.
[0023]
FIG. 3 is a state transition diagram of each mode of the normal mode, the special mode, and the no-signal mode. When the power is turned on, for example, it starts from the special mode. When the mode discrimination circuit 29 continuously detects the vertical synchronization signal detection pulse vres output from the detection processing circuit 13 within the specified number of times in the window 2 in the special mode state, the input vertical synchronization signal VSYNC is a standard television signal. Assuming there is a transition to normal mode. The prescribed number of times here is, for example, four times.
[0024]
In the normal mode state, the mode determination circuit 29 regards the input vertical synchronization signal VSYNC as a standard television signal and maintains the normal mode state when the vertical synchronization signal detection pulse vres is detected in the window 2. . On the other hand, when the vertical synchronization signal detection pulse vres is detected outside the window 2 in the normal mode state, the mode discrimination circuit 29 regards the input vertical synchronization signal VSYNC as a non-standard television signal, and is basically special. Enter mode.
[0025]
However, when the mode discrimination circuit 29 detects the vertical synchronization signal detection pulse vres in the window 3, it does not immediately shift to the special mode. This is because the case where the vertical synchronization signal VSYNC has jitter or is slightly deviated from the period of the standard television signal due to the influence of some noise or the like is ignored. For this reason, when the vertical synchronization signal detection pulse vres is detected in the window 3, the mode shifts to the special mode after a predetermined waiting period has elapsed.
[0026]
Here, in order to set a predetermined waiting period, for example, an up / down counter is used. When the vertical synchronization signal detection pulse vres is detected in the window 2, the up / down counter is counted down. When the vertical synchronization signal detection pulse vres is detected in the window 3, the up / down counter is counted up. When (for example, MSB = 1), the mode is shifted to the special mode.
[0027]
In the normal mode or the special mode, the mode determination circuit 29 receives the vertical synchronization signal VSYNC when the vertical synchronization signal detection pulse vres is not continuously detected within the predetermined number of windows 2 to 4. It is assumed that it is not, and shifts to the no signal mode. The prescribed number of times here is, for example, three times. The reason why the mode does not immediately shift to the no-signal mode when the vertical synchronization signal detection pulse vres is not detected is that the vertical synchronization signal may be lost due to the influence of a weak electric field or noise, and this state is not determined as no signal. It is for doing so.
[0028]
In the no-signal mode state, the mode determination circuit 29 shifts to the special mode when detecting the vertical synchronization signal detection pulse vres regardless of the inside or outside of the windows 2 to 4.
[0029]
FIG. 4 is a block diagram illustrating an example of a specific configuration of the field information generation circuit 30. The field information generation circuit 30 is a circuit that predicts the next field from past field information.
[0030]
In the vertical synchronization signal VSYNC, there are a case where only one field (odd field or even field) exists and a case where both fields (odd field and even field) exist. In the case of a vertical sync signal of only one field, the number of lines included in one field is an integer. In the case of a vertical synchronizing signal having both fields, the number of lines included in one field is not an integer, but includes ½ line. For example, there are 262 lines for one field and 262.5 lines for both fields.
[0031]
The field information and the field prediction result in the field information generation circuit 30 are information indicating whether the vertical synchronization signal is one field or both fields. The field information generation circuit 30 includes a field information generation unit 41 and a field prediction generation unit 42.
[0032]
The field information generation unit 41 includes a counter 411, a decoder 412 and a D-type flip-flop 413. The counter 411 is reset by the vertical synchronization signal detection pulse vres and counts the horizontal scanning period. Based on the count result of the counter 411, the decoder 412 generates a window 5 that is 25% to 75% of 1H based on the horizontal synchronization signal HSYNC.
[0033]
The D-type flip-flop 413 receives the window 5 as a D (data) input, the vertical synchronization signal detection pulse vres as an en (enable) input, and when the vertical synchronization signal detection pulse vres is within the window 5, the vertical synchronization signal VSYNC is both When the vertical synchronization signal detection pulse vres is outside the window 5, the vertical synchronization signal VSYNC is regarded as one field, and this determination result is output as field information S2.
[0034]
The field prediction generation unit 42 includes an up / down counter 421 and a decoder 422. The up / down counter 421 counts up / down the field information S2 generated by the field information generating unit 41. For example, it counts up for one field and counts down for both fields. Then, the count value of the up / down counter 421 is given to the decoder 422.
[0035]
The decoder 422 has a certain threshold value, and outputs a field prediction result S3 depending on whether the count value of the up / down counter 421 is above or below the threshold value. Specifically, when the MSB of the up / down counter 421 is logic “1”, one field is predicted, and when the MSB is logic “0”, both fields are predicted and the field prediction result S3 is output.
[0036]
When the vertical synchronization signal VSYNC is not input, the field information generation circuit 30 does not update the field information S2 and the field prediction result S3, but retains the previous information.
[0037]
FIG. 5 is a timing chart for generating a corrected vertical synchronizing signal (corrected vres) in the normal mode and the no-signal mode in the correction processing circuit 14. The circuit operation of the correction processing circuit 14 when generating the correction vres in the normal mode and the no-signal mode will be described below using this timing chart.
[0038]
The PLL circuit 21 and the decoder 22 generate 0% and 50% signals of one line based on the horizontal synchronization signal HSYNC. The logical sum of these signals is taken by the OR circuit 23A, and the logical sum output is taken as a signal S1. A correction vres is generated at the timing of the signal S1. Since this correction vres has a position in the time axis direction in the vicinity of or in the middle of the horizontal synchronization signal HSYNC, field discrimination and the like in the subsequent stage can be performed stably.
[0039]
In the no-signal mode, the vertical synchronization signal detection pulse vres is not input, so that the correction vres is generated by using the count result of the counter 26 and the signal S1. Thereby, the correction | amendment vres of arbitrary periods can be produced | generated. Further, if the correction vres is generated using the window 2 and the signal S1, the correction vres can be generated with the cycle of the standard television signal even in the no-signal mode.
[0040]
In the case of the standard mode, the correction vres is generated using the window 2 and the signal S1. Thereby, even if the vertical synchronization signal VSYNC includes jitter, a stable correction vres can be generated. Further, even if the vertical synchronization signal VSYNC is lost due to weak electric field or noise, a stable correction vres can be generated.
[0041]
6 to 8 are timing charts for generating a correction vres in the special mode in the correction processing circuit 14. The circuit operation of the correction processing circuit 14 when generating the correction vres in the special mode will be described below using these timing charts.
[0042]
First, as shown in the timing chart of FIG. 6, the PLL circuit 21 and the decoder 22 generate a window 6 and a window 7 having a constant width before and after the horizontal synchronization signal hsync2. These windows 6 and 7 are set to a width of 5% of 1H, for example. These windows are generated for the purpose of detecting that the vertical synchronization signal VSYNC is shifted by about 25% of 1H from the normal timing.
[0043]
Further, as shown in the timing chart of FIG. 8, the signal S4 indicating the range in which the vertical synchronization signal detection pulse vres is supposed to be input is generated by using the LSB of the counter 26 and the field prediction result S3 described above. From the field prediction result S3, it can be determined whether the next vertical synchronizing signal is a signal of only one field or a signal including both fields.
[0044]
In the case of one field, the number of lines included in one field is an integer. Since the counter 24 counts at a frequency twice the horizontal scanning frequency, the vertical synchronization signal detection pulse vres is input when the count value of the counter 24 is an even number. In both fields, since the number of lines included in one field includes ½ line, the vertical synchronization signal detection pulse vres is input when the count value of the counter 24 is an odd number. By utilizing this property, the signal S4 is generated.
[0045]
FIG. 8 shows an example where both fields are expected. The signal S1 within a range (within S4) where the vertical synchronization signal detection pulse vres is supposed to be input is assumed to be a signal S5. When the vertical synchronization signal detection pulse vres is detected outside the window 6 and the window 7, as shown in the timing chart of FIG. 7, the input vertical synchronization signal detection pulse vres is directly used as the correction vres.
[0046]
When the vertical synchronization signal detection pulse vres is detected in the window 6 or the window 7, the correction vres is generated at the timing of the next signal S5. Although the counter 24 is reset by the correction vres, there is no problem in the case of B in the timing chart of FIG. 8, but in the case of A, the counter 24 is delayed by one line from the timing of the correction vres that is originally generated. Therefore, it is necessary to consider this when resetting the counter 24. This also needs to be taken into account when the correction vres is used later.
[0047]
Since the generated correction vres has a position in the time axis direction in the vicinity of or in the middle of the horizontal synchronization signal HSYNC, field discrimination and the like in the subsequent stage can be performed stably.
[0048]
As described above, in the vertical synchronization signal processing circuit according to the present embodiment, in the special mode in which a non-standard television signal is input, the next field is predicted based on past field information. Since the correction vertical synchronizing signal is generated by performing the processing corresponding to the field, 25 of 1H from the timing at which the change point of the vertical synchronizing signal VSYNC is assumed (in the vicinity of the horizontal synchronizing signal HSYNC or in the middle thereof). A stable vertical synchronization signal VSYNC can be obtained even when the ratio is more than about%.
[0049]
Therefore, by using the vertical synchronization signal processing circuit according to this embodiment, a stable vertical synchronization signal VSYNC is provided for both a stable standard television signal and an unstable non-standard television signal. be able to. That is, whether a standard television signal, non-standard television signal or no signal, even if the vertical synchronization signal VSYNC is out of phase with the horizontal synchronization signal HSYNC, or an unstable synchronization signal such as in a weak electric field, A stable vertical synchronization signal VSYNC can be obtained by appropriately adjusting the width of each window and the counter.
[0050]
Also, a stable vertical synchronization signal VSYNC can be obtained by appropriately adjusting the width of each window and the counter for various image display devices and various input television signal formats. Furthermore, a stable vertical synchronization signal VSYNC can be obtained by appropriately adjusting the width and counter of each window and the like for a system that displays an image using a synchronization signal regardless of the television signal. .
[0051]
【The invention's effect】
As described above, according to the present invention, in the special mode in which a non-standard television signal is input, the next field is predicted based on past field information, and the corresponding field is supported. When the corrected vertical sync signal is generated by performing the process, the change point of the vertical sync signal VSYNC is about 25% or more of 1H from the assumed timing (near or in the middle of the horizontal sync signal HSYNC) However, a stable vertical synchronization signal can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a vertical synchronization signal processing circuit according to an embodiment of the present invention.
FIG. 2 is a timing chart of mode determination window generation in the window generation circuit.
FIG. 3 is a state transition diagram of each of a normal mode, a special mode, and a no-signal mode.
FIG. 4 is a block diagram showing an example of a specific configuration of a field information generation circuit.
FIG. 5 is a timing chart of generation of corrected vres in a normal mode and a no-signal mode in a corrected vertical synchronization signal generation circuit.
FIG. 6 is a timing chart (part 1) for generating a corrected vres in the special mode in the corrected vertical synchronization signal generating circuit.
FIG. 7 is a timing chart (part 2) for generating corrected vres in the special mode in the corrected vertical synchronization signal generating circuit.
FIG. 8 is a timing chart (part 3) for generating corrected vres in the special mode in the corrected vertical synchronization signal generating circuit;
FIG. 9 is a timing chart showing a window used for discrimination between an odd field / even field in the related art.
FIG. 10 is a timing chart for explaining a problem of the conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Sync separation circuit, 12 ... Noise removal circuit, 13 ... Detection processing circuit, 14 ... Correction processing circuit, 21 ... PLL circuit, 28 ... Window generation circuit, 29 ... Mode discrimination circuit, 30 ... Field information generation circuit, 31 ... Correction vertical synchronizing signal generation circuit, 41... Field information generation unit, 42.

Claims (6)

A first counter that performs a counting operation at a frequency twice the horizontal scanning frequency and counts the number of lines in the field;
A second counter that is reset by a counting result of the first counter and performs a counting operation at a frequency twice the horizontal scanning frequency;
Based on the count result of the second counter, mode discrimination means for discriminating a special mode in a state where a non-standard television signal is input in synchronization with the input vertical synchronization signal;
Field information generating means for predicting the next field based on past field information from the count result of the second counter;
When the discrimination result of the mode discrimination means is the special mode, a correction vertical synchronization signal is generated by performing processing corresponding to the field predicted by the field information generation means based on the count result of the second counter A vertical synchronizing signal processing circuit comprising: a corrected vertical synchronizing signal generating means for performing The mode discriminating unit discriminates, in addition to the special mode, a normal mode in which a standard television signal is input and a no-signal mode in which a vertical synchronization signal is not input,
The corrected vertical synchronizing signal generating means corrects the same period as the standard television signal from the count result of the second counter when the discrimination result of the mode discrimination means is the normal mode and the no-signal mode. 2. The vertical synchronization signal processing circuit according to claim 1, wherein the vertical synchronization signal is generated. The mode discriminating means includes a first window indicating the same period as the standard television signal, a second window indicating the vicinity of the standard television signal period, and a third window indicating deviation from the standard television signal period. Create a window
When the vertical synchronization signal detection pulse is continuously detected within the first window in the special mode in the special mode, the normal mode is entered.
If the vertical synchronization signal detection pulse is detected outside the first window during the normal mode, the mode is shifted to the special mode.
Transition to the no-signal mode when the vertical synchronization signal detection pulse is not detected within the first, second, and third windows continuously in the normal mode or in the special mode. The vertical synchronizing signal processing circuit according to claim 2. When the mode discrimination means detects the vertical synchronization signal detection pulse outside the first window in the normal mode and within the second window, the mode discrimination means 4. The vertical synchronization signal processing circuit according to claim 3, wherein the vertical synchronization signal processing circuit shifts to a special mode. The field information generation means generates field information indicating whether the input vertical synchronization signal has only one field or both fields in synchronization with the vertical synchronization signal detection pulse, and the field information The vertical synchronization signal processing circuit according to claim 1, further comprising: a field prediction generation unit that predicts a next field from past field information using the field information generated by the generation unit. 2. The vertical synchronization signal processing circuit according to claim 1, further comprising noise processing means for performing noise removal processing on the input vertical synchronization signal.

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