JP2004140619A - Clock transfer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a hardware amount of a clock transfer circuit without setting phases of a writing clock and a reading clock. <P>SOLUTION: A low-order writing address 13 and a high-order writing address 14 are sent by a writing frame pulse signal 11 and a writing clock signal 12 so as to write input data 10 into a 2-port RAM 1. The RAM 1 secures an address area of n fames. A reading control unit 4 generates a high-order reading address 24, based on a reading control signal 30 and the high-order writing address 14. A low-order reading address 23 and the high-order reading address 24 from the reading control unit 4 are sent by a reading frame pulse signal 21 and a reading clock signal 22 as output data 20 from the RAM 1. Since reading areas are generated so as not to overlap by determining writing areas, an interval between writing and reading can be fully held. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock transfer circuit for digital asynchronous transfer mode communication, and more particularly to a clock transfer circuit that enables data transmission and reception between circuits operating in response to a clock signal and a frame pulse signal that are independent of each other.
[0002]
[Prior art]
Conventionally, this type of clock transfer circuit manages clock phases between circuits that operate in response to mutually independent clock signals, thereby avoiding contention between writing and reading to the same memory (for example, And Patent Document 1).
[0003]
FIG. 7 is a block diagram showing an example of the clock transfer circuit. 7, a system control unit 400 outputs a write clock 12, a read clock 22, and a reset signal 40 to a clock transfer circuit 1000. Further, the system control unit 400 outputs the write clock 12 and the read clock 22 under phase management, and further outputs a reset signal 40 in a timely manner.
[0004]
Flip flop 200 latches input data 10 in response to write clock signal 12 and outputs write data 201. Write address counter 110 generates an address in response to write clock signal 12, and read address counter 120 generates an address in response to read clock signal 22. Write / read control section 130 generates address signal WAD based on write address signal 15 and generates address signal RAD based on read address signal 25.
[0005]
The memory means 100 can perform writing and reading independently of each other. For example, the memory means 100 is a dual port memory, and writes the write data 201 to any of the unit memory units 10a to 10d and the unit memory units 10a to 10d. And a switch circuit 103 for selecting from which of the unit memory units 101a to 101d the read data 301 is to be read. The flip-flop 300 latches the read data 301 in response to the read clock 22, and sets the read data 301 as the output data 20.
[0006]
Next, the operation will be described. First, the reset signal 40 is supplied from the system control unit 400 to the write address counter 110 and the read address counter 120 to be initialized. As a result, the address value of the address signal WAD generated by the write / read control unit 130 is sufficiently separated from the address value of the address signal RAD.
[0007]
Input data 10 is latched by flip-flop 200 and provided to memory means 100. In the memory unit 100, the supplied write data 201 is written to any of the unit memory units 10a to 10d specified by the address signal WAD. Further, the read data 301 is read from any of the unit memory sections 10 a to 10 d specified by the address signal RAD, and is supplied to the flip-flop 300. The flip-flop 300 outputs the read data 301 supplied from the memory means 100 as output data 20 to the outside.
[0008]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 8-274585 (No.
[Problems to be solved by the invention]
However, in the prior art described above, the distance between the write address 15 and the read address 16 is set by initializing with the reset signal 40 from the system control unit 400, and thereafter, the write clock 12 and the write clock 12 are set in the system control unit 400. Since the phase of the read clock 22 is managed, there is a problem that a circuit for that is required.
[0010]
Therefore, an object of the present invention is to change the access area at the time of reading or the access area at the time of writing in the memory even if the phases of the write clock signal and the read clock signal change, thereby enabling normal operation with a small amount of hardware. Another object of the present invention is to provide a clock transfer circuit capable of reading out various frame data.
[0011]
[Means for Solving the Problems]
A first clock transfer circuit according to the present invention provides an upper write address designating an address area to be written to a 2-port RAM having a plurality of address areas corresponding to frames and capable of independently writing and reading. Monitoring is performed, an upper read address not overlapping with the upper write address is generated, and data is read from an address area specified by the upper read address.
[0012]
More specifically, a first clock transfer circuit according to the present invention includes a two-port RAM (1 in FIG. 1) having a plurality of address areas corresponding to frames and capable of independently writing and reading, and a write frame pulse signal. A writing means (2 in FIG. 1) for writing frame data (10 in FIG. 1) to the 2-port RAM based on (11 in FIG. 1) and a write clock signal (12 in FIG. 1), and a reading frame pulse signal (FIG. 1). 1 (21) and a read means (3 in FIG. 1) for reading frame data (20 in FIG. 1) from the 2-port RAM based on a read clock signal (22 in FIG. 1), and a read control means (FIG. 1) for arbitrating the read means The writing means stores an upper write address (14 in FIG. 1) indicating an address area of the 2-port RAM and an address corresponding to a time slot of input frame data (10 in FIG. 1). It is possible to generate the lower write address (13 in FIG. 1) and write the input data (10 in FIG. 1) to the address corresponding to the lower write address in the address area corresponding to the upper write address. The read control means monitors the upper write address, and for each read control signal (30 in FIG. 1) inputted immediately before the read frame pulse signal from the read means, the upper read address which does not overlap with the upper write address. (24 in FIG. 1) can be generated, and the reading means includes a lower read address (23 in FIG. 1) indicating an address corresponding to a time slot of the output frame data (20 in FIG. 1) and a read control signal. And the data (20 in FIG. 1) can be read from the address of the 2-port RAM corresponding to the lower read address in the frame area corresponding to the read upper address. Ri, characterized in that as can absorb the change of the write clock and the read clock phase changing carrying clock with priority write data (10 in Fig. 1).
[0013]
A second clock transfer circuit according to the present invention monitors an upper read address designating an address area to be read for a 2-port RAM having a plurality of address areas corresponding to frames and capable of independently writing and reading. An upper write address that does not overlap with the upper read address is generated, and data is written to an address area specified by the upper write address.
[0014]
More specifically, the second clock transfer circuit of the present invention includes a two-port RAM (1 in FIG. 5) having a plurality of address areas corresponding to frames and capable of independently writing and reading, and a read frame pulse signal ( Reading means (3 in FIG. 5) for reading out frame data (20 in FIG. 5) from the 2-port RAM based on 21) in FIG. 5 and a read clock signal (22 in FIG. 5), and a write frame pulse signal (3 in FIG. 5). 11) Writing means (2 in FIG. 5) for writing frame data (10 in FIG. 5) to the 2-port RAM based on the write clock signal (12 in FIG. 5), and write control means for arbitrating the writing means (5 in FIG. 5), and the reading means stores an upper read address (24 in FIG. 5) indicating an address area of the 2-port RAM and an address corresponding to a time slot of output frame data (20 in FIG. 5). The lower read address (23 in FIG. 5) is generated, and the output data (20 in FIG. 5) can be read from the address corresponding to the lower read address in the address area corresponding to the upper read address. The write control unit monitors the upper read address, and for each write control signal (31 in FIG. 5) input immediately before the write frame pulse signal from the write unit, the upper write address which does not overlap with the upper read address. (14 in FIG. 5), and the writing means writes a lower write address (13 in FIG. 5) indicating an address corresponding to the time slot of the input frame data (10 in FIG. 5). A write control signal, and data can be written to a 2-port RAM address corresponding to a lower write address in a frame area corresponding to a write upper address. In favor of the read data (20 in Fig. 5) to absorb the change in the phase locking and the read clock, characterized in that as can changing carrying clock.
[0015]
In the present invention, the phase management of the write clock and the read clock is monitored in the write address area or the read address area, and the access area at the time of writing or the access area at the time of reading is changed so that the two do not overlap. Thus, the phase difference between the write clock and the read clock is managed. Therefore, there is no need to detect the phase monitoring by another device or circuit, and the amount of hardware can be reduced accordingly.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described.
[0017]
In a preferred embodiment, the clock transfer circuit of the present invention includes a two-port RAM having an address area for n frames of input data, and the writing means is divided into two-port RAMs designated by an upper write address. The input data is written to the address specified by the lower write address in the specified address area.
[0018]
On the other hand, the reading means reads out the data of the address specified by the lower read address from the data of the area specified by the upper read address from the read controller as output data from the 2-port RAM. The upper read address is generated in the read control unit by judging the address area divided into frame units of the 2-port RAM being written from the upper write address. For this reason, a sufficient distance between the write address and the read address is maintained for each frame.
[0019]
The clock transfer circuit of this embodiment has a read control circuit having a simple function as described above, and changes the access area at the time of reading even if the phases of the write clock signal and the read clock signal change. Thereby, normal data can be read.
[0020]
[Configuration of the embodiment]
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a clock re-routing circuit of the present invention.
[0021]
Referring to FIG. 1, the clock transfer circuit includes a two-port RAM (random access memory) 1, a write address generator 2, a read address generator 3, and a read controller 4.
[0022]
The two-port RAM 1 is, for example, a dual-port memory in which writing and reading can be performed independently of each other. As shown in FIG. 2, in the two-port RAM 1, address areas # 0 to # 3 for four frames of the input data 10 are secured, and the address area is divided for each frame. The address area to be written is specified by the upper write address 14, and the input data 10 is written to the address specified by the lower write address 13. Further, the address area to be read is specified by the upper read address 24, and the output data 20 is read from the address specified by the lower read address 23.
[0023]
The write address generator 2 generates a lower write address 13 and an upper write address 14 for the two-port RAM 1 based on the write frame pulse 11. The read address generator 3 generates a lower read address 23 to the two-port RAM 1 based on the read frame pulse 21. Further, the read address generation unit 3 sends a read control signal 30 to the read control unit 4. The read control unit 4 generates an upper read address 24 based on the read control signal 30 and the upper write address 14.
[0024]
[Operation of the embodiment]
Next, the operation of this embodiment will be described with reference to the time chart of FIG. 3 and the state transition diagram of FIG.
[0025]
FIG. 3 shows fixed-period frames A1, A2, A3, A5, A6, A7, and A8 as input data 10 input together with the write frame pulse signal 11 at times T1, T2, T3, T5, T6, T7, and T8. 3 is a time chart showing the operation of the present embodiment when one frame of the variable period frame A4 is inserted between A3 and A5. A4 has a period longer by TX than the fixed period frame.
[0026]
In FIG. 1, when a write frame pulse signal 11 is input to a write address generator 2, the write address generator 2 generates a lower write address 13 and an upper write address 14, and the upper write address 14 is designated. The input data 10 is written to the address specified by the lower write address 13 in the address area of the two-port RAM 1 to be operated.
[0027]
Referring to FIG. 3, when the write frame pulse signal 11 of the A1 frame is input to the write address generation unit 2 from time T1 to T2, the upper write address 14 becomes “1” and the address area # of the two-port RAM 1 1 is specified, and the data of the A1 frame is written to the address of the 2-port RAM 1 specified by the lower write address 13.
[0028]
During the next time T2 to T3, when the write frame pulse signal 11 of the A2 frame is input to the write address generator 2, the upper write address 14 becomes "2", and the address area # 2 of the 2-port RAM 1 is designated. A2 frame data is written to the address of the 2-port RAM 1 designated by the lower write address 13.
[0029]
Similarly, the other frames A3, A4, A5, A6, A7, and A8 are sequentially written in the address areas # 3, # 0, # 1, # 2, # 3, and # 0.
[0030]
As described above, the lower write address 13 and the upper write address 14 are managed by the write address generation unit 2, and manage which address of the two-port RAM 1 to write the input data 10 to. Here, the upper write address 14 is transmitted in frame units.
[0031]
The read control unit 4 monitors the upper write address 14, determines which address area of the two-port RAM 1 is being accessed for write, and generates the upper read address 24 at the timing of the read control signal 30. . For example, between times T2 and T3, the value of the upper write address 14 indicates “2”, the value of the upper read address 24 is initially “0”, and the value of the upper read address 24 at the timing of the read control signal 30. Transitions to “1”. From the next time T3 to T4, the value of the upper write address 14 indicates “3”, the value of the upper read address 24 is initially “1”, and the upper read address 24 becomes “1” at the timing of the read control signal 30. 2 ”.
[0032]
In the read control of the variable period frame A4 from time T4 to T5, the value of the upper write address 14 indicates “0”, the value of the upper read address 24 is initially “2”, and The read address 24 changes to “3”.
[0033]
However, at the timing of the next read control signal 30, the upper read address 24 does not transition and remains at "3". This is because the cycle of the variable cycle frame A4 is longer by TX, and if it changes to “0” here, it changes to “1” at the timing of the next read control signal 30, and the end of the time T5 to T6 This is to avoid overlapping with “1” of the upper write address 14 in the above.
[0034]
FIG. 4 is a state transition diagram of the read control unit 4 showing how the upper read address 24 changes according to the upper write address 14. In FIG. 4, for example, when the upper read address 24 is “0” and the upper write address 14 becomes “2”, the upper read address 24 transitions to “1”, and the upper read address 24 becomes “1”. , When the upper write address 14 becomes “3”, the upper read address 24 changes to “2”. When the upper read address 24 is “2”, the upper write address 14 becomes “0”. , The upper read address 24 changes to “3”. This is in agreement with the time chart shown in FIG.
[0035]
As described above, the upper read address 24 is managed by the read control unit 4 and manages which address area of the two-port RAM 2 is to be read. When the read frame pulse signal 21 is input to the read address generator 3, the read address generator 3 generates the lower read address 23, and the lower read address 23 in the address area of the 2-port RAM 1 designated by the upper read address 24 The data at the specified address is read.
[0036]
From time T2 to T3 in FIG. 3, the data of the A1 frame is output from the address of the two-port RAM 1 specified by the lower read address 23 in the address area # 1 of the two-port RAM 1 specified by the upper read address 24. From the next time T3 to T4, A2 frame data is output from the address of the 2-port RAM 1 specified by the lower read address 23 in the address area # 2 of the 2-port RAM 1 specified by the upper read address 24.
[0037]
Two readout frame pulse signals 21 are input during the readout operation period of the variable cycle frame from time T4 to time T5. When the first read frame pulse signal 21 is input, the lower read address 23 is generated by the read address generator 3 and the lower read address 23 in the address area # 3 of the 2-port RAM 1 designated by the upper read address 24 is The data of the A3 frame is output from the specified address of the 2-port RAM 1. Subsequently, when the second read frame pulse signal 21 is input, the upper read address 24 remains at “3” as described above, and is input to the read address generator 3 to specify the upper read address 24. A3 frame data is output from the address of the 2-port RAM 1 designated by the lower read address 23 in the address area # 3 of the 2-port RAM 1.
[0038]
In this manner, the lower read address 23 is managed by the read address generator 3 and manages which address is read out of the address area divided into frames of the 2-port RAM 1. As described above, even if a variable cycle frame is input such that a plurality of read frame pulse signals 21 enter the cycle, the data is written by the same operation as the fixed cycle frame. However, in such a variable cycle frame read, data in the same address area read by the upper read address 24 is read. As a result, the distance between the write address and the read address of the two-port RAM 1 is ensured.
[0039]
[Other embodiments]
Next, another embodiment of the present invention will be described.
[0040]
As another embodiment, the clock transfer circuit according to the present invention includes a two-port RAM having an address area for n frames of input data, and the writing means is designated by an upper write address from a write control unit. The input data is written to the address specified by the lower write address in the divided address area of the 2-port RAM.
[0041]
On the other hand, the reading means reads out, as output data, data at an address specified by the lower read address in an address area specified by the upper read address. The upper write address is generated in the write controller by judging an address area divided into frames of the 2-port RAM being written from the upper read address. For this reason, a sufficient distance between the write address and the read address is maintained for each frame.
[0042]
The clock transfer circuit of this embodiment has a write control circuit having a simple function as described above, so that even when the phases of the write clock signal and the read clock signal change, the access area at the time of reading is changed. By doing so, normal data can be read.
[0043]
FIG. 5 is a block diagram showing a second embodiment of the clock transfer circuit of the present invention, and FIG. 6 is a state transition diagram of a write control unit in the second embodiment, which corresponds to FIGS. ing.
[0044]
As is clear from the comparison between FIG. 5 and FIG. 1, in this embodiment, the write control unit 5 is provided instead of the read control unit 3 in FIG. 1, and the conflict between writing and reading is adjusted on the writing side. Things. Therefore, FIG. 6 is obtained by replacing “write” with “read” and “read” with “write” in FIG.
[0045]
【The invention's effect】
According to the present invention, the upper write address is monitored by the read control circuit to generate the upper read address, or the upper read address is monitored by the write control circuit to generate the upper write address. Even if the phases of the read clock signal and the read clock signal change, normal frame data is read by changing the access area at the time of reading or the access area at the time of writing, so no special phase management setting is required. Therefore, the effect that the amount of hardware can be reduced can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a clock transfer circuit according to the present invention; FIG. 2 is a diagram showing an example of division of an address area of a two-port RAM according to the present invention; FIG. FIG. 4 is a state transition diagram of the read control unit 4 in FIG. 1; FIG. 5 is a block diagram showing another embodiment of the clock transfer circuit of the present invention; FIG. State transition diagram of write control unit 5 FIG. 7 is a block diagram of a conventional clock transfer circuit.
1 2-port RAM
2 Write address generator 3 Read address generator 4 Read controller 5 Write controller 10 Input data 11 Write frame pulse signal 12 Write clock signal 13 Lower write address 14 Upper write address 15 Write address 20 Output Data 21 Read frame pulse signal 22 Read clock signal 23 Lower read address 24 Upper read address 25 Read address 30 Read control signal 31 Write control signal

Claims (4)

For a 2-port RAM having a plurality of address areas corresponding to frames and capable of independently writing and reading, an upper write address for designating an address area to be written is monitored and an upper write address which does not overlap with the upper write address is monitored. A clock transfer circuit that generates a read address and reads data from an address area specified by the upper read address. For a two-port RAM having a plurality of address areas corresponding to frames and capable of independently writing and reading, an upper read address designating an address area to be read is monitored, and an upper write that does not overlap with the upper read address is monitored. A clock transfer circuit that generates an address and writes data to an address area specified by the upper write address. A two-port RAM having a plurality of address areas corresponding to frames and capable of independently writing and reading;
Writing means for writing frame data to the two-port RAM based on a write frame pulse signal and a write clock signal;
Reading means for reading frame data from the 2-port RAM based on a read frame pulse signal and a read clock signal;
Read control means for arbitrating the read means,
The writing means generates an upper write address indicating an address area of the two-port RAM and a lower write address indicating an address corresponding to a time slot of the input frame data, and generates the lower write address corresponding to the upper write address. Input data can be written to an address corresponding to the lower write address in the address area;
The read control unit monitors the upper write address and generates an upper read address that does not overlap with the upper write address for each read control signal input immediately before the read frame pulse signal from the read unit. Is possible,
The read means generates a lower read address indicating an address corresponding to a time slot of the output frame data and the read control signal, and generates the lower read address corresponding to the lower read address in a frame area corresponding to the read upper address. It is possible to read data from the address of the 2-port RAM,
A clock transfer circuit wherein a clock change can be performed with a priority given to write data by absorbing a change in phase between a write clock and a read clock. A two-port RAM having a plurality of address areas corresponding to frames and capable of independently writing and reading;
Reading means for reading frame data from the 2-port RAM based on a read frame pulse signal and a read clock signal;
Writing means for writing frame data to the two-port RAM based on a write frame pulse signal and a write clock signal;
Writing control means for arbitrating the writing means,
The read means generates an upper read address indicating an address area of the 2-port RAM and a lower read address indicating an address corresponding to a time slot of the output frame data, and generates a lower read address in the address area corresponding to the upper read address. It is possible to read output data from an address corresponding to the lower read address of
The write control means monitors the upper read address, and for each write control signal input immediately before the write frame pulse signal from the write means, an upper write address which does not overlap with the upper read address. Can be generated,
The writing unit generates a lower write address indicating an address corresponding to a time slot of the input frame data and the write control signal, and generates the lower write address in a frame area corresponding to the write upper address. Data can be written to the address of the 2-port RAM corresponding to the address,
A clock transfer circuit wherein a clock change can be performed by absorbing a change in phase between a write clock and a read clock and giving priority to read data.

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