JP2004273586A - Pattern forming method and method of manufacturing semiconductor device using the pattern forming method - Google Patents

Abstract

A pattern forming method for improving dimensional accuracy in a resist pattern forming step using a thermal flow process is provided.
A resist pattern forming step (S01 to S06) of forming an antireflection film and a resist film on a substrate to be processed, and forming a resist pattern by subjecting the resist film to pattern exposure, baking and development processing; A monitor pattern measuring step (S07) of measuring a predetermined monitor pattern dimension after the formation of the resist pattern; and controlling conditions for heating the resist pattern based on information obtained from the monitor pattern measurement. A resist pattern deforming step (S08 to S13) of deforming the resist pattern to have a desired size.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for forming a resist pattern having a desired pattern size on a substrate to be processed, and more particularly to a pattern forming method suitable for forming a fine pattern of a semiconductor device, and manufacturing of a semiconductor device using the pattern. About the method.
[0002]
[Prior art]
2. Description of the Related Art As semiconductor devices become more highly integrated, finer patterns are required. In order to cope with such miniaturization, there has been a remarkable progress in exposure apparatus and mask making technology. For example, improvement in the performance of an exposure apparatus such as shortening the wavelength of a light source and increasing the NA of a lens, and the phase shift method And ultra-high resolution technology such as oblique incidence exposure.
[0003]
One of the methods for forming a fine pattern that cannot be formed even by these techniques is a method of performing a heat treatment on the resist pattern to deform the resist pattern to obtain a finer pattern. It has been known.
[0004]
That is, a heating process is performed on the resist pattern 102 having an opening width Wa formed on the substrate 101 to be processed as shown in FIG. 10A, and the resist pattern 102 is caused to flow (reflow) and spread in the lateral direction. Thus, a fine resist opening width Wb as shown in FIG. 10B is obtained.
[0005]
However, in this method of forming a resist pattern, if the process conditions and the like fluctuate during the operation of the apparatus, a desired pattern size cannot be obtained. For example, when the heat treatment is insufficient, FIG. In the case where the heat treatment is excessive, a resist pattern 102 having a large opening width Wc as shown in FIG. .
[0006]
In order to solve this problem, there is known a pattern forming method in which the amount of deformation of a resist is measured and feedback is performed when a desired value is reached to terminate the heat treatment (for example, Patent Document 1 and Patent Document 1). 2).
[0007]
The pattern forming method disclosed in Patent Document 1 will be described with reference to FIG. As shown in FIG. 11, a monitor pattern 103 is formed together with a resist pattern 102 on a substrate 101 to be processed, and a film thickness or an optical constant of the monitor pattern 103 is detected by a spectral ellipsometer 104.
[0008]
Next, when the resist 102 starts flowing due to the heat treatment, the resist deformation amount is indirectly measured from the change amount of the film thickness or the optical constant, and when the deformation amount reaches a desired resist deformation amount, the heat treatment is performed. The way to end.
[0009]
Similarly, in the pattern forming method disclosed in Patent Document 2, the deformation amount of the resist is indirectly measured from the change in the amplitude of the detection signal corresponding to the diffracted light obtained by irradiating the monitor pattern with laser light. When the amount of deformation reaches a desired amount of resist deformation, the heating process is completed.
[0010]
However, in the method disclosed in Patent Document 1 or Patent Document 2, a desired resist pattern dimension can be obtained in the vicinity of the monitor pattern, but in other cases, a desired resist pattern dimension cannot be obtained. There is a problem that it is not possible to cope with variations in the in-plane distribution of the processing substrate.
[0011]
Because there is a process variation factor in each of the normal lithography steps of resist coating, exposure, baking, and development processing, the dimensional variation of the resist pattern is already within the surface of the substrate to be processed before the heat treatment. This is because it exists between the substrates to be processed.
[0012]
This dimensional variation is not improved by the feedback method disclosed in Patent Document 1 or Patent Document 2.
[0013]
Further, since the amount of deformation of the resist is not always stable in the surface of the substrate to be processed due to the unevenness of the temperature distribution of the heat treatment apparatus, a desired pattern size cannot be finally obtained and some defects occur. As a result, there is a problem that a rework rate in a lithography process is increased in order to rescue a substrate to be processed having a pattern dimension defect.
[0014]
In addition, in order to indirectly measure the amount of deformation of the resist pattern in real time during the heating process, a large-scale and complicated device equipped with a precision measuring device using a laser and a controller for feedback is required. is there.
[0015]
[Patent Document 1]
JP-A-2002-64047 (page 3, FIG. 1)
[0016]
[Patent Document 2]
JP-A-2000-91203 (3 pages, FIG. 1)
[0017]
[Problems to be solved by the invention]
In the method of forming a resist pattern disclosed in Patent Documents 1 and 2 described above, variations in the resist pattern dimensions before and after the heat treatment within the surface of the substrate to be processed and between the substrates to be processed, and unevenness in the temperature distribution of the heat treatment apparatus. However, there is a problem that it is impossible to obtain a resist pattern of a desired size by suppressing these fluctuation factors and to cope with a variation in the in-plane distribution of the substrate to be processed.
[0018]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a pattern forming method capable of finally obtaining a desired pattern size in a surface of a substrate to be processed or between substrates to be processed, and a semiconductor device having stable electric characteristics. It is an object of the present invention to provide a method for producing the same.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, in the pattern forming method of the present invention, a resist pattern including a monitor pattern is formed by forming a resist film on a substrate to be processed, exposing the resist film to a pattern, and performing baking and developing treatments. Forming a resist pattern, measuring the size of the monitor pattern disposed in the resist pattern, a monitor pattern measuring step of obtaining the average value of the pattern size in the surface of the substrate to be processed, and the average value A resist pattern deforming step of controlling a heat treatment condition so that the resist pattern has a desired size by comparing the resist pattern with a predetermined reference value to deform the resist pattern.
[0020]
ADVANTAGE OF THE INVENTION According to this invention, the desired pattern with little variation of the resist pattern dimension between to-be-processed substrates can be obtained.
[0021]
According to another aspect of the present invention, there is provided a pattern forming method, comprising: forming a resist film on a substrate to be processed, exposing the resist film to a pattern, and performing baking and developing. A resist pattern forming step of forming a resist pattern including a monitor pattern, and a monitor pattern measuring step of measuring a size of the monitor pattern arranged in the resist pattern to obtain a pattern size distribution in the surface of the substrate to be processed, Comparing the in-plane distribution of the substrate to be processed with a predetermined reference value, controlling a heat treatment condition so that the resist pattern has a desired dimension, and deforming the resist pattern. It is characterized by:
[0022]
According to the present invention, it is possible to obtain a desired pattern with small variations in the size of the resist pattern in the surface of the substrate to be processed.
[0023]
In order to achieve the above object, in the method of manufacturing a semiconductor device according to the present invention, a resist pattern formed on a substrate to be processed is subjected to a heat treatment to obtain a resist pattern having a desired pattern size. A method of manufacturing a semiconductor device by processing the substrate to be processed to form a semiconductor device, the step of forming a resist pattern size of the desired pattern size, forming a resist film on the substrate to be processed A first step of forming a resist pattern including a monitor pattern by exposing the resist film to a pattern and performing a baking and developing process, and measuring the dimensions of the monitor pattern disposed in the resist pattern; A second step of obtaining an average value of pattern dimensions in the surface of the substrate to be processed, and comparing the average value with a predetermined reference value, Resist pattern is characterized by a third step of deforming the resist pattern by controlling the heat treatment conditions in a predetermined dimension.
[0024]
Still further, in order to achieve the above object, in another method for manufacturing a semiconductor device of the present invention, after a resist pattern formed on a substrate to be processed is subjected to a heat treatment to obtain a resist pattern having a desired pattern size, A method of manufacturing a semiconductor device, wherein a semiconductor device is formed by processing the substrate to be processed using the resist pattern, wherein the step of forming a resist pattern having a desired pattern size includes a step of forming a resist film on the substrate to be processed. A first step of forming a resist pattern including a monitor pattern by exposing the resist film to a pattern and performing baking and developing treatments, and measuring dimensions of the monitor pattern disposed in the resist pattern And a second step of obtaining a pattern size distribution in the surface of the substrate to be processed, Compared bets, the resist pattern is characterized by a third step of deforming the resist pattern by controlling the heat treatment conditions in a predetermined dimension.
[0025]
According to the semiconductor device of the present invention, a semiconductor device having stable electric characteristics can be obtained.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the pattern forming method of the present invention will be described with reference to the drawings.
[0027]
(First Embodiment)
FIG. 1 is a view showing a flowchart of a pattern forming method according to the first embodiment of the present invention.
[0028]
As shown in the figure, first, 20 substrates to be processed, for example, 20 silicon substrates (hereinafter simply referred to as substrates) having a 1 μm-thick silicon oxide film to be a film to be processed formed on the upper surface are prepared (first step S01). ).
[0029]
Next, an antireflection film made of an organic polymer is spin-coated on the silicon oxide film so as to have a thickness of, for example, 60 nm, and a bake treatment is performed at 190 ° C. for 60 seconds (second step S02). ).
[0030]
Subsequently, a KrF positive chemically amplified resist film is spin-coated on the anti-reflection film so as to have a film thickness of, for example, 480 nm, and is baked at 110 ° C. for 60 seconds (third step S03). .
[0031]
Next, the resist film is exposed to light using a KrF excimer laser exposure apparatus under the conditions of, for example, a halftone mask having NA = 0.68, σ = 0.75, ／ annular illumination, and a transmittance of 6%. Exposure is performed at 17 mJ / cm 2 (fourth step S04), and post-exposure baking is performed at 130 ° C. for 60 seconds (fifth step S05).
[0032]
Next, development processing is performed for 30 seconds using, for example, a 2.38 wt% aqueous solution of tetramethylammonium hydroxide (TMAH) to form a resist pattern including a contact hole pattern for a device having a diameter of 160 nm and various monitor patterns for measurement. Is performed (sixth step S06).
[0033]
Next, a monitor pattern, for example, an opening size of a contact hole is measured for all 20 substrates at 10 points by SEM (Scanning Electron Microscopy), and the average value is obtained (seventh step S07).
[0034]
Next, it is determined whether or not the average value is within a reference value determined from the process margin of the lithography process, for example, 160 ± 5 nm (eighth step S08). Based on the determination result, the contact after the pattern deformation by the heat treatment is performed. The baking temperature is set for each substrate so that the opening size of the hole approaches a desired size, for example, 120 nm as much as possible.
[0035]
FIG. 2 shows the relationship between the heat treatment conditions and the obtained contact hole opening size. FIG. 2A shows the relationship between the heating temperature and the contact hole opening size, and FIG. FIG. 4 is a diagram illustrating a relationship between a baking time and an opening size of a contact hole.
[0036]
Further, in FIG. 2A, a solid line a in the figure shows a relationship between the baking temperature and the opening size of the contact hole when the opening size of the developed contact hole is a reference value, for example, 160 nm. Is a graph showing the relationship between the baking temperature and the opening size of the contact hole when the opening size of the contact hole after development is larger than the reference value, for example, 170 nm. FIG. 9 is a diagram illustrating a relationship between a baking temperature and an opening size of a contact hole when the value is smaller than the value, for example, 150 nm.
[0037]
As is clear from FIG. 2, according to the experiment, the opening size of the contact hole becomes smaller as the baking temperature becomes higher, and the relationship is shifted substantially in parallel according to the opening size of the contact hole after development. Also, as the baking time becomes longer, the opening size of the contact hole tends to be substantially constant.
[0038]
Thus, for example, with the baking time constant, a thermal flow rate (calibration curve: dimensional change per unit temperature) can be obtained from the relationship between the baking temperature and the opening size of the contact hole, and an appropriate baking temperature can be set. . According to the experiment, a thermal flow rate of -2.7 nm / ° C was obtained.
[0039]
Therefore, when the dimension of the contact hole is within the reference value after development, for example, 160 ± 5 nm, the heat treatment is performed at the standard temperature initially set by the solid line a, for example, 162 ° C. (ninth step S09).
[0040]
On the other hand, if the value is out of the reference value, the magnitude is determined (tenth step S10). If the value is larger than the reference value, for example, 170 nm, the temperature is higher than the standard temperature based on the correlation indicated by the dashed line b. For example, a heat treatment is performed at 165 ° C. (eleventh step S11). On the contrary, when the heat treatment is smaller than the reference value, for example, 150 nm, the temperature is lower than the standard temperature based on the correlation indicated by the two-dot chain line c. For example, heat treatment is performed at 159 ° C. (twelfth step S12). This makes it possible to adjust the amount of deformation of the resist for each substrate.
[0041]
The change of the baking temperature can be easily performed by preparing a plurality of hot plates set to different temperatures in advance, and appropriately selecting a hot plate set to a suitable temperature from the hot plates.
[0042]
After that, the finished pattern size is inspected using the SEM (13th step S13), and non-defective products are paid out to the next step (14th step S14).
[0043]
FIG. 3 shows the results of measurement of the contact hole pattern dimensions of all the substrates after the heat treatment in comparison with the conventional method. In FIG. This is the case according to the method. As is clear from FIG. 3, according to the experiment, the variation in the average size between the substrates is reduced to one third as compared with the conventional method.
[0044]
As described above, in the pattern forming method according to the first embodiment, in the resist pattern deformation step, the baking temperature is adjusted for each substrate by a feedforward method so as to cancel out the variation in the resist pattern dimensions after development. The amount of deformation of the resist is controlled by adjustment.
[0045]
Accordingly, the dimensional accuracy of the resist pattern is improved, and a desired pattern with small variations in the resist pattern dimension between substrates can be obtained.
[0046]
Further, there is no need for a large-scale and complicated apparatus for measuring and feeding back the amount of deformation of the resist pattern in real time during the heating process.
[0047]
In this embodiment, the case where the baking temperature in the pattern deformation step is changed for each substrate is described. However, the process may be performed for each lot using a plurality of substrates as a unit.
[0048]
As the baking processing conditions, parameters other than the temperature, such as baking time and baking atmosphere (in the air, nitrogen purge, etc.), may be changed. Further, the measurement of the monitor pattern and the heating of the pattern deformation are repeated a plurality of times. You can do it.
[0049]
(Second embodiment)
FIG. 4 is a view showing a flowchart of a pattern forming method according to the second embodiment of the present invention.
[0050]
In the present embodiment, the same steps as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0051]
As shown in FIG. 4, the second embodiment differs from the first embodiment in that the distribution of monitor pattern dimensions after development is determined in the plane of the substrate, and the temperature distribution is such that the distribution in the plane is offset. A heat treatment using a hot plate having
[0052]
That is, by using a hot plate having a plurality of built-in heaters, the in-plane temperature distribution of the hot plate is controlled so as to offset the in-plane distribution of the monitor pattern dimension to improve the uniformity of the resist pattern dimension within the substrate plane. can do.
[0053]
First, as in the case of the first embodiment, for example, 20 substrates on which a silicon oxide film having a thickness of 1 μm is formed are prepared, and an antireflection film and a KrF positive chemically amplified resist film are formed thereon. Are formed in this order, pattern exposure, post-exposure bake and development processing are performed, for example, a line in which the line width is gradually reduced to a line object across a center line having a constant pitch of 130 nm and the largest line width. A monitor pattern in which an and space (hereinafter, referred to as L / S) pattern was arranged was formed.
[0054]
This monitor pattern is called a dose meter. When light is irradiated on the monitor pattern, the monitor pattern acts as a diffraction grating, and generates 0-order diffracted light and high-order diffracted light (mainly, primary light).
[0055]
Next, when only the zero-order diffracted light is taken out through the slit and exposed on the resist, a rectangular pattern in which a line of a monitor pattern whose resolution gradually decreases in a line-symmetrical manner across the central space is resolved. The shape pattern is exposed.
[0056]
Since the width of this rectangular pattern is proportional to the effective exposure amount due to only the 0th-order diffracted light, this method can determine the effective exposure amount independent of focus. Since this pattern width is several to ten μm, it is easy to measure optically.
[0057]
Therefore, if the relationship between the effective exposure amount and the actual resist pattern size is determined in advance, by measuring the width of the resolved rectangular pattern, the size of the resist pattern actually resolved on the resist can be determined. Can be converted.
[0058]
Therefore, the in-plane distribution of the resist pattern dimensions can be quickly obtained without directly measuring the nanometer (nm) resist pattern dimensions using the SEM.
[0059]
In the present embodiment, the in-plane distribution of the pattern dimensions was obtained by measuring the effective exposure amount at 50 points in the plane for all 20 substrates (15th step S15).
[0060]
Next, it is determined whether the in-plane distribution of the substrate is within the reference value (sixteenth step S16). If the distribution is within the reference value, heat treatment is performed using a hot plate set to a standard temperature distribution (first step). 17 step S17).
[0061]
On the other hand, if the in-plane distribution of the wafer is outside the reference value, a heating process is performed using a hot plate set to a temperature distribution that cancels out the in-plane distribution of the substrate (18th step S18).
[0062]
5A and 5B are views showing a hot plate having a temperature distribution that cancels out the in-plane distribution of the substrate. FIG. 5A is a plan view showing an arrangement of heaters, and FIG. 3) is a cross-sectional view taken along line AA of FIG.
[0063]
As shown in the figure, a plurality of heaters 12, for example, 36 heaters, are built in the hot plate 11. The surroundings of each heater 12 are covered with a heat insulating material 13 and connected to a power supply 14, so that the heater temperature can be set individually. A substrate 16 is placed on a top plate 15 that covers the heater 12, and a heating process is performed.
[0064]
FIG. 6 is a view showing a heat treatment step for deforming the resist using the hot plate 11, and FIG. 6 (a) is a view showing a distribution of monitor pattern dimensions in a wafer surface after development, and FIG. 6 (b). FIG. 3 is a diagram showing a temperature distribution of the hot plate 11.
[0065]
As shown in the figure, when the monitor pattern dimensions after development include an area 17 within the reference value, an area 18 larger than the reference value, and an area 19 smaller than the reference value and there is an in-plane distribution of the substrate, The in-plane temperature distribution is set so as to offset the in-plane distribution of the monitor pattern dimensions.
[0066]
That is, the temperature of the heater 20 corresponding to the area 17 where the monitor pattern size is within the reference value is set to the standard temperature, and the temperature of the heater 21 corresponding to the area 18 where the monitor pattern size is larger than the reference value is set to the higher temperature. The temperature of the heater 22 corresponding to the area 19 where the pattern size is smaller than the reference value is set to a temperature lower than the standard.
[0067]
By placing the substrate 16 on the hot plate 11 having this temperature distribution and performing the heat treatment, it is possible to cancel out the distribution of the monitor pattern dimension in the substrate plane and make it uniform.
[0068]
Further, the change of the heating temperature distribution can also be performed by selecting a hot plate set to a suitable temperature distribution from a plurality of hot plates previously set to different temperature distributions.
[0069]
FIG. 7 shows the result of measuring the dimensions of the monitor pattern after the heat treatment for all the substrates in comparison with the conventional method. In FIG. This is the case according to the method. As is clear from FIG. 7, according to the experiment, the variation in the substrate surface is reduced to 2/3 as compared with the conventional method.
[0070]
The target value of the dimension of the monitor pattern after the heat treatment is a line width of 160 nm and a space width of 100 nm (L / S), whereas the average values of the actually measured pattern dimensions are a line width of 158 nm and a space width of 102 nm (L / S). L / S), which was almost the target value.
[0071]
As described above, in the pattern forming method according to the second embodiment, in the resist pattern deformation step, the in-plane distribution of the resist pattern dimension after development is canceled for each substrate to be processed by the feedforward method. In addition, since the in-plane distribution of the heating temperature of the hot plate 11 is adjusted to control the in-plane distribution of the resist deformation, the variation in the resist pattern dimension in the substrate is improved.
[0072]
Therefore, the dimensional accuracy of the resist pattern is improved, and a desired pattern with small variations in the resist pattern dimension within the substrate surface can be obtained.
[0073]
Further, there is no need for a large-scale and complicated apparatus for measuring and feeding back the amount of deformation of the resist pattern in real time during the heating process.
[0074]
(Modification 1 of Second Embodiment)
FIG. 8 is a plan view of a hot plate illustrating a first modification of the second embodiment of the present invention. This modification differs from the second embodiment in that the heater has a ring shape, an arc shape, or a combination thereof.
[0075]
That is, in the hot plate 11 of the present modification, as shown in FIG. 8A, a total of 32 hot-plates 11 are coaxially divided into four in the radial direction and eight in the circumferential direction. An arc-shaped heater 31 is arranged.
[0076]
Each arc-shaped heater 31 is covered with a heat insulating material (not shown) and connected to a power supply (not shown) so that the heater temperature can be set individually. A substrate (not shown) is placed on a top plate (not shown) that covers the heater 31, and a heating process is performed.
[0077]
8 (b), three ring-shaped heaters 32 are coaxially arranged and an arc-shaped heater 31 divided into four at the outermost periphery in the circumferential direction. In FIG. 8 (c), four heaters are coaxially arranged. Is disposed. Each of the arc-shaped heater 31 and the ring-shaped heater 32 is covered with a heat insulating material (not shown) and connected to a power supply (not shown) so that the heater temperature can be set individually. .
[0078]
Thus, the temperature distribution can be easily adjusted by making the heater ring-shaped or arc-shaped or a combination thereof, which is particularly effective when the in-plane distribution of the resist pattern dimension is concentric.
[0079]
As described above, in the above-described modified example 2, in the resist pattern deforming step, the hot plate of the hot plate is so formed as to offset the in-plane distribution of the developed resist pattern dimensions for each of the substrates to be processed by the feedforward method. Since the amount of resist deformation is controlled by adjusting the in-plane distribution of the heating temperature, variations in the resist pattern dimensions within the substrate surface are improved.
[0080]
In the present modification, the case where the heater has a ring shape or an arc shape has been described. However, the present invention is not limited to this, and the heater may be a polygonal shape or a part of a polygonal shape formed of a rod-like heater.
[0081]
(Modification 2 of the second embodiment)
In the modified example 2 of the second embodiment of the present invention, in the post-exposure bake step, the opening size of the developed resist pattern is finished larger as the bake temperature is higher. 5 or 8 used in a post-exposure bake step as a hot plate having a temperature distribution that cancels out the in-plane distribution of the wafer, utilizing the contradictory temperature dependency that the opening size of the resist pattern becomes smaller as the height becomes higher. Is used for the heat treatment in the resist pattern deformation step.
[0082]
That is, it is possible to cancel the influence of the in-plane temperature distribution of the hot plate by using the same hot plate as the hot plate in the post-exposure bake step and the resist pattern deformation step by changing only the set value of the temperature. is there.
[0083]
As described above, in Modification 2 described above, the baking after exposure and the heat treatment for resist deformation have the opposite temperature characteristics with respect to the resist pattern dimensions, and are mutually used using the same hot plate. Fluctuations are automatically canceled.
[0084]
Therefore, the uniformity of the resist pattern dimensions in the substrate surface is improved, and the number of hot plates used can be reduced.
[0085]
Further, there is an advantage that the manufacturing process is simplified because the work of finely adjusting the temperature distribution is reduced.
[0086]
In the above-described second embodiment, the in-plane temperature distribution of the hot plate having a plurality of heaters is adjusted to improve the in-plane uniformity of the substrate after the resist pattern is deformed. However, the heat treatment may be performed by combining a plurality of hot plates having different in-plane temperature distributions of the hot plates.
[0087]
Further, in the first and second embodiments described above, the case where the resist pattern is formed on the interlayer insulating film of the silicon oxide film formed on the substrate has been described, but the present invention is not limited to this. Instead, various changes can be applied.
[0088]
(Third embodiment)
Next, a method for manufacturing a semiconductor device using the pattern forming method according to the third embodiment of the present invention will be described with reference to the drawings.
[0089]
FIG. 9 is a view showing a flowchart of a method for manufacturing a semiconductor device using the pattern forming method according to the third embodiment.
[0090]
First, after a resist film is formed on a substrate according to the first to sixth steps shown in FIG. 1, a resist pattern is formed by exposing the resist film to a pattern and performing baking and developing treatments (the first step). One process) (31st step S31).
[0091]
Next, according to the seventh step shown in FIG. 1, the dimensions of the predetermined monitor pattern arranged in the resist pattern are measured, and the average value in the substrate plane is obtained (second step) (the 32nd step S32). ).
[0092]
Next, according to the eighth to fourteenth steps shown in FIG. 1, the average value in the substrate surface is compared with a predetermined reference value, and the heat treatment conditions are controlled so that the resist pattern has a desired size. To deform the resist pattern (third step) (33rd step S33).
[0093]
Next, the following various device manufacturing processes including a process of etching a film to be processed using the obtained resist pattern to form a pattern of a desired size are performed (34th step S34).
[0094]
In this step, pre-processes for manufacturing various devices are further performed. For example, in the manufacture of an insulated gate field effect transistor, gate, source, drain regions and film formation, exposure, etching, Ion implantation and the like are performed.
[0095]
Further, a step of repeating the above-described resist pattern forming steps from the 31st step to the 33rd step may be included.
[0096]
Finally, as a post-process of device manufacturing, the substrate on which the semiconductor chip is formed is diced and divided into semiconductor chips, mounted and bonded to a lead frame, and molded with resin to complete the semiconductor device.
[0097]
As described above, according to the method for manufacturing a semiconductor device using the pattern forming method according to the first embodiment, the variation in the electrical characteristics due to the variation in the resist pattern dimension between the substrates is small, and the electrical characteristics are small. Is obtained.
[0098]
Further, a semiconductor device may be manufactured by using the pattern forming method according to the second embodiment. In this case, a semiconductor device having stable electrical characteristics with little variation in electrical characteristics due to variation in resist pattern dimensions in the substrate surface can be obtained.
[0099]
【The invention's effect】
As described above, according to the pattern forming method of the present invention, a desired pattern size is finally obtained in the plane of the substrate or between the substrates.
[0100]
Therefore, according to the method of manufacturing a semiconductor device using this pattern forming method, stable electric characteristics can be obtained.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a pattern forming method according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a relationship between a heat treatment condition and a resist pattern size according to the first embodiment of the present invention. FIG. 2A is a diagram showing a relationship between a heating temperature and a resist pattern size, and FIG. (b) is a diagram showing the relationship between the heating time and the resist pattern dimensions.
FIG. 3 is a diagram showing a distribution of resist pattern dimensions between substrates according to the first embodiment of the present invention.
FIG. 4 is a flowchart illustrating a pattern forming method according to a second embodiment of the present invention.
5A and 5B are diagrams showing a hot plate according to a second embodiment of the present invention. FIG. 5A is a plan view showing the heater arrangement, and FIG. Sectional drawing cut | disconnected along the A line and seen from the arrow direction.
FIG. 6 is a view showing a heating step of deforming a resist by a hot plate according to a second embodiment of the present invention, and FIG. 6 (a) shows a distribution of monitor pattern dimensions in a substrate after development. FIG. 6B is a diagram showing the temperature distribution of the hot plate.
FIG. 7 is a diagram showing distribution of resist pattern dimensions in a substrate surface according to a second embodiment of the present invention.
8A and 8B are diagrams showing a hot plate according to a first modification of the second embodiment of the present invention, wherein FIG. 8A is a plan view showing an arc-shaped heater array, and FIG. FIG. 8C is a plan view showing a ring-shaped heater arrangement.
FIG. 9 is a view showing a flowchart of a method for manufacturing a semiconductor device using the pattern forming method according to the third embodiment of the present invention.
FIG. 10 is a schematic sectional view showing a conventional resist pattern forming method.
FIG. 11 is a schematic cross-sectional view showing a conventional pattern forming method of measuring the amount of deformation of a resist and providing feedback during a heat treatment time.
[Explanation of symbols]
11 Hot plate
12 heater
13 Insulation
14 Power supply
15 Top plate
16 substrates
17 Area within standard value
18 Area larger than the reference value
19 Area smaller than the reference value
20 Standard temperature heater
21 Heater with higher temperature than standard temperature
22 Heater lower than standard temperature
31 Arc-shaped heater
32 ring heater

Claims (14)

Forming a resist film on a substrate to be processed, a resist pattern forming step of forming a resist pattern including a monitor pattern by performing baking and developing treatment by exposing the resist film to a pattern,
A monitor pattern measuring step of measuring the dimensions of the monitor pattern arranged in the resist pattern to determine an average value of the pattern dimensions in the surface of the substrate to be processed, and comparing the average value with a predetermined reference value. A resist pattern deformation step of controlling the heat treatment conditions so that the resist pattern has a desired size to deform the resist pattern;
A pattern forming method, comprising: Forming a resist film on a substrate to be processed, a resist pattern forming step of forming a resist pattern including a monitor pattern by performing baking and developing treatment by exposing the resist film to a pattern,
A monitor pattern measuring step of measuring the size of the monitor pattern arranged in the resist pattern to obtain a pattern size distribution in the surface of the substrate to be processed,
Comparing the distribution in the substrate surface and a predetermined reference value, a resist pattern deformation step of deforming the resist pattern by controlling heat treatment conditions so that the resist pattern has a desired size,
A pattern forming method, comprising: 3. The pattern forming method according to claim 1, wherein the heat treatment in the resist pattern deformation step is performed using at least one of a bake temperature, a bake time, and a bake atmosphere as parameters. 3. The pattern forming method according to claim 1, wherein the heat treatment conditions in the resist pattern deformation step are controlled for each substrate to be processed or for each lot having a plurality of substrates as one unit. 3. The pattern forming method according to claim 2, wherein in the resist pattern deformation step, a degree of deformation of the resist pattern is changed in a plane of the substrate to be processed. 3. The pattern forming method according to claim 2, wherein the heat treatment in the resist pattern deformation step is performed using a single hot plate having a plurality of heaters. 3. The pattern forming method according to claim 2, wherein the heat treatment in the resist pattern deformation step is performed using a plurality of hot plates having different in-plane temperature distributions of the hot plates. 3. The pattern forming method according to claim 2, wherein the heat treatment in the resist pattern deformation step is performed using a hot plate used in a post-exposure bake in the resist pattern forming step. 3. The pattern forming method according to claim 1, wherein the dimension measurement of the monitor pattern is performed by pattern length measurement using an SEM. 3. The pattern forming method according to claim 1, wherein the dimension measurement of the monitor pattern is performed by optical pattern length measurement or film thickness measurement. The resist pattern deformation step is performed only on the measurement result of the dimension of the monitor pattern that is within a preset range, and the resist pattern removal step is performed on the one outside the range, and the process is repeated from the resist pattern formation step. 3. The pattern forming method according to claim 1, wherein: 3. The pattern forming method according to claim 1, wherein the monitor pattern measuring step and the resist pattern deforming step are repeatedly performed a plurality of times. Manufacturing a semiconductor device in which a resist pattern formed on a substrate to be processed is subjected to heat treatment to obtain a resist pattern having a desired pattern size, and then the substrate to be processed is processed using the resist pattern to form a semiconductor device. Method, the step of forming a resist pattern of the desired pattern size,
Forming a resist film on the substrate to be processed, a first step of forming a resist pattern including a monitor pattern by exposing the resist film to a pattern and performing baking and developing treatments;
A second step of measuring the size of the monitor pattern arranged in the resist pattern and obtaining an average value of the pattern size in the surface of the substrate to be processed;
A third step of comparing the average value with a predetermined reference value, controlling a heat treatment condition so that the resist pattern has a desired dimension, and deforming the resist pattern. Device manufacturing method. Manufacturing a semiconductor device in which a resist pattern formed on a substrate to be processed is subjected to heat treatment to obtain a resist pattern having a desired pattern size, and then the substrate to be processed is processed using the resist pattern to form a semiconductor device. A method, processing the substrate to be processed using the resist pattern to form a semiconductor device,
Forming a resist film on the substrate to be processed, a first step of forming a resist pattern including a monitor pattern by exposing the resist film to a pattern and performing baking and developing treatments;
Measuring a size of the monitor pattern arranged in the resist pattern to obtain a pattern size distribution in the surface of the substrate to be processed;
Comparing the in-plane distribution with a predetermined reference value, controlling a heat treatment condition so that the resist pattern has a desired dimension, and deforming the resist pattern;
A method for manufacturing a semiconductor device, comprising:

Images